1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Here is where the ball gets rolling as far as the kernel is concerned. 4 * When control is transferred to _start, the bootload has already 5 * loaded us to the correct address. All that's left to do here is 6 * to set up the kernel's global pointer and jump to the kernel 7 * entry point. 8 * 9 * Copyright (C) 1998-2001, 2003, 2005 Hewlett-Packard Co 10 * David Mosberger-Tang <davidm@hpl.hp.com> 11 * Stephane Eranian <eranian@hpl.hp.com> 12 * Copyright (C) 1999 VA Linux Systems 13 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com> 14 * Copyright (C) 1999 Intel Corp. 15 * Copyright (C) 1999 Asit Mallick <Asit.K.Mallick@intel.com> 16 * Copyright (C) 1999 Don Dugger <Don.Dugger@intel.com> 17 * Copyright (C) 2002 Fenghua Yu <fenghua.yu@intel.com> 18 * -Optimize __ia64_save_fpu() and __ia64_load_fpu() for Itanium 2. 19 * Copyright (C) 2004 Ashok Raj <ashok.raj@intel.com> 20 * Support for CPU Hotplug 21 */ 22 23 24#include <linux/pgtable.h> 25#include <asm/asmmacro.h> 26#include <asm/fpu.h> 27#include <asm/kregs.h> 28#include <asm/mmu_context.h> 29#include <asm/asm-offsets.h> 30#include <asm/pal.h> 31#include <asm/processor.h> 32#include <asm/ptrace.h> 33#include <asm/mca_asm.h> 34#include <linux/init.h> 35#include <linux/linkage.h> 36#include <asm/export.h> 37 38#ifdef CONFIG_HOTPLUG_CPU 39#define SAL_PSR_BITS_TO_SET \ 40 (IA64_PSR_AC | IA64_PSR_BN | IA64_PSR_MFH | IA64_PSR_MFL) 41 42#define SAVE_FROM_REG(src, ptr, dest) \ 43 mov dest=src;; \ 44 st8 [ptr]=dest,0x08 45 46#define RESTORE_REG(reg, ptr, _tmp) \ 47 ld8 _tmp=[ptr],0x08;; \ 48 mov reg=_tmp 49 50#define SAVE_BREAK_REGS(ptr, _idx, _breg, _dest)\ 51 mov ar.lc=IA64_NUM_DBG_REGS-1;; \ 52 mov _idx=0;; \ 531: \ 54 SAVE_FROM_REG(_breg[_idx], ptr, _dest);; \ 55 add _idx=1,_idx;; \ 56 br.cloop.sptk.many 1b 57 58#define RESTORE_BREAK_REGS(ptr, _idx, _breg, _tmp, _lbl)\ 59 mov ar.lc=IA64_NUM_DBG_REGS-1;; \ 60 mov _idx=0;; \ 61_lbl: RESTORE_REG(_breg[_idx], ptr, _tmp);; \ 62 add _idx=1, _idx;; \ 63 br.cloop.sptk.many _lbl 64 65#define SAVE_ONE_RR(num, _reg, _tmp) \ 66 movl _tmp=(num<<61);; \ 67 mov _reg=rr[_tmp] 68 69#define SAVE_REGION_REGS(_tmp, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7) \ 70 SAVE_ONE_RR(0,_r0, _tmp);; \ 71 SAVE_ONE_RR(1,_r1, _tmp);; \ 72 SAVE_ONE_RR(2,_r2, _tmp);; \ 73 SAVE_ONE_RR(3,_r3, _tmp);; \ 74 SAVE_ONE_RR(4,_r4, _tmp);; \ 75 SAVE_ONE_RR(5,_r5, _tmp);; \ 76 SAVE_ONE_RR(6,_r6, _tmp);; \ 77 SAVE_ONE_RR(7,_r7, _tmp);; 78 79#define STORE_REGION_REGS(ptr, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7) \ 80 st8 [ptr]=_r0, 8;; \ 81 st8 [ptr]=_r1, 8;; \ 82 st8 [ptr]=_r2, 8;; \ 83 st8 [ptr]=_r3, 8;; \ 84 st8 [ptr]=_r4, 8;; \ 85 st8 [ptr]=_r5, 8;; \ 86 st8 [ptr]=_r6, 8;; \ 87 st8 [ptr]=_r7, 8;; 88 89#define RESTORE_REGION_REGS(ptr, _idx1, _idx2, _tmp) \ 90 mov ar.lc=0x08-1;; \ 91 movl _idx1=0x00;; \ 92RestRR: \ 93 dep.z _idx2=_idx1,61,3;; \ 94 ld8 _tmp=[ptr],8;; \ 95 mov rr[_idx2]=_tmp;; \ 96 srlz.d;; \ 97 add _idx1=1,_idx1;; \ 98 br.cloop.sptk.few RestRR 99 100#define SET_AREA_FOR_BOOTING_CPU(reg1, reg2) \ 101 movl reg1=sal_state_for_booting_cpu;; \ 102 ld8 reg2=[reg1];; 103 104/* 105 * Adjust region registers saved before starting to save 106 * break regs and rest of the states that need to be preserved. 107 */ 108#define SAL_TO_OS_BOOT_HANDOFF_STATE_SAVE(_reg1,_reg2,_pred) \ 109 SAVE_FROM_REG(b0,_reg1,_reg2);; \ 110 SAVE_FROM_REG(b1,_reg1,_reg2);; \ 111 SAVE_FROM_REG(b2,_reg1,_reg2);; \ 112 SAVE_FROM_REG(b3,_reg1,_reg2);; \ 113 SAVE_FROM_REG(b4,_reg1,_reg2);; \ 114 SAVE_FROM_REG(b5,_reg1,_reg2);; \ 115 st8 [_reg1]=r1,0x08;; \ 116 st8 [_reg1]=r12,0x08;; \ 117 st8 [_reg1]=r13,0x08;; \ 118 SAVE_FROM_REG(ar.fpsr,_reg1,_reg2);; \ 119 SAVE_FROM_REG(ar.pfs,_reg1,_reg2);; \ 120 SAVE_FROM_REG(ar.rnat,_reg1,_reg2);; \ 121 SAVE_FROM_REG(ar.unat,_reg1,_reg2);; \ 122 SAVE_FROM_REG(ar.bspstore,_reg1,_reg2);; \ 123 SAVE_FROM_REG(cr.dcr,_reg1,_reg2);; \ 124 SAVE_FROM_REG(cr.iva,_reg1,_reg2);; \ 125 SAVE_FROM_REG(cr.pta,_reg1,_reg2);; \ 126 SAVE_FROM_REG(cr.itv,_reg1,_reg2);; \ 127 SAVE_FROM_REG(cr.pmv,_reg1,_reg2);; \ 128 SAVE_FROM_REG(cr.cmcv,_reg1,_reg2);; \ 129 SAVE_FROM_REG(cr.lrr0,_reg1,_reg2);; \ 130 SAVE_FROM_REG(cr.lrr1,_reg1,_reg2);; \ 131 st8 [_reg1]=r4,0x08;; \ 132 st8 [_reg1]=r5,0x08;; \ 133 st8 [_reg1]=r6,0x08;; \ 134 st8 [_reg1]=r7,0x08;; \ 135 st8 [_reg1]=_pred,0x08;; \ 136 SAVE_FROM_REG(ar.lc, _reg1, _reg2);; \ 137 stf.spill.nta [_reg1]=f2,16;; \ 138 stf.spill.nta [_reg1]=f3,16;; \ 139 stf.spill.nta [_reg1]=f4,16;; \ 140 stf.spill.nta [_reg1]=f5,16;; \ 141 stf.spill.nta [_reg1]=f16,16;; \ 142 stf.spill.nta [_reg1]=f17,16;; \ 143 stf.spill.nta [_reg1]=f18,16;; \ 144 stf.spill.nta [_reg1]=f19,16;; \ 145 stf.spill.nta [_reg1]=f20,16;; \ 146 stf.spill.nta [_reg1]=f21,16;; \ 147 stf.spill.nta [_reg1]=f22,16;; \ 148 stf.spill.nta [_reg1]=f23,16;; \ 149 stf.spill.nta [_reg1]=f24,16;; \ 150 stf.spill.nta [_reg1]=f25,16;; \ 151 stf.spill.nta [_reg1]=f26,16;; \ 152 stf.spill.nta [_reg1]=f27,16;; \ 153 stf.spill.nta [_reg1]=f28,16;; \ 154 stf.spill.nta [_reg1]=f29,16;; \ 155 stf.spill.nta [_reg1]=f30,16;; \ 156 stf.spill.nta [_reg1]=f31,16;; 157 158#else 159#define SET_AREA_FOR_BOOTING_CPU(a1, a2) 160#define SAL_TO_OS_BOOT_HANDOFF_STATE_SAVE(a1,a2, a3) 161#define SAVE_REGION_REGS(_tmp, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7) 162#define STORE_REGION_REGS(ptr, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7) 163#endif 164 165#define SET_ONE_RR(num, pgsize, _tmp1, _tmp2, vhpt) \ 166 movl _tmp1=(num << 61);; \ 167 mov _tmp2=((ia64_rid(IA64_REGION_ID_KERNEL, (num<<61)) << 8) | (pgsize << 2) | vhpt);; \ 168 mov rr[_tmp1]=_tmp2 169 170 __PAGE_ALIGNED_DATA 171 172 .global empty_zero_page 173EXPORT_SYMBOL_GPL(empty_zero_page) 174empty_zero_page: 175 .skip PAGE_SIZE 176 177 .global swapper_pg_dir 178swapper_pg_dir: 179 .skip PAGE_SIZE 180 181 .rodata 182halt_msg: 183 stringz "Halting kernel\n" 184 185 __REF 186 187 .global start_ap 188 189 /* 190 * Start the kernel. When the bootloader passes control to _start(), r28 191 * points to the address of the boot parameter area. Execution reaches 192 * here in physical mode. 193 */ 194GLOBAL_ENTRY(_start) 195start_ap: 196 .prologue 197 .save rp, r0 // terminate unwind chain with a NULL rp 198 .body 199 200 rsm psr.i | psr.ic 201 ;; 202 srlz.i 203 ;; 204 { 205 flushrs // must be first insn in group 206 srlz.i 207 } 208 ;; 209 /* 210 * Save the region registers, predicate before they get clobbered 211 */ 212 SAVE_REGION_REGS(r2, r8,r9,r10,r11,r12,r13,r14,r15); 213 mov r25=pr;; 214 215 /* 216 * Initialize kernel region registers: 217 * rr[0]: VHPT enabled, page size = PAGE_SHIFT 218 * rr[1]: VHPT enabled, page size = PAGE_SHIFT 219 * rr[2]: VHPT enabled, page size = PAGE_SHIFT 220 * rr[3]: VHPT enabled, page size = PAGE_SHIFT 221 * rr[4]: VHPT enabled, page size = PAGE_SHIFT 222 * rr[5]: VHPT enabled, page size = PAGE_SHIFT 223 * rr[6]: VHPT disabled, page size = IA64_GRANULE_SHIFT 224 * rr[7]: VHPT disabled, page size = IA64_GRANULE_SHIFT 225 * We initialize all of them to prevent inadvertently assuming 226 * something about the state of address translation early in boot. 227 */ 228 SET_ONE_RR(0, PAGE_SHIFT, r2, r16, 1);; 229 SET_ONE_RR(1, PAGE_SHIFT, r2, r16, 1);; 230 SET_ONE_RR(2, PAGE_SHIFT, r2, r16, 1);; 231 SET_ONE_RR(3, PAGE_SHIFT, r2, r16, 1);; 232 SET_ONE_RR(4, PAGE_SHIFT, r2, r16, 1);; 233 SET_ONE_RR(5, PAGE_SHIFT, r2, r16, 1);; 234 SET_ONE_RR(6, IA64_GRANULE_SHIFT, r2, r16, 0);; 235 SET_ONE_RR(7, IA64_GRANULE_SHIFT, r2, r16, 0);; 236 /* 237 * Now pin mappings into the TLB for kernel text and data 238 */ 239 mov r18=KERNEL_TR_PAGE_SHIFT<<2 240 movl r17=KERNEL_START 241 ;; 242 mov cr.itir=r18 243 mov cr.ifa=r17 244 mov r16=IA64_TR_KERNEL 245 mov r3=ip 246 movl r18=PAGE_KERNEL 247 ;; 248 dep r2=0,r3,0,KERNEL_TR_PAGE_SHIFT 249 ;; 250 or r18=r2,r18 251 ;; 252 srlz.i 253 ;; 254 itr.i itr[r16]=r18 255 ;; 256 itr.d dtr[r16]=r18 257 ;; 258 srlz.i 259 260 /* 261 * Switch into virtual mode: 262 */ 263 movl r16=(IA64_PSR_IT|IA64_PSR_IC|IA64_PSR_DT|IA64_PSR_RT|IA64_PSR_DFH|IA64_PSR_BN \ 264 |IA64_PSR_DI) 265 ;; 266 mov cr.ipsr=r16 267 movl r17=1f 268 ;; 269 mov cr.iip=r17 270 mov cr.ifs=r0 271 ;; 272 rfi 273 ;; 2741: // now we are in virtual mode 275 276 SET_AREA_FOR_BOOTING_CPU(r2, r16); 277 278 STORE_REGION_REGS(r16, r8,r9,r10,r11,r12,r13,r14,r15); 279 SAL_TO_OS_BOOT_HANDOFF_STATE_SAVE(r16,r17,r25) 280 ;; 281 282 // set IVT entry point---can't access I/O ports without it 283 movl r3=ia64_ivt 284 ;; 285 mov cr.iva=r3 286 movl r2=FPSR_DEFAULT 287 ;; 288 srlz.i 289 movl gp=__gp 290 291 mov ar.fpsr=r2 292 ;; 293 294#define isAP p2 // are we an Application Processor? 295#define isBP p3 // are we the Bootstrap Processor? 296 297#ifdef CONFIG_SMP 298 /* 299 * Find the init_task for the currently booting CPU. At poweron, and in 300 * UP mode, task_for_booting_cpu is NULL. 301 */ 302 movl r3=task_for_booting_cpu 303 ;; 304 ld8 r3=[r3] 305 movl r2=init_task 306 ;; 307 cmp.eq isBP,isAP=r3,r0 308 ;; 309(isAP) mov r2=r3 310#else 311 movl r2=init_task 312 cmp.eq isBP,isAP=r0,r0 313#endif 314 ;; 315 tpa r3=r2 // r3 == phys addr of task struct 316 mov r16=-1 317(isBP) br.cond.dpnt .load_current // BP stack is on region 5 --- no need to map it 318 319 // load mapping for stack (virtaddr in r2, physaddr in r3) 320 rsm psr.ic 321 movl r17=PAGE_KERNEL 322 ;; 323 srlz.d 324 dep r18=0,r3,0,12 325 ;; 326 or r18=r17,r18 327 dep r2=-1,r3,61,3 // IMVA of task 328 ;; 329 mov r17=rr[r2] 330 shr.u r16=r3,IA64_GRANULE_SHIFT 331 ;; 332 dep r17=0,r17,8,24 333 ;; 334 mov cr.itir=r17 335 mov cr.ifa=r2 336 337 mov r19=IA64_TR_CURRENT_STACK 338 ;; 339 itr.d dtr[r19]=r18 340 ;; 341 ssm psr.ic 342 srlz.d 343 ;; 344 345.load_current: 346 // load the "current" pointer (r13) and ar.k6 with the current task 347 mov IA64_KR(CURRENT)=r2 // virtual address 348 mov IA64_KR(CURRENT_STACK)=r16 349 mov r13=r2 350 /* 351 * Reserve space at the top of the stack for "struct pt_regs". Kernel 352 * threads don't store interesting values in that structure, but the space 353 * still needs to be there because time-critical stuff such as the context 354 * switching can be implemented more efficiently (for example, __switch_to() 355 * always sets the psr.dfh bit of the task it is switching to). 356 */ 357 358 addl r12=IA64_STK_OFFSET-IA64_PT_REGS_SIZE-16,r2 359 addl r2=IA64_RBS_OFFSET,r2 // initialize the RSE 360 mov ar.rsc=0 // place RSE in enforced lazy mode 361 ;; 362 loadrs // clear the dirty partition 363 movl r19=__phys_per_cpu_start 364 mov r18=PERCPU_PAGE_SIZE 365 ;; 366#ifndef CONFIG_SMP 367 add r19=r19,r18 368 ;; 369#else 370(isAP) br.few 2f 371 movl r20=__cpu0_per_cpu 372 ;; 373 shr.u r18=r18,3 3741: 375 ld8 r21=[r19],8;; 376 st8[r20]=r21,8 377 adds r18=-1,r18;; 378 cmp4.lt p7,p6=0,r18 379(p7) br.cond.dptk.few 1b 380 mov r19=r20 381 ;; 3822: 383#endif 384 tpa r19=r19 385 ;; 386 .pred.rel.mutex isBP,isAP 387(isBP) mov IA64_KR(PER_CPU_DATA)=r19 // per-CPU base for cpu0 388(isAP) mov IA64_KR(PER_CPU_DATA)=r0 // clear physical per-CPU base 389 ;; 390 mov ar.bspstore=r2 // establish the new RSE stack 391 ;; 392 mov ar.rsc=0x3 // place RSE in eager mode 393 394(isBP) dep r28=-1,r28,61,3 // make address virtual 395(isBP) movl r2=ia64_boot_param 396 ;; 397(isBP) st8 [r2]=r28 // save the address of the boot param area passed by the bootloader 398 399#ifdef CONFIG_SMP 400(isAP) br.call.sptk.many rp=start_secondary 401.ret0: 402(isAP) br.cond.sptk self 403#endif 404 405 // This is executed by the bootstrap processor (bsp) only: 406 407 br.call.sptk.many rp=start_kernel 408.ret2: addl r3=@ltoff(halt_msg),gp 409 ;; 410 alloc r2=ar.pfs,8,0,2,0 411 ;; 412 ld8 out0=[r3] 413 br.call.sptk.many b0=console_print 414 415self: hint @pause 416 br.sptk.many self // endless loop 417END(_start) 418 419 .text 420 421GLOBAL_ENTRY(ia64_save_debug_regs) 422 alloc r16=ar.pfs,1,0,0,0 423 mov r20=ar.lc // preserve ar.lc 424 mov ar.lc=IA64_NUM_DBG_REGS-1 425 mov r18=0 426 add r19=IA64_NUM_DBG_REGS*8,in0 427 ;; 4281: mov r16=dbr[r18] 429#ifdef CONFIG_ITANIUM 430 ;; 431 srlz.d 432#endif 433 mov r17=ibr[r18] 434 add r18=1,r18 435 ;; 436 st8.nta [in0]=r16,8 437 st8.nta [r19]=r17,8 438 br.cloop.sptk.many 1b 439 ;; 440 mov ar.lc=r20 // restore ar.lc 441 br.ret.sptk.many rp 442END(ia64_save_debug_regs) 443 444GLOBAL_ENTRY(ia64_load_debug_regs) 445 alloc r16=ar.pfs,1,0,0,0 446 lfetch.nta [in0] 447 mov r20=ar.lc // preserve ar.lc 448 add r19=IA64_NUM_DBG_REGS*8,in0 449 mov ar.lc=IA64_NUM_DBG_REGS-1 450 mov r18=-1 451 ;; 4521: ld8.nta r16=[in0],8 453 ld8.nta r17=[r19],8 454 add r18=1,r18 455 ;; 456 mov dbr[r18]=r16 457#ifdef CONFIG_ITANIUM 458 ;; 459 srlz.d // Errata 132 (NoFix status) 460#endif 461 mov ibr[r18]=r17 462 br.cloop.sptk.many 1b 463 ;; 464 mov ar.lc=r20 // restore ar.lc 465 br.ret.sptk.many rp 466END(ia64_load_debug_regs) 467 468GLOBAL_ENTRY(__ia64_save_fpu) 469 alloc r2=ar.pfs,1,4,0,0 470 adds loc0=96*16-16,in0 471 adds loc1=96*16-16-128,in0 472 ;; 473 stf.spill.nta [loc0]=f127,-256 474 stf.spill.nta [loc1]=f119,-256 475 ;; 476 stf.spill.nta [loc0]=f111,-256 477 stf.spill.nta [loc1]=f103,-256 478 ;; 479 stf.spill.nta [loc0]=f95,-256 480 stf.spill.nta [loc1]=f87,-256 481 ;; 482 stf.spill.nta [loc0]=f79,-256 483 stf.spill.nta [loc1]=f71,-256 484 ;; 485 stf.spill.nta [loc0]=f63,-256 486 stf.spill.nta [loc1]=f55,-256 487 adds loc2=96*16-32,in0 488 ;; 489 stf.spill.nta [loc0]=f47,-256 490 stf.spill.nta [loc1]=f39,-256 491 adds loc3=96*16-32-128,in0 492 ;; 493 stf.spill.nta [loc2]=f126,-256 494 stf.spill.nta [loc3]=f118,-256 495 ;; 496 stf.spill.nta [loc2]=f110,-256 497 stf.spill.nta [loc3]=f102,-256 498 ;; 499 stf.spill.nta [loc2]=f94,-256 500 stf.spill.nta [loc3]=f86,-256 501 ;; 502 stf.spill.nta [loc2]=f78,-256 503 stf.spill.nta [loc3]=f70,-256 504 ;; 505 stf.spill.nta [loc2]=f62,-256 506 stf.spill.nta [loc3]=f54,-256 507 adds loc0=96*16-48,in0 508 ;; 509 stf.spill.nta [loc2]=f46,-256 510 stf.spill.nta [loc3]=f38,-256 511 adds loc1=96*16-48-128,in0 512 ;; 513 stf.spill.nta [loc0]=f125,-256 514 stf.spill.nta [loc1]=f117,-256 515 ;; 516 stf.spill.nta [loc0]=f109,-256 517 stf.spill.nta [loc1]=f101,-256 518 ;; 519 stf.spill.nta [loc0]=f93,-256 520 stf.spill.nta [loc1]=f85,-256 521 ;; 522 stf.spill.nta [loc0]=f77,-256 523 stf.spill.nta [loc1]=f69,-256 524 ;; 525 stf.spill.nta [loc0]=f61,-256 526 stf.spill.nta [loc1]=f53,-256 527 adds loc2=96*16-64,in0 528 ;; 529 stf.spill.nta [loc0]=f45,-256 530 stf.spill.nta [loc1]=f37,-256 531 adds loc3=96*16-64-128,in0 532 ;; 533 stf.spill.nta [loc2]=f124,-256 534 stf.spill.nta [loc3]=f116,-256 535 ;; 536 stf.spill.nta [loc2]=f108,-256 537 stf.spill.nta [loc3]=f100,-256 538 ;; 539 stf.spill.nta [loc2]=f92,-256 540 stf.spill.nta [loc3]=f84,-256 541 ;; 542 stf.spill.nta [loc2]=f76,-256 543 stf.spill.nta [loc3]=f68,-256 544 ;; 545 stf.spill.nta [loc2]=f60,-256 546 stf.spill.nta [loc3]=f52,-256 547 adds loc0=96*16-80,in0 548 ;; 549 stf.spill.nta [loc2]=f44,-256 550 stf.spill.nta [loc3]=f36,-256 551 adds loc1=96*16-80-128,in0 552 ;; 553 stf.spill.nta [loc0]=f123,-256 554 stf.spill.nta [loc1]=f115,-256 555 ;; 556 stf.spill.nta [loc0]=f107,-256 557 stf.spill.nta [loc1]=f99,-256 558 ;; 559 stf.spill.nta [loc0]=f91,-256 560 stf.spill.nta [loc1]=f83,-256 561 ;; 562 stf.spill.nta [loc0]=f75,-256 563 stf.spill.nta [loc1]=f67,-256 564 ;; 565 stf.spill.nta [loc0]=f59,-256 566 stf.spill.nta [loc1]=f51,-256 567 adds loc2=96*16-96,in0 568 ;; 569 stf.spill.nta [loc0]=f43,-256 570 stf.spill.nta [loc1]=f35,-256 571 adds loc3=96*16-96-128,in0 572 ;; 573 stf.spill.nta [loc2]=f122,-256 574 stf.spill.nta [loc3]=f114,-256 575 ;; 576 stf.spill.nta [loc2]=f106,-256 577 stf.spill.nta [loc3]=f98,-256 578 ;; 579 stf.spill.nta [loc2]=f90,-256 580 stf.spill.nta [loc3]=f82,-256 581 ;; 582 stf.spill.nta [loc2]=f74,-256 583 stf.spill.nta [loc3]=f66,-256 584 ;; 585 stf.spill.nta [loc2]=f58,-256 586 stf.spill.nta [loc3]=f50,-256 587 adds loc0=96*16-112,in0 588 ;; 589 stf.spill.nta [loc2]=f42,-256 590 stf.spill.nta [loc3]=f34,-256 591 adds loc1=96*16-112-128,in0 592 ;; 593 stf.spill.nta [loc0]=f121,-256 594 stf.spill.nta [loc1]=f113,-256 595 ;; 596 stf.spill.nta [loc0]=f105,-256 597 stf.spill.nta [loc1]=f97,-256 598 ;; 599 stf.spill.nta [loc0]=f89,-256 600 stf.spill.nta [loc1]=f81,-256 601 ;; 602 stf.spill.nta [loc0]=f73,-256 603 stf.spill.nta [loc1]=f65,-256 604 ;; 605 stf.spill.nta [loc0]=f57,-256 606 stf.spill.nta [loc1]=f49,-256 607 adds loc2=96*16-128,in0 608 ;; 609 stf.spill.nta [loc0]=f41,-256 610 stf.spill.nta [loc1]=f33,-256 611 adds loc3=96*16-128-128,in0 612 ;; 613 stf.spill.nta [loc2]=f120,-256 614 stf.spill.nta [loc3]=f112,-256 615 ;; 616 stf.spill.nta [loc2]=f104,-256 617 stf.spill.nta [loc3]=f96,-256 618 ;; 619 stf.spill.nta [loc2]=f88,-256 620 stf.spill.nta [loc3]=f80,-256 621 ;; 622 stf.spill.nta [loc2]=f72,-256 623 stf.spill.nta [loc3]=f64,-256 624 ;; 625 stf.spill.nta [loc2]=f56,-256 626 stf.spill.nta [loc3]=f48,-256 627 ;; 628 stf.spill.nta [loc2]=f40 629 stf.spill.nta [loc3]=f32 630 br.ret.sptk.many rp 631END(__ia64_save_fpu) 632 633GLOBAL_ENTRY(__ia64_load_fpu) 634 alloc r2=ar.pfs,1,2,0,0 635 adds r3=128,in0 636 adds r14=256,in0 637 adds r15=384,in0 638 mov loc0=512 639 mov loc1=-1024+16 640 ;; 641 ldf.fill.nta f32=[in0],loc0 642 ldf.fill.nta f40=[ r3],loc0 643 ldf.fill.nta f48=[r14],loc0 644 ldf.fill.nta f56=[r15],loc0 645 ;; 646 ldf.fill.nta f64=[in0],loc0 647 ldf.fill.nta f72=[ r3],loc0 648 ldf.fill.nta f80=[r14],loc0 649 ldf.fill.nta f88=[r15],loc0 650 ;; 651 ldf.fill.nta f96=[in0],loc1 652 ldf.fill.nta f104=[ r3],loc1 653 ldf.fill.nta f112=[r14],loc1 654 ldf.fill.nta f120=[r15],loc1 655 ;; 656 ldf.fill.nta f33=[in0],loc0 657 ldf.fill.nta f41=[ r3],loc0 658 ldf.fill.nta f49=[r14],loc0 659 ldf.fill.nta f57=[r15],loc0 660 ;; 661 ldf.fill.nta f65=[in0],loc0 662 ldf.fill.nta f73=[ r3],loc0 663 ldf.fill.nta f81=[r14],loc0 664 ldf.fill.nta f89=[r15],loc0 665 ;; 666 ldf.fill.nta f97=[in0],loc1 667 ldf.fill.nta f105=[ r3],loc1 668 ldf.fill.nta f113=[r14],loc1 669 ldf.fill.nta f121=[r15],loc1 670 ;; 671 ldf.fill.nta f34=[in0],loc0 672 ldf.fill.nta f42=[ r3],loc0 673 ldf.fill.nta f50=[r14],loc0 674 ldf.fill.nta f58=[r15],loc0 675 ;; 676 ldf.fill.nta f66=[in0],loc0 677 ldf.fill.nta f74=[ r3],loc0 678 ldf.fill.nta f82=[r14],loc0 679 ldf.fill.nta f90=[r15],loc0 680 ;; 681 ldf.fill.nta f98=[in0],loc1 682 ldf.fill.nta f106=[ r3],loc1 683 ldf.fill.nta f114=[r14],loc1 684 ldf.fill.nta f122=[r15],loc1 685 ;; 686 ldf.fill.nta f35=[in0],loc0 687 ldf.fill.nta f43=[ r3],loc0 688 ldf.fill.nta f51=[r14],loc0 689 ldf.fill.nta f59=[r15],loc0 690 ;; 691 ldf.fill.nta f67=[in0],loc0 692 ldf.fill.nta f75=[ r3],loc0 693 ldf.fill.nta f83=[r14],loc0 694 ldf.fill.nta f91=[r15],loc0 695 ;; 696 ldf.fill.nta f99=[in0],loc1 697 ldf.fill.nta f107=[ r3],loc1 698 ldf.fill.nta f115=[r14],loc1 699 ldf.fill.nta f123=[r15],loc1 700 ;; 701 ldf.fill.nta f36=[in0],loc0 702 ldf.fill.nta f44=[ r3],loc0 703 ldf.fill.nta f52=[r14],loc0 704 ldf.fill.nta f60=[r15],loc0 705 ;; 706 ldf.fill.nta f68=[in0],loc0 707 ldf.fill.nta f76=[ r3],loc0 708 ldf.fill.nta f84=[r14],loc0 709 ldf.fill.nta f92=[r15],loc0 710 ;; 711 ldf.fill.nta f100=[in0],loc1 712 ldf.fill.nta f108=[ r3],loc1 713 ldf.fill.nta f116=[r14],loc1 714 ldf.fill.nta f124=[r15],loc1 715 ;; 716 ldf.fill.nta f37=[in0],loc0 717 ldf.fill.nta f45=[ r3],loc0 718 ldf.fill.nta f53=[r14],loc0 719 ldf.fill.nta f61=[r15],loc0 720 ;; 721 ldf.fill.nta f69=[in0],loc0 722 ldf.fill.nta f77=[ r3],loc0 723 ldf.fill.nta f85=[r14],loc0 724 ldf.fill.nta f93=[r15],loc0 725 ;; 726 ldf.fill.nta f101=[in0],loc1 727 ldf.fill.nta f109=[ r3],loc1 728 ldf.fill.nta f117=[r14],loc1 729 ldf.fill.nta f125=[r15],loc1 730 ;; 731 ldf.fill.nta f38 =[in0],loc0 732 ldf.fill.nta f46 =[ r3],loc0 733 ldf.fill.nta f54 =[r14],loc0 734 ldf.fill.nta f62 =[r15],loc0 735 ;; 736 ldf.fill.nta f70 =[in0],loc0 737 ldf.fill.nta f78 =[ r3],loc0 738 ldf.fill.nta f86 =[r14],loc0 739 ldf.fill.nta f94 =[r15],loc0 740 ;; 741 ldf.fill.nta f102=[in0],loc1 742 ldf.fill.nta f110=[ r3],loc1 743 ldf.fill.nta f118=[r14],loc1 744 ldf.fill.nta f126=[r15],loc1 745 ;; 746 ldf.fill.nta f39 =[in0],loc0 747 ldf.fill.nta f47 =[ r3],loc0 748 ldf.fill.nta f55 =[r14],loc0 749 ldf.fill.nta f63 =[r15],loc0 750 ;; 751 ldf.fill.nta f71 =[in0],loc0 752 ldf.fill.nta f79 =[ r3],loc0 753 ldf.fill.nta f87 =[r14],loc0 754 ldf.fill.nta f95 =[r15],loc0 755 ;; 756 ldf.fill.nta f103=[in0] 757 ldf.fill.nta f111=[ r3] 758 ldf.fill.nta f119=[r14] 759 ldf.fill.nta f127=[r15] 760 br.ret.sptk.many rp 761END(__ia64_load_fpu) 762 763GLOBAL_ENTRY(__ia64_init_fpu) 764 stf.spill [sp]=f0 // M3 765 mov f32=f0 // F 766 nop.b 0 767 768 ldfps f33,f34=[sp] // M0 769 ldfps f35,f36=[sp] // M1 770 mov f37=f0 // F 771 ;; 772 773 setf.s f38=r0 // M2 774 setf.s f39=r0 // M3 775 mov f40=f0 // F 776 777 ldfps f41,f42=[sp] // M0 778 ldfps f43,f44=[sp] // M1 779 mov f45=f0 // F 780 781 setf.s f46=r0 // M2 782 setf.s f47=r0 // M3 783 mov f48=f0 // F 784 785 ldfps f49,f50=[sp] // M0 786 ldfps f51,f52=[sp] // M1 787 mov f53=f0 // F 788 789 setf.s f54=r0 // M2 790 setf.s f55=r0 // M3 791 mov f56=f0 // F 792 793 ldfps f57,f58=[sp] // M0 794 ldfps f59,f60=[sp] // M1 795 mov f61=f0 // F 796 797 setf.s f62=r0 // M2 798 setf.s f63=r0 // M3 799 mov f64=f0 // F 800 801 ldfps f65,f66=[sp] // M0 802 ldfps f67,f68=[sp] // M1 803 mov f69=f0 // F 804 805 setf.s f70=r0 // M2 806 setf.s f71=r0 // M3 807 mov f72=f0 // F 808 809 ldfps f73,f74=[sp] // M0 810 ldfps f75,f76=[sp] // M1 811 mov f77=f0 // F 812 813 setf.s f78=r0 // M2 814 setf.s f79=r0 // M3 815 mov f80=f0 // F 816 817 ldfps f81,f82=[sp] // M0 818 ldfps f83,f84=[sp] // M1 819 mov f85=f0 // F 820 821 setf.s f86=r0 // M2 822 setf.s f87=r0 // M3 823 mov f88=f0 // F 824 825 /* 826 * When the instructions are cached, it would be faster to initialize 827 * the remaining registers with simply mov instructions (F-unit). 828 * This gets the time down to ~29 cycles. However, this would use up 829 * 33 bundles, whereas continuing with the above pattern yields 830 * 10 bundles and ~30 cycles. 831 */ 832 833 ldfps f89,f90=[sp] // M0 834 ldfps f91,f92=[sp] // M1 835 mov f93=f0 // F 836 837 setf.s f94=r0 // M2 838 setf.s f95=r0 // M3 839 mov f96=f0 // F 840 841 ldfps f97,f98=[sp] // M0 842 ldfps f99,f100=[sp] // M1 843 mov f101=f0 // F 844 845 setf.s f102=r0 // M2 846 setf.s f103=r0 // M3 847 mov f104=f0 // F 848 849 ldfps f105,f106=[sp] // M0 850 ldfps f107,f108=[sp] // M1 851 mov f109=f0 // F 852 853 setf.s f110=r0 // M2 854 setf.s f111=r0 // M3 855 mov f112=f0 // F 856 857 ldfps f113,f114=[sp] // M0 858 ldfps f115,f116=[sp] // M1 859 mov f117=f0 // F 860 861 setf.s f118=r0 // M2 862 setf.s f119=r0 // M3 863 mov f120=f0 // F 864 865 ldfps f121,f122=[sp] // M0 866 ldfps f123,f124=[sp] // M1 867 mov f125=f0 // F 868 869 setf.s f126=r0 // M2 870 setf.s f127=r0 // M3 871 br.ret.sptk.many rp // F 872END(__ia64_init_fpu) 873 874/* 875 * Switch execution mode from virtual to physical 876 * 877 * Inputs: 878 * r16 = new psr to establish 879 * Output: 880 * r19 = old virtual address of ar.bsp 881 * r20 = old virtual address of sp 882 * 883 * Note: RSE must already be in enforced lazy mode 884 */ 885GLOBAL_ENTRY(ia64_switch_mode_phys) 886 { 887 rsm psr.i | psr.ic // disable interrupts and interrupt collection 888 mov r15=ip 889 } 890 ;; 891 { 892 flushrs // must be first insn in group 893 srlz.i 894 } 895 ;; 896 mov cr.ipsr=r16 // set new PSR 897 add r3=1f-ia64_switch_mode_phys,r15 898 899 mov r19=ar.bsp 900 mov r20=sp 901 mov r14=rp // get return address into a general register 902 ;; 903 904 // going to physical mode, use tpa to translate virt->phys 905 tpa r17=r19 906 tpa r3=r3 907 tpa sp=sp 908 tpa r14=r14 909 ;; 910 911 mov r18=ar.rnat // save ar.rnat 912 mov ar.bspstore=r17 // this steps on ar.rnat 913 mov cr.iip=r3 914 mov cr.ifs=r0 915 ;; 916 mov ar.rnat=r18 // restore ar.rnat 917 rfi // must be last insn in group 918 ;; 9191: mov rp=r14 920 br.ret.sptk.many rp 921END(ia64_switch_mode_phys) 922 923/* 924 * Switch execution mode from physical to virtual 925 * 926 * Inputs: 927 * r16 = new psr to establish 928 * r19 = new bspstore to establish 929 * r20 = new sp to establish 930 * 931 * Note: RSE must already be in enforced lazy mode 932 */ 933GLOBAL_ENTRY(ia64_switch_mode_virt) 934 { 935 rsm psr.i | psr.ic // disable interrupts and interrupt collection 936 mov r15=ip 937 } 938 ;; 939 { 940 flushrs // must be first insn in group 941 srlz.i 942 } 943 ;; 944 mov cr.ipsr=r16 // set new PSR 945 add r3=1f-ia64_switch_mode_virt,r15 946 947 mov r14=rp // get return address into a general register 948 ;; 949 950 // going to virtual 951 // - for code addresses, set upper bits of addr to KERNEL_START 952 // - for stack addresses, copy from input argument 953 movl r18=KERNEL_START 954 dep r3=0,r3,KERNEL_TR_PAGE_SHIFT,64-KERNEL_TR_PAGE_SHIFT 955 dep r14=0,r14,KERNEL_TR_PAGE_SHIFT,64-KERNEL_TR_PAGE_SHIFT 956 mov sp=r20 957 ;; 958 or r3=r3,r18 959 or r14=r14,r18 960 ;; 961 962 mov r18=ar.rnat // save ar.rnat 963 mov ar.bspstore=r19 // this steps on ar.rnat 964 mov cr.iip=r3 965 mov cr.ifs=r0 966 ;; 967 mov ar.rnat=r18 // restore ar.rnat 968 rfi // must be last insn in group 969 ;; 9701: mov rp=r14 971 br.ret.sptk.many rp 972END(ia64_switch_mode_virt) 973 974GLOBAL_ENTRY(ia64_delay_loop) 975 .prologue 976{ nop 0 // work around GAS unwind info generation bug... 977 .save ar.lc,r2 978 mov r2=ar.lc 979 .body 980 ;; 981 mov ar.lc=r32 982} 983 ;; 984 // force loop to be 32-byte aligned (GAS bug means we cannot use .align 985 // inside function body without corrupting unwind info). 986{ nop 0 } 9871: br.cloop.sptk.few 1b 988 ;; 989 mov ar.lc=r2 990 br.ret.sptk.many rp 991END(ia64_delay_loop) 992 993/* 994 * Return a CPU-local timestamp in nano-seconds. This timestamp is 995 * NOT synchronized across CPUs its return value must never be 996 * compared against the values returned on another CPU. The usage in 997 * kernel/sched/core.c ensures that. 998 * 999 * The return-value of sched_clock() is NOT supposed to wrap-around. 1000 * If it did, it would cause some scheduling hiccups (at the worst). 1001 * Fortunately, with a 64-bit cycle-counter ticking at 100GHz, even 1002 * that would happen only once every 5+ years. 1003 * 1004 * The code below basically calculates: 1005 * 1006 * (ia64_get_itc() * local_cpu_data->nsec_per_cyc) >> IA64_NSEC_PER_CYC_SHIFT 1007 * 1008 * except that the multiplication and the shift are done with 128-bit 1009 * intermediate precision so that we can produce a full 64-bit result. 1010 */ 1011GLOBAL_ENTRY(ia64_native_sched_clock) 1012 addl r8=THIS_CPU(ia64_cpu_info) + IA64_CPUINFO_NSEC_PER_CYC_OFFSET,r0 1013 mov.m r9=ar.itc // fetch cycle-counter (35 cyc) 1014 ;; 1015 ldf8 f8=[r8] 1016 ;; 1017 setf.sig f9=r9 // certain to stall, so issue it _after_ ldf8... 1018 ;; 1019 xmpy.lu f10=f9,f8 // calculate low 64 bits of 128-bit product (4 cyc) 1020 xmpy.hu f11=f9,f8 // calculate high 64 bits of 128-bit product 1021 ;; 1022 getf.sig r8=f10 // (5 cyc) 1023 getf.sig r9=f11 1024 ;; 1025 shrp r8=r9,r8,IA64_NSEC_PER_CYC_SHIFT 1026 br.ret.sptk.many rp 1027END(ia64_native_sched_clock) 1028 1029#ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE 1030GLOBAL_ENTRY(cycle_to_nsec) 1031 alloc r16=ar.pfs,1,0,0,0 1032 addl r8=THIS_CPU(ia64_cpu_info) + IA64_CPUINFO_NSEC_PER_CYC_OFFSET,r0 1033 ;; 1034 ldf8 f8=[r8] 1035 ;; 1036 setf.sig f9=r32 1037 ;; 1038 xmpy.lu f10=f9,f8 // calculate low 64 bits of 128-bit product (4 cyc) 1039 xmpy.hu f11=f9,f8 // calculate high 64 bits of 128-bit product 1040 ;; 1041 getf.sig r8=f10 // (5 cyc) 1042 getf.sig r9=f11 1043 ;; 1044 shrp r8=r9,r8,IA64_NSEC_PER_CYC_SHIFT 1045 br.ret.sptk.many rp 1046END(cycle_to_nsec) 1047#endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */ 1048 1049#ifdef CONFIG_IA64_BRL_EMU 1050 1051/* 1052 * Assembly routines used by brl_emu.c to set preserved register state. 1053 */ 1054 1055#define SET_REG(reg) \ 1056 GLOBAL_ENTRY(ia64_set_##reg); \ 1057 alloc r16=ar.pfs,1,0,0,0; \ 1058 mov reg=r32; \ 1059 ;; \ 1060 br.ret.sptk.many rp; \ 1061 END(ia64_set_##reg) 1062 1063SET_REG(b1); 1064SET_REG(b2); 1065SET_REG(b3); 1066SET_REG(b4); 1067SET_REG(b5); 1068 1069#endif /* CONFIG_IA64_BRL_EMU */ 1070 1071#ifdef CONFIG_SMP 1072 1073#ifdef CONFIG_HOTPLUG_CPU 1074GLOBAL_ENTRY(ia64_jump_to_sal) 1075 alloc r16=ar.pfs,1,0,0,0;; 1076 rsm psr.i | psr.ic 1077{ 1078 flushrs 1079 srlz.i 1080} 1081 tpa r25=in0 1082 movl r18=tlb_purge_done;; 1083 DATA_VA_TO_PA(r18);; 1084 mov b1=r18 // Return location 1085 movl r18=ia64_do_tlb_purge;; 1086 DATA_VA_TO_PA(r18);; 1087 mov b2=r18 // doing tlb_flush work 1088 mov ar.rsc=0 // Put RSE in enforced lazy, LE mode 1089 movl r17=1f;; 1090 DATA_VA_TO_PA(r17);; 1091 mov cr.iip=r17 1092 movl r16=SAL_PSR_BITS_TO_SET;; 1093 mov cr.ipsr=r16 1094 mov cr.ifs=r0;; 1095 rfi;; // note: this unmask MCA/INIT (psr.mc) 10961: 1097 /* 1098 * Invalidate all TLB data/inst 1099 */ 1100 br.sptk.many b2;; // jump to tlb purge code 1101 1102tlb_purge_done: 1103 RESTORE_REGION_REGS(r25, r17,r18,r19);; 1104 RESTORE_REG(b0, r25, r17);; 1105 RESTORE_REG(b1, r25, r17);; 1106 RESTORE_REG(b2, r25, r17);; 1107 RESTORE_REG(b3, r25, r17);; 1108 RESTORE_REG(b4, r25, r17);; 1109 RESTORE_REG(b5, r25, r17);; 1110 ld8 r1=[r25],0x08;; 1111 ld8 r12=[r25],0x08;; 1112 ld8 r13=[r25],0x08;; 1113 RESTORE_REG(ar.fpsr, r25, r17);; 1114 RESTORE_REG(ar.pfs, r25, r17);; 1115 RESTORE_REG(ar.rnat, r25, r17);; 1116 RESTORE_REG(ar.unat, r25, r17);; 1117 RESTORE_REG(ar.bspstore, r25, r17);; 1118 RESTORE_REG(cr.dcr, r25, r17);; 1119 RESTORE_REG(cr.iva, r25, r17);; 1120 RESTORE_REG(cr.pta, r25, r17);; 1121 srlz.d;; // required not to violate RAW dependency 1122 RESTORE_REG(cr.itv, r25, r17);; 1123 RESTORE_REG(cr.pmv, r25, r17);; 1124 RESTORE_REG(cr.cmcv, r25, r17);; 1125 RESTORE_REG(cr.lrr0, r25, r17);; 1126 RESTORE_REG(cr.lrr1, r25, r17);; 1127 ld8 r4=[r25],0x08;; 1128 ld8 r5=[r25],0x08;; 1129 ld8 r6=[r25],0x08;; 1130 ld8 r7=[r25],0x08;; 1131 ld8 r17=[r25],0x08;; 1132 mov pr=r17,-1;; 1133 RESTORE_REG(ar.lc, r25, r17);; 1134 /* 1135 * Now Restore floating point regs 1136 */ 1137 ldf.fill.nta f2=[r25],16;; 1138 ldf.fill.nta f3=[r25],16;; 1139 ldf.fill.nta f4=[r25],16;; 1140 ldf.fill.nta f5=[r25],16;; 1141 ldf.fill.nta f16=[r25],16;; 1142 ldf.fill.nta f17=[r25],16;; 1143 ldf.fill.nta f18=[r25],16;; 1144 ldf.fill.nta f19=[r25],16;; 1145 ldf.fill.nta f20=[r25],16;; 1146 ldf.fill.nta f21=[r25],16;; 1147 ldf.fill.nta f22=[r25],16;; 1148 ldf.fill.nta f23=[r25],16;; 1149 ldf.fill.nta f24=[r25],16;; 1150 ldf.fill.nta f25=[r25],16;; 1151 ldf.fill.nta f26=[r25],16;; 1152 ldf.fill.nta f27=[r25],16;; 1153 ldf.fill.nta f28=[r25],16;; 1154 ldf.fill.nta f29=[r25],16;; 1155 ldf.fill.nta f30=[r25],16;; 1156 ldf.fill.nta f31=[r25],16;; 1157 1158 /* 1159 * Now that we have done all the register restores 1160 * we are now ready for the big DIVE to SAL Land 1161 */ 1162 ssm psr.ic;; 1163 srlz.d;; 1164 br.ret.sptk.many b0;; 1165END(ia64_jump_to_sal) 1166#endif /* CONFIG_HOTPLUG_CPU */ 1167 1168#endif /* CONFIG_SMP */ 1169