1/* 2 * Here is where the ball gets rolling as far as the kernel is concerned. 3 * When control is transferred to _start, the bootload has already 4 * loaded us to the correct address. All that's left to do here is 5 * to set up the kernel's global pointer and jump to the kernel 6 * entry point. 7 * 8 * Copyright (C) 1998-2001, 2003, 2005 Hewlett-Packard Co 9 * David Mosberger-Tang <davidm@hpl.hp.com> 10 * Stephane Eranian <eranian@hpl.hp.com> 11 * Copyright (C) 1999 VA Linux Systems 12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com> 13 * Copyright (C) 1999 Intel Corp. 14 * Copyright (C) 1999 Asit Mallick <Asit.K.Mallick@intel.com> 15 * Copyright (C) 1999 Don Dugger <Don.Dugger@intel.com> 16 * Copyright (C) 2002 Fenghua Yu <fenghua.yu@intel.com> 17 * -Optimize __ia64_save_fpu() and __ia64_load_fpu() for Itanium 2. 18 * Copyright (C) 2004 Ashok Raj <ashok.raj@intel.com> 19 * Support for CPU Hotplug 20 */ 21 22 23#include <asm/asmmacro.h> 24#include <asm/fpu.h> 25#include <asm/kregs.h> 26#include <asm/mmu_context.h> 27#include <asm/asm-offsets.h> 28#include <asm/pal.h> 29#include <asm/paravirt.h> 30#include <asm/pgtable.h> 31#include <asm/processor.h> 32#include <asm/ptrace.h> 33#include <asm/system.h> 34#include <asm/mca_asm.h> 35#include <linux/init.h> 36#include <linux/linkage.h> 37 38#ifdef CONFIG_HOTPLUG_CPU 39#define SAL_PSR_BITS_TO_SET \ 40 (IA64_PSR_AC | IA64_PSR_BN | IA64_PSR_MFH | IA64_PSR_MFL) 41 42#define SAVE_FROM_REG(src, ptr, dest) \ 43 mov dest=src;; \ 44 st8 [ptr]=dest,0x08 45 46#define RESTORE_REG(reg, ptr, _tmp) \ 47 ld8 _tmp=[ptr],0x08;; \ 48 mov reg=_tmp 49 50#define SAVE_BREAK_REGS(ptr, _idx, _breg, _dest)\ 51 mov ar.lc=IA64_NUM_DBG_REGS-1;; \ 52 mov _idx=0;; \ 531: \ 54 SAVE_FROM_REG(_breg[_idx], ptr, _dest);; \ 55 add _idx=1,_idx;; \ 56 br.cloop.sptk.many 1b 57 58#define RESTORE_BREAK_REGS(ptr, _idx, _breg, _tmp, _lbl)\ 59 mov ar.lc=IA64_NUM_DBG_REGS-1;; \ 60 mov _idx=0;; \ 61_lbl: RESTORE_REG(_breg[_idx], ptr, _tmp);; \ 62 add _idx=1, _idx;; \ 63 br.cloop.sptk.many _lbl 64 65#define SAVE_ONE_RR(num, _reg, _tmp) \ 66 movl _tmp=(num<<61);; \ 67 mov _reg=rr[_tmp] 68 69#define SAVE_REGION_REGS(_tmp, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7) \ 70 SAVE_ONE_RR(0,_r0, _tmp);; \ 71 SAVE_ONE_RR(1,_r1, _tmp);; \ 72 SAVE_ONE_RR(2,_r2, _tmp);; \ 73 SAVE_ONE_RR(3,_r3, _tmp);; \ 74 SAVE_ONE_RR(4,_r4, _tmp);; \ 75 SAVE_ONE_RR(5,_r5, _tmp);; \ 76 SAVE_ONE_RR(6,_r6, _tmp);; \ 77 SAVE_ONE_RR(7,_r7, _tmp);; 78 79#define STORE_REGION_REGS(ptr, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7) \ 80 st8 [ptr]=_r0, 8;; \ 81 st8 [ptr]=_r1, 8;; \ 82 st8 [ptr]=_r2, 8;; \ 83 st8 [ptr]=_r3, 8;; \ 84 st8 [ptr]=_r4, 8;; \ 85 st8 [ptr]=_r5, 8;; \ 86 st8 [ptr]=_r6, 8;; \ 87 st8 [ptr]=_r7, 8;; 88 89#define RESTORE_REGION_REGS(ptr, _idx1, _idx2, _tmp) \ 90 mov ar.lc=0x08-1;; \ 91 movl _idx1=0x00;; \ 92RestRR: \ 93 dep.z _idx2=_idx1,61,3;; \ 94 ld8 _tmp=[ptr],8;; \ 95 mov rr[_idx2]=_tmp;; \ 96 srlz.d;; \ 97 add _idx1=1,_idx1;; \ 98 br.cloop.sptk.few RestRR 99 100#define SET_AREA_FOR_BOOTING_CPU(reg1, reg2) \ 101 movl reg1=sal_state_for_booting_cpu;; \ 102 ld8 reg2=[reg1];; 103 104/* 105 * Adjust region registers saved before starting to save 106 * break regs and rest of the states that need to be preserved. 107 */ 108#define SAL_TO_OS_BOOT_HANDOFF_STATE_SAVE(_reg1,_reg2,_pred) \ 109 SAVE_FROM_REG(b0,_reg1,_reg2);; \ 110 SAVE_FROM_REG(b1,_reg1,_reg2);; \ 111 SAVE_FROM_REG(b2,_reg1,_reg2);; \ 112 SAVE_FROM_REG(b3,_reg1,_reg2);; \ 113 SAVE_FROM_REG(b4,_reg1,_reg2);; \ 114 SAVE_FROM_REG(b5,_reg1,_reg2);; \ 115 st8 [_reg1]=r1,0x08;; \ 116 st8 [_reg1]=r12,0x08;; \ 117 st8 [_reg1]=r13,0x08;; \ 118 SAVE_FROM_REG(ar.fpsr,_reg1,_reg2);; \ 119 SAVE_FROM_REG(ar.pfs,_reg1,_reg2);; \ 120 SAVE_FROM_REG(ar.rnat,_reg1,_reg2);; \ 121 SAVE_FROM_REG(ar.unat,_reg1,_reg2);; \ 122 SAVE_FROM_REG(ar.bspstore,_reg1,_reg2);; \ 123 SAVE_FROM_REG(cr.dcr,_reg1,_reg2);; \ 124 SAVE_FROM_REG(cr.iva,_reg1,_reg2);; \ 125 SAVE_FROM_REG(cr.pta,_reg1,_reg2);; \ 126 SAVE_FROM_REG(cr.itv,_reg1,_reg2);; \ 127 SAVE_FROM_REG(cr.pmv,_reg1,_reg2);; \ 128 SAVE_FROM_REG(cr.cmcv,_reg1,_reg2);; \ 129 SAVE_FROM_REG(cr.lrr0,_reg1,_reg2);; \ 130 SAVE_FROM_REG(cr.lrr1,_reg1,_reg2);; \ 131 st8 [_reg1]=r4,0x08;; \ 132 st8 [_reg1]=r5,0x08;; \ 133 st8 [_reg1]=r6,0x08;; \ 134 st8 [_reg1]=r7,0x08;; \ 135 st8 [_reg1]=_pred,0x08;; \ 136 SAVE_FROM_REG(ar.lc, _reg1, _reg2);; \ 137 stf.spill.nta [_reg1]=f2,16;; \ 138 stf.spill.nta [_reg1]=f3,16;; \ 139 stf.spill.nta [_reg1]=f4,16;; \ 140 stf.spill.nta [_reg1]=f5,16;; \ 141 stf.spill.nta [_reg1]=f16,16;; \ 142 stf.spill.nta [_reg1]=f17,16;; \ 143 stf.spill.nta [_reg1]=f18,16;; \ 144 stf.spill.nta [_reg1]=f19,16;; \ 145 stf.spill.nta [_reg1]=f20,16;; \ 146 stf.spill.nta [_reg1]=f21,16;; \ 147 stf.spill.nta [_reg1]=f22,16;; \ 148 stf.spill.nta [_reg1]=f23,16;; \ 149 stf.spill.nta [_reg1]=f24,16;; \ 150 stf.spill.nta [_reg1]=f25,16;; \ 151 stf.spill.nta [_reg1]=f26,16;; \ 152 stf.spill.nta [_reg1]=f27,16;; \ 153 stf.spill.nta [_reg1]=f28,16;; \ 154 stf.spill.nta [_reg1]=f29,16;; \ 155 stf.spill.nta [_reg1]=f30,16;; \ 156 stf.spill.nta [_reg1]=f31,16;; 157 158#else 159#define SET_AREA_FOR_BOOTING_CPU(a1, a2) 160#define SAL_TO_OS_BOOT_HANDOFF_STATE_SAVE(a1,a2, a3) 161#define SAVE_REGION_REGS(_tmp, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7) 162#define STORE_REGION_REGS(ptr, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7) 163#endif 164 165#define SET_ONE_RR(num, pgsize, _tmp1, _tmp2, vhpt) \ 166 movl _tmp1=(num << 61);; \ 167 mov _tmp2=((ia64_rid(IA64_REGION_ID_KERNEL, (num<<61)) << 8) | (pgsize << 2) | vhpt);; \ 168 mov rr[_tmp1]=_tmp2 169 170 .section __special_page_section,"ax" 171 172 .global empty_zero_page 173empty_zero_page: 174 .skip PAGE_SIZE 175 176 .global swapper_pg_dir 177swapper_pg_dir: 178 .skip PAGE_SIZE 179 180 .rodata 181halt_msg: 182 stringz "Halting kernel\n" 183 184 .section .text.head,"ax" 185 186 .global start_ap 187 188 /* 189 * Start the kernel. When the bootloader passes control to _start(), r28 190 * points to the address of the boot parameter area. Execution reaches 191 * here in physical mode. 192 */ 193GLOBAL_ENTRY(_start) 194start_ap: 195 .prologue 196 .save rp, r0 // terminate unwind chain with a NULL rp 197 .body 198 199 rsm psr.i | psr.ic 200 ;; 201 srlz.i 202 ;; 203 { 204 flushrs // must be first insn in group 205 srlz.i 206 } 207 ;; 208 /* 209 * Save the region registers, predicate before they get clobbered 210 */ 211 SAVE_REGION_REGS(r2, r8,r9,r10,r11,r12,r13,r14,r15); 212 mov r25=pr;; 213 214 /* 215 * Initialize kernel region registers: 216 * rr[0]: VHPT enabled, page size = PAGE_SHIFT 217 * rr[1]: VHPT enabled, page size = PAGE_SHIFT 218 * rr[2]: VHPT enabled, page size = PAGE_SHIFT 219 * rr[3]: VHPT enabled, page size = PAGE_SHIFT 220 * rr[4]: VHPT enabled, page size = PAGE_SHIFT 221 * rr[5]: VHPT enabled, page size = PAGE_SHIFT 222 * rr[6]: VHPT disabled, page size = IA64_GRANULE_SHIFT 223 * rr[7]: VHPT disabled, page size = IA64_GRANULE_SHIFT 224 * We initialize all of them to prevent inadvertently assuming 225 * something about the state of address translation early in boot. 226 */ 227 SET_ONE_RR(0, PAGE_SHIFT, r2, r16, 1);; 228 SET_ONE_RR(1, PAGE_SHIFT, r2, r16, 1);; 229 SET_ONE_RR(2, PAGE_SHIFT, r2, r16, 1);; 230 SET_ONE_RR(3, PAGE_SHIFT, r2, r16, 1);; 231 SET_ONE_RR(4, PAGE_SHIFT, r2, r16, 1);; 232 SET_ONE_RR(5, PAGE_SHIFT, r2, r16, 1);; 233 SET_ONE_RR(6, IA64_GRANULE_SHIFT, r2, r16, 0);; 234 SET_ONE_RR(7, IA64_GRANULE_SHIFT, r2, r16, 0);; 235 /* 236 * Now pin mappings into the TLB for kernel text and data 237 */ 238 mov r18=KERNEL_TR_PAGE_SHIFT<<2 239 movl r17=KERNEL_START 240 ;; 241 mov cr.itir=r18 242 mov cr.ifa=r17 243 mov r16=IA64_TR_KERNEL 244 mov r3=ip 245 movl r18=PAGE_KERNEL 246 ;; 247 dep r2=0,r3,0,KERNEL_TR_PAGE_SHIFT 248 ;; 249 or r18=r2,r18 250 ;; 251 srlz.i 252 ;; 253 itr.i itr[r16]=r18 254 ;; 255 itr.d dtr[r16]=r18 256 ;; 257 srlz.i 258 259 /* 260 * Switch into virtual mode: 261 */ 262 movl r16=(IA64_PSR_IT|IA64_PSR_IC|IA64_PSR_DT|IA64_PSR_RT|IA64_PSR_DFH|IA64_PSR_BN \ 263 |IA64_PSR_DI) 264 ;; 265 mov cr.ipsr=r16 266 movl r17=1f 267 ;; 268 mov cr.iip=r17 269 mov cr.ifs=r0 270 ;; 271 rfi 272 ;; 2731: // now we are in virtual mode 274 275 SET_AREA_FOR_BOOTING_CPU(r2, r16); 276 277 STORE_REGION_REGS(r16, r8,r9,r10,r11,r12,r13,r14,r15); 278 SAL_TO_OS_BOOT_HANDOFF_STATE_SAVE(r16,r17,r25) 279 ;; 280 281 // set IVT entry point---can't access I/O ports without it 282 movl r3=ia64_ivt 283 ;; 284 mov cr.iva=r3 285 movl r2=FPSR_DEFAULT 286 ;; 287 srlz.i 288 movl gp=__gp 289 290 mov ar.fpsr=r2 291 ;; 292 293#define isAP p2 // are we an Application Processor? 294#define isBP p3 // are we the Bootstrap Processor? 295 296#ifdef CONFIG_SMP 297 /* 298 * Find the init_task for the currently booting CPU. At poweron, and in 299 * UP mode, task_for_booting_cpu is NULL. 300 */ 301 movl r3=task_for_booting_cpu 302 ;; 303 ld8 r3=[r3] 304 movl r2=init_task 305 ;; 306 cmp.eq isBP,isAP=r3,r0 307 ;; 308(isAP) mov r2=r3 309#else 310 movl r2=init_task 311 cmp.eq isBP,isAP=r0,r0 312#endif 313 ;; 314 tpa r3=r2 // r3 == phys addr of task struct 315 mov r16=-1 316(isBP) br.cond.dpnt .load_current // BP stack is on region 5 --- no need to map it 317 318 // load mapping for stack (virtaddr in r2, physaddr in r3) 319 rsm psr.ic 320 movl r17=PAGE_KERNEL 321 ;; 322 srlz.d 323 dep r18=0,r3,0,12 324 ;; 325 or r18=r17,r18 326 dep r2=-1,r3,61,3 // IMVA of task 327 ;; 328 mov r17=rr[r2] 329 shr.u r16=r3,IA64_GRANULE_SHIFT 330 ;; 331 dep r17=0,r17,8,24 332 ;; 333 mov cr.itir=r17 334 mov cr.ifa=r2 335 336 mov r19=IA64_TR_CURRENT_STACK 337 ;; 338 itr.d dtr[r19]=r18 339 ;; 340 ssm psr.ic 341 srlz.d 342 ;; 343 344.load_current: 345 // load the "current" pointer (r13) and ar.k6 with the current task 346 mov IA64_KR(CURRENT)=r2 // virtual address 347 mov IA64_KR(CURRENT_STACK)=r16 348 mov r13=r2 349 /* 350 * Reserve space at the top of the stack for "struct pt_regs". Kernel 351 * threads don't store interesting values in that structure, but the space 352 * still needs to be there because time-critical stuff such as the context 353 * switching can be implemented more efficiently (for example, __switch_to() 354 * always sets the psr.dfh bit of the task it is switching to). 355 */ 356 357 addl r12=IA64_STK_OFFSET-IA64_PT_REGS_SIZE-16,r2 358 addl r2=IA64_RBS_OFFSET,r2 // initialize the RSE 359 mov ar.rsc=0 // place RSE in enforced lazy mode 360 ;; 361 loadrs // clear the dirty partition 362 mov IA64_KR(PER_CPU_DATA)=r0 // clear physical per-CPU base 363 ;; 364 mov ar.bspstore=r2 // establish the new RSE stack 365 ;; 366 mov ar.rsc=0x3 // place RSE in eager mode 367 368(isBP) dep r28=-1,r28,61,3 // make address virtual 369(isBP) movl r2=ia64_boot_param 370 ;; 371(isBP) st8 [r2]=r28 // save the address of the boot param area passed by the bootloader 372 373#ifdef CONFIG_PARAVIRT 374 375 movl r14=hypervisor_setup_hooks 376 movl r15=hypervisor_type 377 mov r16=num_hypervisor_hooks 378 ;; 379 ld8 r2=[r15] 380 ;; 381 cmp.ltu p7,p0=r2,r16 // array size check 382 shladd r8=r2,3,r14 383 ;; 384(p7) ld8 r9=[r8] 385 ;; 386(p7) mov b1=r9 387(p7) cmp.ne.unc p7,p0=r9,r0 // no actual branch to NULL 388 ;; 389(p7) br.call.sptk.many rp=b1 390 391 __INITDATA 392 393default_setup_hook = 0 // Currently nothing needs to be done. 394 395 .weak xen_setup_hook 396 397 .global hypervisor_type 398hypervisor_type: 399 data8 PARAVIRT_HYPERVISOR_TYPE_DEFAULT 400 401 // must have the same order with PARAVIRT_HYPERVISOR_TYPE_xxx 402 403hypervisor_setup_hooks: 404 data8 default_setup_hook 405 data8 xen_setup_hook 406num_hypervisor_hooks = (. - hypervisor_setup_hooks) / 8 407 .previous 408 409#endif 410 411#ifdef CONFIG_SMP 412(isAP) br.call.sptk.many rp=start_secondary 413.ret0: 414(isAP) br.cond.sptk self 415#endif 416 417 // This is executed by the bootstrap processor (bsp) only: 418 419#ifdef CONFIG_IA64_FW_EMU 420 // initialize PAL & SAL emulator: 421 br.call.sptk.many rp=sys_fw_init 422.ret1: 423#endif 424 br.call.sptk.many rp=start_kernel 425.ret2: addl r3=@ltoff(halt_msg),gp 426 ;; 427 alloc r2=ar.pfs,8,0,2,0 428 ;; 429 ld8 out0=[r3] 430 br.call.sptk.many b0=console_print 431 432self: hint @pause 433 br.sptk.many self // endless loop 434END(_start) 435 436 .text 437 438GLOBAL_ENTRY(ia64_save_debug_regs) 439 alloc r16=ar.pfs,1,0,0,0 440 mov r20=ar.lc // preserve ar.lc 441 mov ar.lc=IA64_NUM_DBG_REGS-1 442 mov r18=0 443 add r19=IA64_NUM_DBG_REGS*8,in0 444 ;; 4451: mov r16=dbr[r18] 446#ifdef CONFIG_ITANIUM 447 ;; 448 srlz.d 449#endif 450 mov r17=ibr[r18] 451 add r18=1,r18 452 ;; 453 st8.nta [in0]=r16,8 454 st8.nta [r19]=r17,8 455 br.cloop.sptk.many 1b 456 ;; 457 mov ar.lc=r20 // restore ar.lc 458 br.ret.sptk.many rp 459END(ia64_save_debug_regs) 460 461GLOBAL_ENTRY(ia64_load_debug_regs) 462 alloc r16=ar.pfs,1,0,0,0 463 lfetch.nta [in0] 464 mov r20=ar.lc // preserve ar.lc 465 add r19=IA64_NUM_DBG_REGS*8,in0 466 mov ar.lc=IA64_NUM_DBG_REGS-1 467 mov r18=-1 468 ;; 4691: ld8.nta r16=[in0],8 470 ld8.nta r17=[r19],8 471 add r18=1,r18 472 ;; 473 mov dbr[r18]=r16 474#ifdef CONFIG_ITANIUM 475 ;; 476 srlz.d // Errata 132 (NoFix status) 477#endif 478 mov ibr[r18]=r17 479 br.cloop.sptk.many 1b 480 ;; 481 mov ar.lc=r20 // restore ar.lc 482 br.ret.sptk.many rp 483END(ia64_load_debug_regs) 484 485GLOBAL_ENTRY(__ia64_save_fpu) 486 alloc r2=ar.pfs,1,4,0,0 487 adds loc0=96*16-16,in0 488 adds loc1=96*16-16-128,in0 489 ;; 490 stf.spill.nta [loc0]=f127,-256 491 stf.spill.nta [loc1]=f119,-256 492 ;; 493 stf.spill.nta [loc0]=f111,-256 494 stf.spill.nta [loc1]=f103,-256 495 ;; 496 stf.spill.nta [loc0]=f95,-256 497 stf.spill.nta [loc1]=f87,-256 498 ;; 499 stf.spill.nta [loc0]=f79,-256 500 stf.spill.nta [loc1]=f71,-256 501 ;; 502 stf.spill.nta [loc0]=f63,-256 503 stf.spill.nta [loc1]=f55,-256 504 adds loc2=96*16-32,in0 505 ;; 506 stf.spill.nta [loc0]=f47,-256 507 stf.spill.nta [loc1]=f39,-256 508 adds loc3=96*16-32-128,in0 509 ;; 510 stf.spill.nta [loc2]=f126,-256 511 stf.spill.nta [loc3]=f118,-256 512 ;; 513 stf.spill.nta [loc2]=f110,-256 514 stf.spill.nta [loc3]=f102,-256 515 ;; 516 stf.spill.nta [loc2]=f94,-256 517 stf.spill.nta [loc3]=f86,-256 518 ;; 519 stf.spill.nta [loc2]=f78,-256 520 stf.spill.nta [loc3]=f70,-256 521 ;; 522 stf.spill.nta [loc2]=f62,-256 523 stf.spill.nta [loc3]=f54,-256 524 adds loc0=96*16-48,in0 525 ;; 526 stf.spill.nta [loc2]=f46,-256 527 stf.spill.nta [loc3]=f38,-256 528 adds loc1=96*16-48-128,in0 529 ;; 530 stf.spill.nta [loc0]=f125,-256 531 stf.spill.nta [loc1]=f117,-256 532 ;; 533 stf.spill.nta [loc0]=f109,-256 534 stf.spill.nta [loc1]=f101,-256 535 ;; 536 stf.spill.nta [loc0]=f93,-256 537 stf.spill.nta [loc1]=f85,-256 538 ;; 539 stf.spill.nta [loc0]=f77,-256 540 stf.spill.nta [loc1]=f69,-256 541 ;; 542 stf.spill.nta [loc0]=f61,-256 543 stf.spill.nta [loc1]=f53,-256 544 adds loc2=96*16-64,in0 545 ;; 546 stf.spill.nta [loc0]=f45,-256 547 stf.spill.nta [loc1]=f37,-256 548 adds loc3=96*16-64-128,in0 549 ;; 550 stf.spill.nta [loc2]=f124,-256 551 stf.spill.nta [loc3]=f116,-256 552 ;; 553 stf.spill.nta [loc2]=f108,-256 554 stf.spill.nta [loc3]=f100,-256 555 ;; 556 stf.spill.nta [loc2]=f92,-256 557 stf.spill.nta [loc3]=f84,-256 558 ;; 559 stf.spill.nta [loc2]=f76,-256 560 stf.spill.nta [loc3]=f68,-256 561 ;; 562 stf.spill.nta [loc2]=f60,-256 563 stf.spill.nta [loc3]=f52,-256 564 adds loc0=96*16-80,in0 565 ;; 566 stf.spill.nta [loc2]=f44,-256 567 stf.spill.nta [loc3]=f36,-256 568 adds loc1=96*16-80-128,in0 569 ;; 570 stf.spill.nta [loc0]=f123,-256 571 stf.spill.nta [loc1]=f115,-256 572 ;; 573 stf.spill.nta [loc0]=f107,-256 574 stf.spill.nta [loc1]=f99,-256 575 ;; 576 stf.spill.nta [loc0]=f91,-256 577 stf.spill.nta [loc1]=f83,-256 578 ;; 579 stf.spill.nta [loc0]=f75,-256 580 stf.spill.nta [loc1]=f67,-256 581 ;; 582 stf.spill.nta [loc0]=f59,-256 583 stf.spill.nta [loc1]=f51,-256 584 adds loc2=96*16-96,in0 585 ;; 586 stf.spill.nta [loc0]=f43,-256 587 stf.spill.nta [loc1]=f35,-256 588 adds loc3=96*16-96-128,in0 589 ;; 590 stf.spill.nta [loc2]=f122,-256 591 stf.spill.nta [loc3]=f114,-256 592 ;; 593 stf.spill.nta [loc2]=f106,-256 594 stf.spill.nta [loc3]=f98,-256 595 ;; 596 stf.spill.nta [loc2]=f90,-256 597 stf.spill.nta [loc3]=f82,-256 598 ;; 599 stf.spill.nta [loc2]=f74,-256 600 stf.spill.nta [loc3]=f66,-256 601 ;; 602 stf.spill.nta [loc2]=f58,-256 603 stf.spill.nta [loc3]=f50,-256 604 adds loc0=96*16-112,in0 605 ;; 606 stf.spill.nta [loc2]=f42,-256 607 stf.spill.nta [loc3]=f34,-256 608 adds loc1=96*16-112-128,in0 609 ;; 610 stf.spill.nta [loc0]=f121,-256 611 stf.spill.nta [loc1]=f113,-256 612 ;; 613 stf.spill.nta [loc0]=f105,-256 614 stf.spill.nta [loc1]=f97,-256 615 ;; 616 stf.spill.nta [loc0]=f89,-256 617 stf.spill.nta [loc1]=f81,-256 618 ;; 619 stf.spill.nta [loc0]=f73,-256 620 stf.spill.nta [loc1]=f65,-256 621 ;; 622 stf.spill.nta [loc0]=f57,-256 623 stf.spill.nta [loc1]=f49,-256 624 adds loc2=96*16-128,in0 625 ;; 626 stf.spill.nta [loc0]=f41,-256 627 stf.spill.nta [loc1]=f33,-256 628 adds loc3=96*16-128-128,in0 629 ;; 630 stf.spill.nta [loc2]=f120,-256 631 stf.spill.nta [loc3]=f112,-256 632 ;; 633 stf.spill.nta [loc2]=f104,-256 634 stf.spill.nta [loc3]=f96,-256 635 ;; 636 stf.spill.nta [loc2]=f88,-256 637 stf.spill.nta [loc3]=f80,-256 638 ;; 639 stf.spill.nta [loc2]=f72,-256 640 stf.spill.nta [loc3]=f64,-256 641 ;; 642 stf.spill.nta [loc2]=f56,-256 643 stf.spill.nta [loc3]=f48,-256 644 ;; 645 stf.spill.nta [loc2]=f40 646 stf.spill.nta [loc3]=f32 647 br.ret.sptk.many rp 648END(__ia64_save_fpu) 649 650GLOBAL_ENTRY(__ia64_load_fpu) 651 alloc r2=ar.pfs,1,2,0,0 652 adds r3=128,in0 653 adds r14=256,in0 654 adds r15=384,in0 655 mov loc0=512 656 mov loc1=-1024+16 657 ;; 658 ldf.fill.nta f32=[in0],loc0 659 ldf.fill.nta f40=[ r3],loc0 660 ldf.fill.nta f48=[r14],loc0 661 ldf.fill.nta f56=[r15],loc0 662 ;; 663 ldf.fill.nta f64=[in0],loc0 664 ldf.fill.nta f72=[ r3],loc0 665 ldf.fill.nta f80=[r14],loc0 666 ldf.fill.nta f88=[r15],loc0 667 ;; 668 ldf.fill.nta f96=[in0],loc1 669 ldf.fill.nta f104=[ r3],loc1 670 ldf.fill.nta f112=[r14],loc1 671 ldf.fill.nta f120=[r15],loc1 672 ;; 673 ldf.fill.nta f33=[in0],loc0 674 ldf.fill.nta f41=[ r3],loc0 675 ldf.fill.nta f49=[r14],loc0 676 ldf.fill.nta f57=[r15],loc0 677 ;; 678 ldf.fill.nta f65=[in0],loc0 679 ldf.fill.nta f73=[ r3],loc0 680 ldf.fill.nta f81=[r14],loc0 681 ldf.fill.nta f89=[r15],loc0 682 ;; 683 ldf.fill.nta f97=[in0],loc1 684 ldf.fill.nta f105=[ r3],loc1 685 ldf.fill.nta f113=[r14],loc1 686 ldf.fill.nta f121=[r15],loc1 687 ;; 688 ldf.fill.nta f34=[in0],loc0 689 ldf.fill.nta f42=[ r3],loc0 690 ldf.fill.nta f50=[r14],loc0 691 ldf.fill.nta f58=[r15],loc0 692 ;; 693 ldf.fill.nta f66=[in0],loc0 694 ldf.fill.nta f74=[ r3],loc0 695 ldf.fill.nta f82=[r14],loc0 696 ldf.fill.nta f90=[r15],loc0 697 ;; 698 ldf.fill.nta f98=[in0],loc1 699 ldf.fill.nta f106=[ r3],loc1 700 ldf.fill.nta f114=[r14],loc1 701 ldf.fill.nta f122=[r15],loc1 702 ;; 703 ldf.fill.nta f35=[in0],loc0 704 ldf.fill.nta f43=[ r3],loc0 705 ldf.fill.nta f51=[r14],loc0 706 ldf.fill.nta f59=[r15],loc0 707 ;; 708 ldf.fill.nta f67=[in0],loc0 709 ldf.fill.nta f75=[ r3],loc0 710 ldf.fill.nta f83=[r14],loc0 711 ldf.fill.nta f91=[r15],loc0 712 ;; 713 ldf.fill.nta f99=[in0],loc1 714 ldf.fill.nta f107=[ r3],loc1 715 ldf.fill.nta f115=[r14],loc1 716 ldf.fill.nta f123=[r15],loc1 717 ;; 718 ldf.fill.nta f36=[in0],loc0 719 ldf.fill.nta f44=[ r3],loc0 720 ldf.fill.nta f52=[r14],loc0 721 ldf.fill.nta f60=[r15],loc0 722 ;; 723 ldf.fill.nta f68=[in0],loc0 724 ldf.fill.nta f76=[ r3],loc0 725 ldf.fill.nta f84=[r14],loc0 726 ldf.fill.nta f92=[r15],loc0 727 ;; 728 ldf.fill.nta f100=[in0],loc1 729 ldf.fill.nta f108=[ r3],loc1 730 ldf.fill.nta f116=[r14],loc1 731 ldf.fill.nta f124=[r15],loc1 732 ;; 733 ldf.fill.nta f37=[in0],loc0 734 ldf.fill.nta f45=[ r3],loc0 735 ldf.fill.nta f53=[r14],loc0 736 ldf.fill.nta f61=[r15],loc0 737 ;; 738 ldf.fill.nta f69=[in0],loc0 739 ldf.fill.nta f77=[ r3],loc0 740 ldf.fill.nta f85=[r14],loc0 741 ldf.fill.nta f93=[r15],loc0 742 ;; 743 ldf.fill.nta f101=[in0],loc1 744 ldf.fill.nta f109=[ r3],loc1 745 ldf.fill.nta f117=[r14],loc1 746 ldf.fill.nta f125=[r15],loc1 747 ;; 748 ldf.fill.nta f38 =[in0],loc0 749 ldf.fill.nta f46 =[ r3],loc0 750 ldf.fill.nta f54 =[r14],loc0 751 ldf.fill.nta f62 =[r15],loc0 752 ;; 753 ldf.fill.nta f70 =[in0],loc0 754 ldf.fill.nta f78 =[ r3],loc0 755 ldf.fill.nta f86 =[r14],loc0 756 ldf.fill.nta f94 =[r15],loc0 757 ;; 758 ldf.fill.nta f102=[in0],loc1 759 ldf.fill.nta f110=[ r3],loc1 760 ldf.fill.nta f118=[r14],loc1 761 ldf.fill.nta f126=[r15],loc1 762 ;; 763 ldf.fill.nta f39 =[in0],loc0 764 ldf.fill.nta f47 =[ r3],loc0 765 ldf.fill.nta f55 =[r14],loc0 766 ldf.fill.nta f63 =[r15],loc0 767 ;; 768 ldf.fill.nta f71 =[in0],loc0 769 ldf.fill.nta f79 =[ r3],loc0 770 ldf.fill.nta f87 =[r14],loc0 771 ldf.fill.nta f95 =[r15],loc0 772 ;; 773 ldf.fill.nta f103=[in0] 774 ldf.fill.nta f111=[ r3] 775 ldf.fill.nta f119=[r14] 776 ldf.fill.nta f127=[r15] 777 br.ret.sptk.many rp 778END(__ia64_load_fpu) 779 780GLOBAL_ENTRY(__ia64_init_fpu) 781 stf.spill [sp]=f0 // M3 782 mov f32=f0 // F 783 nop.b 0 784 785 ldfps f33,f34=[sp] // M0 786 ldfps f35,f36=[sp] // M1 787 mov f37=f0 // F 788 ;; 789 790 setf.s f38=r0 // M2 791 setf.s f39=r0 // M3 792 mov f40=f0 // F 793 794 ldfps f41,f42=[sp] // M0 795 ldfps f43,f44=[sp] // M1 796 mov f45=f0 // F 797 798 setf.s f46=r0 // M2 799 setf.s f47=r0 // M3 800 mov f48=f0 // F 801 802 ldfps f49,f50=[sp] // M0 803 ldfps f51,f52=[sp] // M1 804 mov f53=f0 // F 805 806 setf.s f54=r0 // M2 807 setf.s f55=r0 // M3 808 mov f56=f0 // F 809 810 ldfps f57,f58=[sp] // M0 811 ldfps f59,f60=[sp] // M1 812 mov f61=f0 // F 813 814 setf.s f62=r0 // M2 815 setf.s f63=r0 // M3 816 mov f64=f0 // F 817 818 ldfps f65,f66=[sp] // M0 819 ldfps f67,f68=[sp] // M1 820 mov f69=f0 // F 821 822 setf.s f70=r0 // M2 823 setf.s f71=r0 // M3 824 mov f72=f0 // F 825 826 ldfps f73,f74=[sp] // M0 827 ldfps f75,f76=[sp] // M1 828 mov f77=f0 // F 829 830 setf.s f78=r0 // M2 831 setf.s f79=r0 // M3 832 mov f80=f0 // F 833 834 ldfps f81,f82=[sp] // M0 835 ldfps f83,f84=[sp] // M1 836 mov f85=f0 // F 837 838 setf.s f86=r0 // M2 839 setf.s f87=r0 // M3 840 mov f88=f0 // F 841 842 /* 843 * When the instructions are cached, it would be faster to initialize 844 * the remaining registers with simply mov instructions (F-unit). 845 * This gets the time down to ~29 cycles. However, this would use up 846 * 33 bundles, whereas continuing with the above pattern yields 847 * 10 bundles and ~30 cycles. 848 */ 849 850 ldfps f89,f90=[sp] // M0 851 ldfps f91,f92=[sp] // M1 852 mov f93=f0 // F 853 854 setf.s f94=r0 // M2 855 setf.s f95=r0 // M3 856 mov f96=f0 // F 857 858 ldfps f97,f98=[sp] // M0 859 ldfps f99,f100=[sp] // M1 860 mov f101=f0 // F 861 862 setf.s f102=r0 // M2 863 setf.s f103=r0 // M3 864 mov f104=f0 // F 865 866 ldfps f105,f106=[sp] // M0 867 ldfps f107,f108=[sp] // M1 868 mov f109=f0 // F 869 870 setf.s f110=r0 // M2 871 setf.s f111=r0 // M3 872 mov f112=f0 // F 873 874 ldfps f113,f114=[sp] // M0 875 ldfps f115,f116=[sp] // M1 876 mov f117=f0 // F 877 878 setf.s f118=r0 // M2 879 setf.s f119=r0 // M3 880 mov f120=f0 // F 881 882 ldfps f121,f122=[sp] // M0 883 ldfps f123,f124=[sp] // M1 884 mov f125=f0 // F 885 886 setf.s f126=r0 // M2 887 setf.s f127=r0 // M3 888 br.ret.sptk.many rp // F 889END(__ia64_init_fpu) 890 891/* 892 * Switch execution mode from virtual to physical 893 * 894 * Inputs: 895 * r16 = new psr to establish 896 * Output: 897 * r19 = old virtual address of ar.bsp 898 * r20 = old virtual address of sp 899 * 900 * Note: RSE must already be in enforced lazy mode 901 */ 902GLOBAL_ENTRY(ia64_switch_mode_phys) 903 { 904 rsm psr.i | psr.ic // disable interrupts and interrupt collection 905 mov r15=ip 906 } 907 ;; 908 { 909 flushrs // must be first insn in group 910 srlz.i 911 } 912 ;; 913 mov cr.ipsr=r16 // set new PSR 914 add r3=1f-ia64_switch_mode_phys,r15 915 916 mov r19=ar.bsp 917 mov r20=sp 918 mov r14=rp // get return address into a general register 919 ;; 920 921 // going to physical mode, use tpa to translate virt->phys 922 tpa r17=r19 923 tpa r3=r3 924 tpa sp=sp 925 tpa r14=r14 926 ;; 927 928 mov r18=ar.rnat // save ar.rnat 929 mov ar.bspstore=r17 // this steps on ar.rnat 930 mov cr.iip=r3 931 mov cr.ifs=r0 932 ;; 933 mov ar.rnat=r18 // restore ar.rnat 934 rfi // must be last insn in group 935 ;; 9361: mov rp=r14 937 br.ret.sptk.many rp 938END(ia64_switch_mode_phys) 939 940/* 941 * Switch execution mode from physical to virtual 942 * 943 * Inputs: 944 * r16 = new psr to establish 945 * r19 = new bspstore to establish 946 * r20 = new sp to establish 947 * 948 * Note: RSE must already be in enforced lazy mode 949 */ 950GLOBAL_ENTRY(ia64_switch_mode_virt) 951 { 952 rsm psr.i | psr.ic // disable interrupts and interrupt collection 953 mov r15=ip 954 } 955 ;; 956 { 957 flushrs // must be first insn in group 958 srlz.i 959 } 960 ;; 961 mov cr.ipsr=r16 // set new PSR 962 add r3=1f-ia64_switch_mode_virt,r15 963 964 mov r14=rp // get return address into a general register 965 ;; 966 967 // going to virtual 968 // - for code addresses, set upper bits of addr to KERNEL_START 969 // - for stack addresses, copy from input argument 970 movl r18=KERNEL_START 971 dep r3=0,r3,KERNEL_TR_PAGE_SHIFT,64-KERNEL_TR_PAGE_SHIFT 972 dep r14=0,r14,KERNEL_TR_PAGE_SHIFT,64-KERNEL_TR_PAGE_SHIFT 973 mov sp=r20 974 ;; 975 or r3=r3,r18 976 or r14=r14,r18 977 ;; 978 979 mov r18=ar.rnat // save ar.rnat 980 mov ar.bspstore=r19 // this steps on ar.rnat 981 mov cr.iip=r3 982 mov cr.ifs=r0 983 ;; 984 mov ar.rnat=r18 // restore ar.rnat 985 rfi // must be last insn in group 986 ;; 9871: mov rp=r14 988 br.ret.sptk.many rp 989END(ia64_switch_mode_virt) 990 991GLOBAL_ENTRY(ia64_delay_loop) 992 .prologue 993{ nop 0 // work around GAS unwind info generation bug... 994 .save ar.lc,r2 995 mov r2=ar.lc 996 .body 997 ;; 998 mov ar.lc=r32 999} 1000 ;; 1001 // force loop to be 32-byte aligned (GAS bug means we cannot use .align 1002 // inside function body without corrupting unwind info). 1003{ nop 0 } 10041: br.cloop.sptk.few 1b 1005 ;; 1006 mov ar.lc=r2 1007 br.ret.sptk.many rp 1008END(ia64_delay_loop) 1009 1010/* 1011 * Return a CPU-local timestamp in nano-seconds. This timestamp is 1012 * NOT synchronized across CPUs its return value must never be 1013 * compared against the values returned on another CPU. The usage in 1014 * kernel/sched.c ensures that. 1015 * 1016 * The return-value of sched_clock() is NOT supposed to wrap-around. 1017 * If it did, it would cause some scheduling hiccups (at the worst). 1018 * Fortunately, with a 64-bit cycle-counter ticking at 100GHz, even 1019 * that would happen only once every 5+ years. 1020 * 1021 * The code below basically calculates: 1022 * 1023 * (ia64_get_itc() * local_cpu_data->nsec_per_cyc) >> IA64_NSEC_PER_CYC_SHIFT 1024 * 1025 * except that the multiplication and the shift are done with 128-bit 1026 * intermediate precision so that we can produce a full 64-bit result. 1027 */ 1028GLOBAL_ENTRY(sched_clock) 1029 addl r8=THIS_CPU(cpu_info) + IA64_CPUINFO_NSEC_PER_CYC_OFFSET,r0 1030 mov.m r9=ar.itc // fetch cycle-counter (35 cyc) 1031 ;; 1032 ldf8 f8=[r8] 1033 ;; 1034 setf.sig f9=r9 // certain to stall, so issue it _after_ ldf8... 1035 ;; 1036 xmpy.lu f10=f9,f8 // calculate low 64 bits of 128-bit product (4 cyc) 1037 xmpy.hu f11=f9,f8 // calculate high 64 bits of 128-bit product 1038 ;; 1039 getf.sig r8=f10 // (5 cyc) 1040 getf.sig r9=f11 1041 ;; 1042 shrp r8=r9,r8,IA64_NSEC_PER_CYC_SHIFT 1043 br.ret.sptk.many rp 1044END(sched_clock) 1045 1046#ifdef CONFIG_VIRT_CPU_ACCOUNTING 1047GLOBAL_ENTRY(cycle_to_cputime) 1048 alloc r16=ar.pfs,1,0,0,0 1049 addl r8=THIS_CPU(cpu_info) + IA64_CPUINFO_NSEC_PER_CYC_OFFSET,r0 1050 ;; 1051 ldf8 f8=[r8] 1052 ;; 1053 setf.sig f9=r32 1054 ;; 1055 xmpy.lu f10=f9,f8 // calculate low 64 bits of 128-bit product (4 cyc) 1056 xmpy.hu f11=f9,f8 // calculate high 64 bits of 128-bit product 1057 ;; 1058 getf.sig r8=f10 // (5 cyc) 1059 getf.sig r9=f11 1060 ;; 1061 shrp r8=r9,r8,IA64_NSEC_PER_CYC_SHIFT 1062 br.ret.sptk.many rp 1063END(cycle_to_cputime) 1064#endif /* CONFIG_VIRT_CPU_ACCOUNTING */ 1065 1066GLOBAL_ENTRY(start_kernel_thread) 1067 .prologue 1068 .save rp, r0 // this is the end of the call-chain 1069 .body 1070 alloc r2 = ar.pfs, 0, 0, 2, 0 1071 mov out0 = r9 1072 mov out1 = r11;; 1073 br.call.sptk.many rp = kernel_thread_helper;; 1074 mov out0 = r8 1075 br.call.sptk.many rp = sys_exit;; 10761: br.sptk.few 1b // not reached 1077END(start_kernel_thread) 1078 1079#ifdef CONFIG_IA64_BRL_EMU 1080 1081/* 1082 * Assembly routines used by brl_emu.c to set preserved register state. 1083 */ 1084 1085#define SET_REG(reg) \ 1086 GLOBAL_ENTRY(ia64_set_##reg); \ 1087 alloc r16=ar.pfs,1,0,0,0; \ 1088 mov reg=r32; \ 1089 ;; \ 1090 br.ret.sptk.many rp; \ 1091 END(ia64_set_##reg) 1092 1093SET_REG(b1); 1094SET_REG(b2); 1095SET_REG(b3); 1096SET_REG(b4); 1097SET_REG(b5); 1098 1099#endif /* CONFIG_IA64_BRL_EMU */ 1100 1101#ifdef CONFIG_SMP 1102 /* 1103 * This routine handles spinlock contention. It uses a non-standard calling 1104 * convention to avoid converting leaf routines into interior routines. Because 1105 * of this special convention, there are several restrictions: 1106 * 1107 * - do not use gp relative variables, this code is called from the kernel 1108 * and from modules, r1 is undefined. 1109 * - do not use stacked registers, the caller owns them. 1110 * - do not use the scratch stack space, the caller owns it. 1111 * - do not use any registers other than the ones listed below 1112 * 1113 * Inputs: 1114 * ar.pfs - saved CFM of caller 1115 * ar.ccv - 0 (and available for use) 1116 * r27 - flags from spin_lock_irqsave or 0. Must be preserved. 1117 * r28 - available for use. 1118 * r29 - available for use. 1119 * r30 - available for use. 1120 * r31 - address of lock, available for use. 1121 * b6 - return address 1122 * p14 - available for use. 1123 * p15 - used to track flag status. 1124 * 1125 * If you patch this code to use more registers, do not forget to update 1126 * the clobber lists for spin_lock() in include/asm-ia64/spinlock.h. 1127 */ 1128 1129#if (__GNUC__ == 3 && __GNUC_MINOR__ < 3) 1130 1131GLOBAL_ENTRY(ia64_spinlock_contention_pre3_4) 1132 .prologue 1133 .save ar.pfs, r0 // this code effectively has a zero frame size 1134 .save rp, r28 1135 .body 1136 nop 0 1137 tbit.nz p15,p0=r27,IA64_PSR_I_BIT 1138 .restore sp // pop existing prologue after next insn 1139 mov b6 = r28 1140 .prologue 1141 .save ar.pfs, r0 1142 .altrp b6 1143 .body 1144 ;; 1145(p15) ssm psr.i // reenable interrupts if they were on 1146 // DavidM says that srlz.d is slow and is not required in this case 1147.wait: 1148 // exponential backoff, kdb, lockmeter etc. go in here 1149 hint @pause 1150 ld4 r30=[r31] // don't use ld4.bias; if it's contended, we won't write the word 1151 nop 0 1152 ;; 1153 cmp4.ne p14,p0=r30,r0 1154(p14) br.cond.sptk.few .wait 1155(p15) rsm psr.i // disable interrupts if we reenabled them 1156 br.cond.sptk.few b6 // lock is now free, try to acquire 1157 .global ia64_spinlock_contention_pre3_4_end // for kernprof 1158ia64_spinlock_contention_pre3_4_end: 1159END(ia64_spinlock_contention_pre3_4) 1160 1161#else 1162 1163GLOBAL_ENTRY(ia64_spinlock_contention) 1164 .prologue 1165 .altrp b6 1166 .body 1167 tbit.nz p15,p0=r27,IA64_PSR_I_BIT 1168 ;; 1169.wait: 1170(p15) ssm psr.i // reenable interrupts if they were on 1171 // DavidM says that srlz.d is slow and is not required in this case 1172.wait2: 1173 // exponential backoff, kdb, lockmeter etc. go in here 1174 hint @pause 1175 ld4 r30=[r31] // don't use ld4.bias; if it's contended, we won't write the word 1176 ;; 1177 cmp4.ne p14,p0=r30,r0 1178 mov r30 = 1 1179(p14) br.cond.sptk.few .wait2 1180(p15) rsm psr.i // disable interrupts if we reenabled them 1181 ;; 1182 cmpxchg4.acq r30=[r31], r30, ar.ccv 1183 ;; 1184 cmp4.ne p14,p0=r0,r30 1185(p14) br.cond.sptk.few .wait 1186 1187 br.ret.sptk.many b6 // lock is now taken 1188END(ia64_spinlock_contention) 1189 1190#endif 1191 1192#ifdef CONFIG_HOTPLUG_CPU 1193GLOBAL_ENTRY(ia64_jump_to_sal) 1194 alloc r16=ar.pfs,1,0,0,0;; 1195 rsm psr.i | psr.ic 1196{ 1197 flushrs 1198 srlz.i 1199} 1200 tpa r25=in0 1201 movl r18=tlb_purge_done;; 1202 DATA_VA_TO_PA(r18);; 1203 mov b1=r18 // Return location 1204 movl r18=ia64_do_tlb_purge;; 1205 DATA_VA_TO_PA(r18);; 1206 mov b2=r18 // doing tlb_flush work 1207 mov ar.rsc=0 // Put RSE in enforced lazy, LE mode 1208 movl r17=1f;; 1209 DATA_VA_TO_PA(r17);; 1210 mov cr.iip=r17 1211 movl r16=SAL_PSR_BITS_TO_SET;; 1212 mov cr.ipsr=r16 1213 mov cr.ifs=r0;; 1214 rfi;; 12151: 1216 /* 1217 * Invalidate all TLB data/inst 1218 */ 1219 br.sptk.many b2;; // jump to tlb purge code 1220 1221tlb_purge_done: 1222 RESTORE_REGION_REGS(r25, r17,r18,r19);; 1223 RESTORE_REG(b0, r25, r17);; 1224 RESTORE_REG(b1, r25, r17);; 1225 RESTORE_REG(b2, r25, r17);; 1226 RESTORE_REG(b3, r25, r17);; 1227 RESTORE_REG(b4, r25, r17);; 1228 RESTORE_REG(b5, r25, r17);; 1229 ld8 r1=[r25],0x08;; 1230 ld8 r12=[r25],0x08;; 1231 ld8 r13=[r25],0x08;; 1232 RESTORE_REG(ar.fpsr, r25, r17);; 1233 RESTORE_REG(ar.pfs, r25, r17);; 1234 RESTORE_REG(ar.rnat, r25, r17);; 1235 RESTORE_REG(ar.unat, r25, r17);; 1236 RESTORE_REG(ar.bspstore, r25, r17);; 1237 RESTORE_REG(cr.dcr, r25, r17);; 1238 RESTORE_REG(cr.iva, r25, r17);; 1239 RESTORE_REG(cr.pta, r25, r17);; 1240 srlz.d;; // required not to violate RAW dependency 1241 RESTORE_REG(cr.itv, r25, r17);; 1242 RESTORE_REG(cr.pmv, r25, r17);; 1243 RESTORE_REG(cr.cmcv, r25, r17);; 1244 RESTORE_REG(cr.lrr0, r25, r17);; 1245 RESTORE_REG(cr.lrr1, r25, r17);; 1246 ld8 r4=[r25],0x08;; 1247 ld8 r5=[r25],0x08;; 1248 ld8 r6=[r25],0x08;; 1249 ld8 r7=[r25],0x08;; 1250 ld8 r17=[r25],0x08;; 1251 mov pr=r17,-1;; 1252 RESTORE_REG(ar.lc, r25, r17);; 1253 /* 1254 * Now Restore floating point regs 1255 */ 1256 ldf.fill.nta f2=[r25],16;; 1257 ldf.fill.nta f3=[r25],16;; 1258 ldf.fill.nta f4=[r25],16;; 1259 ldf.fill.nta f5=[r25],16;; 1260 ldf.fill.nta f16=[r25],16;; 1261 ldf.fill.nta f17=[r25],16;; 1262 ldf.fill.nta f18=[r25],16;; 1263 ldf.fill.nta f19=[r25],16;; 1264 ldf.fill.nta f20=[r25],16;; 1265 ldf.fill.nta f21=[r25],16;; 1266 ldf.fill.nta f22=[r25],16;; 1267 ldf.fill.nta f23=[r25],16;; 1268 ldf.fill.nta f24=[r25],16;; 1269 ldf.fill.nta f25=[r25],16;; 1270 ldf.fill.nta f26=[r25],16;; 1271 ldf.fill.nta f27=[r25],16;; 1272 ldf.fill.nta f28=[r25],16;; 1273 ldf.fill.nta f29=[r25],16;; 1274 ldf.fill.nta f30=[r25],16;; 1275 ldf.fill.nta f31=[r25],16;; 1276 1277 /* 1278 * Now that we have done all the register restores 1279 * we are now ready for the big DIVE to SAL Land 1280 */ 1281 ssm psr.ic;; 1282 srlz.d;; 1283 br.ret.sptk.many b0;; 1284END(ia64_jump_to_sal) 1285#endif /* CONFIG_HOTPLUG_CPU */ 1286 1287#endif /* CONFIG_SMP */ 1288