1/* 2 * Here is where the ball gets rolling as far as the kernel is concerned. 3 * When control is transferred to _start, the bootload has already 4 * loaded us to the correct address. All that's left to do here is 5 * to set up the kernel's global pointer and jump to the kernel 6 * entry point. 7 * 8 * Copyright (C) 1998-2001, 2003, 2005 Hewlett-Packard Co 9 * David Mosberger-Tang <davidm@hpl.hp.com> 10 * Stephane Eranian <eranian@hpl.hp.com> 11 * Copyright (C) 1999 VA Linux Systems 12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com> 13 * Copyright (C) 1999 Intel Corp. 14 * Copyright (C) 1999 Asit Mallick <Asit.K.Mallick@intel.com> 15 * Copyright (C) 1999 Don Dugger <Don.Dugger@intel.com> 16 * Copyright (C) 2002 Fenghua Yu <fenghua.yu@intel.com> 17 * -Optimize __ia64_save_fpu() and __ia64_load_fpu() for Itanium 2. 18 * Copyright (C) 2004 Ashok Raj <ashok.raj@intel.com> 19 * Support for CPU Hotplug 20 */ 21 22 23#include <asm/asmmacro.h> 24#include <asm/fpu.h> 25#include <asm/kregs.h> 26#include <asm/mmu_context.h> 27#include <asm/asm-offsets.h> 28#include <asm/pal.h> 29#include <asm/pgtable.h> 30#include <asm/processor.h> 31#include <asm/ptrace.h> 32#include <asm/system.h> 33#include <asm/mca_asm.h> 34 35#ifdef CONFIG_HOTPLUG_CPU 36#define SAL_PSR_BITS_TO_SET \ 37 (IA64_PSR_AC | IA64_PSR_BN | IA64_PSR_MFH | IA64_PSR_MFL) 38 39#define SAVE_FROM_REG(src, ptr, dest) \ 40 mov dest=src;; \ 41 st8 [ptr]=dest,0x08 42 43#define RESTORE_REG(reg, ptr, _tmp) \ 44 ld8 _tmp=[ptr],0x08;; \ 45 mov reg=_tmp 46 47#define SAVE_BREAK_REGS(ptr, _idx, _breg, _dest)\ 48 mov ar.lc=IA64_NUM_DBG_REGS-1;; \ 49 mov _idx=0;; \ 501: \ 51 SAVE_FROM_REG(_breg[_idx], ptr, _dest);; \ 52 add _idx=1,_idx;; \ 53 br.cloop.sptk.many 1b 54 55#define RESTORE_BREAK_REGS(ptr, _idx, _breg, _tmp, _lbl)\ 56 mov ar.lc=IA64_NUM_DBG_REGS-1;; \ 57 mov _idx=0;; \ 58_lbl: RESTORE_REG(_breg[_idx], ptr, _tmp);; \ 59 add _idx=1, _idx;; \ 60 br.cloop.sptk.many _lbl 61 62#define SAVE_ONE_RR(num, _reg, _tmp) \ 63 movl _tmp=(num<<61);; \ 64 mov _reg=rr[_tmp] 65 66#define SAVE_REGION_REGS(_tmp, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7) \ 67 SAVE_ONE_RR(0,_r0, _tmp);; \ 68 SAVE_ONE_RR(1,_r1, _tmp);; \ 69 SAVE_ONE_RR(2,_r2, _tmp);; \ 70 SAVE_ONE_RR(3,_r3, _tmp);; \ 71 SAVE_ONE_RR(4,_r4, _tmp);; \ 72 SAVE_ONE_RR(5,_r5, _tmp);; \ 73 SAVE_ONE_RR(6,_r6, _tmp);; \ 74 SAVE_ONE_RR(7,_r7, _tmp);; 75 76#define STORE_REGION_REGS(ptr, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7) \ 77 st8 [ptr]=_r0, 8;; \ 78 st8 [ptr]=_r1, 8;; \ 79 st8 [ptr]=_r2, 8;; \ 80 st8 [ptr]=_r3, 8;; \ 81 st8 [ptr]=_r4, 8;; \ 82 st8 [ptr]=_r5, 8;; \ 83 st8 [ptr]=_r6, 8;; \ 84 st8 [ptr]=_r7, 8;; 85 86#define RESTORE_REGION_REGS(ptr, _idx1, _idx2, _tmp) \ 87 mov ar.lc=0x08-1;; \ 88 movl _idx1=0x00;; \ 89RestRR: \ 90 dep.z _idx2=_idx1,61,3;; \ 91 ld8 _tmp=[ptr],8;; \ 92 mov rr[_idx2]=_tmp;; \ 93 srlz.d;; \ 94 add _idx1=1,_idx1;; \ 95 br.cloop.sptk.few RestRR 96 97#define SET_AREA_FOR_BOOTING_CPU(reg1, reg2) \ 98 movl reg1=sal_state_for_booting_cpu;; \ 99 ld8 reg2=[reg1];; 100 101/* 102 * Adjust region registers saved before starting to save 103 * break regs and rest of the states that need to be preserved. 104 */ 105#define SAL_TO_OS_BOOT_HANDOFF_STATE_SAVE(_reg1,_reg2,_pred) \ 106 SAVE_FROM_REG(b0,_reg1,_reg2);; \ 107 SAVE_FROM_REG(b1,_reg1,_reg2);; \ 108 SAVE_FROM_REG(b2,_reg1,_reg2);; \ 109 SAVE_FROM_REG(b3,_reg1,_reg2);; \ 110 SAVE_FROM_REG(b4,_reg1,_reg2);; \ 111 SAVE_FROM_REG(b5,_reg1,_reg2);; \ 112 st8 [_reg1]=r1,0x08;; \ 113 st8 [_reg1]=r12,0x08;; \ 114 st8 [_reg1]=r13,0x08;; \ 115 SAVE_FROM_REG(ar.fpsr,_reg1,_reg2);; \ 116 SAVE_FROM_REG(ar.pfs,_reg1,_reg2);; \ 117 SAVE_FROM_REG(ar.rnat,_reg1,_reg2);; \ 118 SAVE_FROM_REG(ar.unat,_reg1,_reg2);; \ 119 SAVE_FROM_REG(ar.bspstore,_reg1,_reg2);; \ 120 SAVE_FROM_REG(cr.dcr,_reg1,_reg2);; \ 121 SAVE_FROM_REG(cr.iva,_reg1,_reg2);; \ 122 SAVE_FROM_REG(cr.pta,_reg1,_reg2);; \ 123 SAVE_FROM_REG(cr.itv,_reg1,_reg2);; \ 124 SAVE_FROM_REG(cr.pmv,_reg1,_reg2);; \ 125 SAVE_FROM_REG(cr.cmcv,_reg1,_reg2);; \ 126 SAVE_FROM_REG(cr.lrr0,_reg1,_reg2);; \ 127 SAVE_FROM_REG(cr.lrr1,_reg1,_reg2);; \ 128 st8 [_reg1]=r4,0x08;; \ 129 st8 [_reg1]=r5,0x08;; \ 130 st8 [_reg1]=r6,0x08;; \ 131 st8 [_reg1]=r7,0x08;; \ 132 st8 [_reg1]=_pred,0x08;; \ 133 SAVE_FROM_REG(ar.lc, _reg1, _reg2);; \ 134 stf.spill.nta [_reg1]=f2,16;; \ 135 stf.spill.nta [_reg1]=f3,16;; \ 136 stf.spill.nta [_reg1]=f4,16;; \ 137 stf.spill.nta [_reg1]=f5,16;; \ 138 stf.spill.nta [_reg1]=f16,16;; \ 139 stf.spill.nta [_reg1]=f17,16;; \ 140 stf.spill.nta [_reg1]=f18,16;; \ 141 stf.spill.nta [_reg1]=f19,16;; \ 142 stf.spill.nta [_reg1]=f20,16;; \ 143 stf.spill.nta [_reg1]=f21,16;; \ 144 stf.spill.nta [_reg1]=f22,16;; \ 145 stf.spill.nta [_reg1]=f23,16;; \ 146 stf.spill.nta [_reg1]=f24,16;; \ 147 stf.spill.nta [_reg1]=f25,16;; \ 148 stf.spill.nta [_reg1]=f26,16;; \ 149 stf.spill.nta [_reg1]=f27,16;; \ 150 stf.spill.nta [_reg1]=f28,16;; \ 151 stf.spill.nta [_reg1]=f29,16;; \ 152 stf.spill.nta [_reg1]=f30,16;; \ 153 stf.spill.nta [_reg1]=f31,16;; 154 155#else 156#define SET_AREA_FOR_BOOTING_CPU(a1, a2) 157#define SAL_TO_OS_BOOT_HANDOFF_STATE_SAVE(a1,a2, a3) 158#define SAVE_REGION_REGS(_tmp, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7) 159#define STORE_REGION_REGS(ptr, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7) 160#endif 161 162#define SET_ONE_RR(num, pgsize, _tmp1, _tmp2, vhpt) \ 163 movl _tmp1=(num << 61);; \ 164 mov _tmp2=((ia64_rid(IA64_REGION_ID_KERNEL, (num<<61)) << 8) | (pgsize << 2) | vhpt);; \ 165 mov rr[_tmp1]=_tmp2 166 167 .section __special_page_section,"ax" 168 169 .global empty_zero_page 170empty_zero_page: 171 .skip PAGE_SIZE 172 173 .global swapper_pg_dir 174swapper_pg_dir: 175 .skip PAGE_SIZE 176 177 .rodata 178halt_msg: 179 stringz "Halting kernel\n" 180 181 .section .text.head,"ax" 182 183 .global start_ap 184 185 /* 186 * Start the kernel. When the bootloader passes control to _start(), r28 187 * points to the address of the boot parameter area. Execution reaches 188 * here in physical mode. 189 */ 190GLOBAL_ENTRY(_start) 191start_ap: 192 .prologue 193 .save rp, r0 // terminate unwind chain with a NULL rp 194 .body 195 196 rsm psr.i | psr.ic 197 ;; 198 srlz.i 199 ;; 200 { 201 flushrs // must be first insn in group 202 srlz.i 203 } 204 ;; 205 /* 206 * Save the region registers, predicate before they get clobbered 207 */ 208 SAVE_REGION_REGS(r2, r8,r9,r10,r11,r12,r13,r14,r15); 209 mov r25=pr;; 210 211 /* 212 * Initialize kernel region registers: 213 * rr[0]: VHPT enabled, page size = PAGE_SHIFT 214 * rr[1]: VHPT enabled, page size = PAGE_SHIFT 215 * rr[2]: VHPT enabled, page size = PAGE_SHIFT 216 * rr[3]: VHPT enabled, page size = PAGE_SHIFT 217 * rr[4]: VHPT enabled, page size = PAGE_SHIFT 218 * rr[5]: VHPT enabled, page size = PAGE_SHIFT 219 * rr[6]: VHPT disabled, page size = IA64_GRANULE_SHIFT 220 * rr[7]: VHPT disabled, page size = IA64_GRANULE_SHIFT 221 * We initialize all of them to prevent inadvertently assuming 222 * something about the state of address translation early in boot. 223 */ 224 SET_ONE_RR(0, PAGE_SHIFT, r2, r16, 1);; 225 SET_ONE_RR(1, PAGE_SHIFT, r2, r16, 1);; 226 SET_ONE_RR(2, PAGE_SHIFT, r2, r16, 1);; 227 SET_ONE_RR(3, PAGE_SHIFT, r2, r16, 1);; 228 SET_ONE_RR(4, PAGE_SHIFT, r2, r16, 1);; 229 SET_ONE_RR(5, PAGE_SHIFT, r2, r16, 1);; 230 SET_ONE_RR(6, IA64_GRANULE_SHIFT, r2, r16, 0);; 231 SET_ONE_RR(7, IA64_GRANULE_SHIFT, r2, r16, 0);; 232 /* 233 * Now pin mappings into the TLB for kernel text and data 234 */ 235 mov r18=KERNEL_TR_PAGE_SHIFT<<2 236 movl r17=KERNEL_START 237 ;; 238 mov cr.itir=r18 239 mov cr.ifa=r17 240 mov r16=IA64_TR_KERNEL 241 mov r3=ip 242 movl r18=PAGE_KERNEL 243 ;; 244 dep r2=0,r3,0,KERNEL_TR_PAGE_SHIFT 245 ;; 246 or r18=r2,r18 247 ;; 248 srlz.i 249 ;; 250 itr.i itr[r16]=r18 251 ;; 252 itr.d dtr[r16]=r18 253 ;; 254 srlz.i 255 256 /* 257 * Switch into virtual mode: 258 */ 259 movl r16=(IA64_PSR_IT|IA64_PSR_IC|IA64_PSR_DT|IA64_PSR_RT|IA64_PSR_DFH|IA64_PSR_BN \ 260 |IA64_PSR_DI) 261 ;; 262 mov cr.ipsr=r16 263 movl r17=1f 264 ;; 265 mov cr.iip=r17 266 mov cr.ifs=r0 267 ;; 268 rfi 269 ;; 2701: // now we are in virtual mode 271 272 SET_AREA_FOR_BOOTING_CPU(r2, r16); 273 274 STORE_REGION_REGS(r16, r8,r9,r10,r11,r12,r13,r14,r15); 275 SAL_TO_OS_BOOT_HANDOFF_STATE_SAVE(r16,r17,r25) 276 ;; 277 278 // set IVT entry point---can't access I/O ports without it 279 movl r3=ia64_ivt 280 ;; 281 mov cr.iva=r3 282 movl r2=FPSR_DEFAULT 283 ;; 284 srlz.i 285 movl gp=__gp 286 287 mov ar.fpsr=r2 288 ;; 289 290#define isAP p2 // are we an Application Processor? 291#define isBP p3 // are we the Bootstrap Processor? 292 293#ifdef CONFIG_SMP 294 /* 295 * Find the init_task for the currently booting CPU. At poweron, and in 296 * UP mode, task_for_booting_cpu is NULL. 297 */ 298 movl r3=task_for_booting_cpu 299 ;; 300 ld8 r3=[r3] 301 movl r2=init_task 302 ;; 303 cmp.eq isBP,isAP=r3,r0 304 ;; 305(isAP) mov r2=r3 306#else 307 movl r2=init_task 308 cmp.eq isBP,isAP=r0,r0 309#endif 310 ;; 311 tpa r3=r2 // r3 == phys addr of task struct 312 mov r16=-1 313(isBP) br.cond.dpnt .load_current // BP stack is on region 5 --- no need to map it 314 315 // load mapping for stack (virtaddr in r2, physaddr in r3) 316 rsm psr.ic 317 movl r17=PAGE_KERNEL 318 ;; 319 srlz.d 320 dep r18=0,r3,0,12 321 ;; 322 or r18=r17,r18 323 dep r2=-1,r3,61,3 // IMVA of task 324 ;; 325 mov r17=rr[r2] 326 shr.u r16=r3,IA64_GRANULE_SHIFT 327 ;; 328 dep r17=0,r17,8,24 329 ;; 330 mov cr.itir=r17 331 mov cr.ifa=r2 332 333 mov r19=IA64_TR_CURRENT_STACK 334 ;; 335 itr.d dtr[r19]=r18 336 ;; 337 ssm psr.ic 338 srlz.d 339 ;; 340 341.load_current: 342 // load the "current" pointer (r13) and ar.k6 with the current task 343 mov IA64_KR(CURRENT)=r2 // virtual address 344 mov IA64_KR(CURRENT_STACK)=r16 345 mov r13=r2 346 /* 347 * Reserve space at the top of the stack for "struct pt_regs". Kernel 348 * threads don't store interesting values in that structure, but the space 349 * still needs to be there because time-critical stuff such as the context 350 * switching can be implemented more efficiently (for example, __switch_to() 351 * always sets the psr.dfh bit of the task it is switching to). 352 */ 353 354 addl r12=IA64_STK_OFFSET-IA64_PT_REGS_SIZE-16,r2 355 addl r2=IA64_RBS_OFFSET,r2 // initialize the RSE 356 mov ar.rsc=0 // place RSE in enforced lazy mode 357 ;; 358 loadrs // clear the dirty partition 359 mov IA64_KR(PER_CPU_DATA)=r0 // clear physical per-CPU base 360 ;; 361 mov ar.bspstore=r2 // establish the new RSE stack 362 ;; 363 mov ar.rsc=0x3 // place RSE in eager mode 364 365(isBP) dep r28=-1,r28,61,3 // make address virtual 366(isBP) movl r2=ia64_boot_param 367 ;; 368(isBP) st8 [r2]=r28 // save the address of the boot param area passed by the bootloader 369 370#ifdef CONFIG_SMP 371(isAP) br.call.sptk.many rp=start_secondary 372.ret0: 373(isAP) br.cond.sptk self 374#endif 375 376 // This is executed by the bootstrap processor (bsp) only: 377 378#ifdef CONFIG_IA64_FW_EMU 379 // initialize PAL & SAL emulator: 380 br.call.sptk.many rp=sys_fw_init 381.ret1: 382#endif 383 br.call.sptk.many rp=start_kernel 384.ret2: addl r3=@ltoff(halt_msg),gp 385 ;; 386 alloc r2=ar.pfs,8,0,2,0 387 ;; 388 ld8 out0=[r3] 389 br.call.sptk.many b0=console_print 390 391self: hint @pause 392 br.sptk.many self // endless loop 393END(_start) 394 395 .text 396 397GLOBAL_ENTRY(ia64_save_debug_regs) 398 alloc r16=ar.pfs,1,0,0,0 399 mov r20=ar.lc // preserve ar.lc 400 mov ar.lc=IA64_NUM_DBG_REGS-1 401 mov r18=0 402 add r19=IA64_NUM_DBG_REGS*8,in0 403 ;; 4041: mov r16=dbr[r18] 405#ifdef CONFIG_ITANIUM 406 ;; 407 srlz.d 408#endif 409 mov r17=ibr[r18] 410 add r18=1,r18 411 ;; 412 st8.nta [in0]=r16,8 413 st8.nta [r19]=r17,8 414 br.cloop.sptk.many 1b 415 ;; 416 mov ar.lc=r20 // restore ar.lc 417 br.ret.sptk.many rp 418END(ia64_save_debug_regs) 419 420GLOBAL_ENTRY(ia64_load_debug_regs) 421 alloc r16=ar.pfs,1,0,0,0 422 lfetch.nta [in0] 423 mov r20=ar.lc // preserve ar.lc 424 add r19=IA64_NUM_DBG_REGS*8,in0 425 mov ar.lc=IA64_NUM_DBG_REGS-1 426 mov r18=-1 427 ;; 4281: ld8.nta r16=[in0],8 429 ld8.nta r17=[r19],8 430 add r18=1,r18 431 ;; 432 mov dbr[r18]=r16 433#ifdef CONFIG_ITANIUM 434 ;; 435 srlz.d // Errata 132 (NoFix status) 436#endif 437 mov ibr[r18]=r17 438 br.cloop.sptk.many 1b 439 ;; 440 mov ar.lc=r20 // restore ar.lc 441 br.ret.sptk.many rp 442END(ia64_load_debug_regs) 443 444GLOBAL_ENTRY(__ia64_save_fpu) 445 alloc r2=ar.pfs,1,4,0,0 446 adds loc0=96*16-16,in0 447 adds loc1=96*16-16-128,in0 448 ;; 449 stf.spill.nta [loc0]=f127,-256 450 stf.spill.nta [loc1]=f119,-256 451 ;; 452 stf.spill.nta [loc0]=f111,-256 453 stf.spill.nta [loc1]=f103,-256 454 ;; 455 stf.spill.nta [loc0]=f95,-256 456 stf.spill.nta [loc1]=f87,-256 457 ;; 458 stf.spill.nta [loc0]=f79,-256 459 stf.spill.nta [loc1]=f71,-256 460 ;; 461 stf.spill.nta [loc0]=f63,-256 462 stf.spill.nta [loc1]=f55,-256 463 adds loc2=96*16-32,in0 464 ;; 465 stf.spill.nta [loc0]=f47,-256 466 stf.spill.nta [loc1]=f39,-256 467 adds loc3=96*16-32-128,in0 468 ;; 469 stf.spill.nta [loc2]=f126,-256 470 stf.spill.nta [loc3]=f118,-256 471 ;; 472 stf.spill.nta [loc2]=f110,-256 473 stf.spill.nta [loc3]=f102,-256 474 ;; 475 stf.spill.nta [loc2]=f94,-256 476 stf.spill.nta [loc3]=f86,-256 477 ;; 478 stf.spill.nta [loc2]=f78,-256 479 stf.spill.nta [loc3]=f70,-256 480 ;; 481 stf.spill.nta [loc2]=f62,-256 482 stf.spill.nta [loc3]=f54,-256 483 adds loc0=96*16-48,in0 484 ;; 485 stf.spill.nta [loc2]=f46,-256 486 stf.spill.nta [loc3]=f38,-256 487 adds loc1=96*16-48-128,in0 488 ;; 489 stf.spill.nta [loc0]=f125,-256 490 stf.spill.nta [loc1]=f117,-256 491 ;; 492 stf.spill.nta [loc0]=f109,-256 493 stf.spill.nta [loc1]=f101,-256 494 ;; 495 stf.spill.nta [loc0]=f93,-256 496 stf.spill.nta [loc1]=f85,-256 497 ;; 498 stf.spill.nta [loc0]=f77,-256 499 stf.spill.nta [loc1]=f69,-256 500 ;; 501 stf.spill.nta [loc0]=f61,-256 502 stf.spill.nta [loc1]=f53,-256 503 adds loc2=96*16-64,in0 504 ;; 505 stf.spill.nta [loc0]=f45,-256 506 stf.spill.nta [loc1]=f37,-256 507 adds loc3=96*16-64-128,in0 508 ;; 509 stf.spill.nta [loc2]=f124,-256 510 stf.spill.nta [loc3]=f116,-256 511 ;; 512 stf.spill.nta [loc2]=f108,-256 513 stf.spill.nta [loc3]=f100,-256 514 ;; 515 stf.spill.nta [loc2]=f92,-256 516 stf.spill.nta [loc3]=f84,-256 517 ;; 518 stf.spill.nta [loc2]=f76,-256 519 stf.spill.nta [loc3]=f68,-256 520 ;; 521 stf.spill.nta [loc2]=f60,-256 522 stf.spill.nta [loc3]=f52,-256 523 adds loc0=96*16-80,in0 524 ;; 525 stf.spill.nta [loc2]=f44,-256 526 stf.spill.nta [loc3]=f36,-256 527 adds loc1=96*16-80-128,in0 528 ;; 529 stf.spill.nta [loc0]=f123,-256 530 stf.spill.nta [loc1]=f115,-256 531 ;; 532 stf.spill.nta [loc0]=f107,-256 533 stf.spill.nta [loc1]=f99,-256 534 ;; 535 stf.spill.nta [loc0]=f91,-256 536 stf.spill.nta [loc1]=f83,-256 537 ;; 538 stf.spill.nta [loc0]=f75,-256 539 stf.spill.nta [loc1]=f67,-256 540 ;; 541 stf.spill.nta [loc0]=f59,-256 542 stf.spill.nta [loc1]=f51,-256 543 adds loc2=96*16-96,in0 544 ;; 545 stf.spill.nta [loc0]=f43,-256 546 stf.spill.nta [loc1]=f35,-256 547 adds loc3=96*16-96-128,in0 548 ;; 549 stf.spill.nta [loc2]=f122,-256 550 stf.spill.nta [loc3]=f114,-256 551 ;; 552 stf.spill.nta [loc2]=f106,-256 553 stf.spill.nta [loc3]=f98,-256 554 ;; 555 stf.spill.nta [loc2]=f90,-256 556 stf.spill.nta [loc3]=f82,-256 557 ;; 558 stf.spill.nta [loc2]=f74,-256 559 stf.spill.nta [loc3]=f66,-256 560 ;; 561 stf.spill.nta [loc2]=f58,-256 562 stf.spill.nta [loc3]=f50,-256 563 adds loc0=96*16-112,in0 564 ;; 565 stf.spill.nta [loc2]=f42,-256 566 stf.spill.nta [loc3]=f34,-256 567 adds loc1=96*16-112-128,in0 568 ;; 569 stf.spill.nta [loc0]=f121,-256 570 stf.spill.nta [loc1]=f113,-256 571 ;; 572 stf.spill.nta [loc0]=f105,-256 573 stf.spill.nta [loc1]=f97,-256 574 ;; 575 stf.spill.nta [loc0]=f89,-256 576 stf.spill.nta [loc1]=f81,-256 577 ;; 578 stf.spill.nta [loc0]=f73,-256 579 stf.spill.nta [loc1]=f65,-256 580 ;; 581 stf.spill.nta [loc0]=f57,-256 582 stf.spill.nta [loc1]=f49,-256 583 adds loc2=96*16-128,in0 584 ;; 585 stf.spill.nta [loc0]=f41,-256 586 stf.spill.nta [loc1]=f33,-256 587 adds loc3=96*16-128-128,in0 588 ;; 589 stf.spill.nta [loc2]=f120,-256 590 stf.spill.nta [loc3]=f112,-256 591 ;; 592 stf.spill.nta [loc2]=f104,-256 593 stf.spill.nta [loc3]=f96,-256 594 ;; 595 stf.spill.nta [loc2]=f88,-256 596 stf.spill.nta [loc3]=f80,-256 597 ;; 598 stf.spill.nta [loc2]=f72,-256 599 stf.spill.nta [loc3]=f64,-256 600 ;; 601 stf.spill.nta [loc2]=f56,-256 602 stf.spill.nta [loc3]=f48,-256 603 ;; 604 stf.spill.nta [loc2]=f40 605 stf.spill.nta [loc3]=f32 606 br.ret.sptk.many rp 607END(__ia64_save_fpu) 608 609GLOBAL_ENTRY(__ia64_load_fpu) 610 alloc r2=ar.pfs,1,2,0,0 611 adds r3=128,in0 612 adds r14=256,in0 613 adds r15=384,in0 614 mov loc0=512 615 mov loc1=-1024+16 616 ;; 617 ldf.fill.nta f32=[in0],loc0 618 ldf.fill.nta f40=[ r3],loc0 619 ldf.fill.nta f48=[r14],loc0 620 ldf.fill.nta f56=[r15],loc0 621 ;; 622 ldf.fill.nta f64=[in0],loc0 623 ldf.fill.nta f72=[ r3],loc0 624 ldf.fill.nta f80=[r14],loc0 625 ldf.fill.nta f88=[r15],loc0 626 ;; 627 ldf.fill.nta f96=[in0],loc1 628 ldf.fill.nta f104=[ r3],loc1 629 ldf.fill.nta f112=[r14],loc1 630 ldf.fill.nta f120=[r15],loc1 631 ;; 632 ldf.fill.nta f33=[in0],loc0 633 ldf.fill.nta f41=[ r3],loc0 634 ldf.fill.nta f49=[r14],loc0 635 ldf.fill.nta f57=[r15],loc0 636 ;; 637 ldf.fill.nta f65=[in0],loc0 638 ldf.fill.nta f73=[ r3],loc0 639 ldf.fill.nta f81=[r14],loc0 640 ldf.fill.nta f89=[r15],loc0 641 ;; 642 ldf.fill.nta f97=[in0],loc1 643 ldf.fill.nta f105=[ r3],loc1 644 ldf.fill.nta f113=[r14],loc1 645 ldf.fill.nta f121=[r15],loc1 646 ;; 647 ldf.fill.nta f34=[in0],loc0 648 ldf.fill.nta f42=[ r3],loc0 649 ldf.fill.nta f50=[r14],loc0 650 ldf.fill.nta f58=[r15],loc0 651 ;; 652 ldf.fill.nta f66=[in0],loc0 653 ldf.fill.nta f74=[ r3],loc0 654 ldf.fill.nta f82=[r14],loc0 655 ldf.fill.nta f90=[r15],loc0 656 ;; 657 ldf.fill.nta f98=[in0],loc1 658 ldf.fill.nta f106=[ r3],loc1 659 ldf.fill.nta f114=[r14],loc1 660 ldf.fill.nta f122=[r15],loc1 661 ;; 662 ldf.fill.nta f35=[in0],loc0 663 ldf.fill.nta f43=[ r3],loc0 664 ldf.fill.nta f51=[r14],loc0 665 ldf.fill.nta f59=[r15],loc0 666 ;; 667 ldf.fill.nta f67=[in0],loc0 668 ldf.fill.nta f75=[ r3],loc0 669 ldf.fill.nta f83=[r14],loc0 670 ldf.fill.nta f91=[r15],loc0 671 ;; 672 ldf.fill.nta f99=[in0],loc1 673 ldf.fill.nta f107=[ r3],loc1 674 ldf.fill.nta f115=[r14],loc1 675 ldf.fill.nta f123=[r15],loc1 676 ;; 677 ldf.fill.nta f36=[in0],loc0 678 ldf.fill.nta f44=[ r3],loc0 679 ldf.fill.nta f52=[r14],loc0 680 ldf.fill.nta f60=[r15],loc0 681 ;; 682 ldf.fill.nta f68=[in0],loc0 683 ldf.fill.nta f76=[ r3],loc0 684 ldf.fill.nta f84=[r14],loc0 685 ldf.fill.nta f92=[r15],loc0 686 ;; 687 ldf.fill.nta f100=[in0],loc1 688 ldf.fill.nta f108=[ r3],loc1 689 ldf.fill.nta f116=[r14],loc1 690 ldf.fill.nta f124=[r15],loc1 691 ;; 692 ldf.fill.nta f37=[in0],loc0 693 ldf.fill.nta f45=[ r3],loc0 694 ldf.fill.nta f53=[r14],loc0 695 ldf.fill.nta f61=[r15],loc0 696 ;; 697 ldf.fill.nta f69=[in0],loc0 698 ldf.fill.nta f77=[ r3],loc0 699 ldf.fill.nta f85=[r14],loc0 700 ldf.fill.nta f93=[r15],loc0 701 ;; 702 ldf.fill.nta f101=[in0],loc1 703 ldf.fill.nta f109=[ r3],loc1 704 ldf.fill.nta f117=[r14],loc1 705 ldf.fill.nta f125=[r15],loc1 706 ;; 707 ldf.fill.nta f38 =[in0],loc0 708 ldf.fill.nta f46 =[ r3],loc0 709 ldf.fill.nta f54 =[r14],loc0 710 ldf.fill.nta f62 =[r15],loc0 711 ;; 712 ldf.fill.nta f70 =[in0],loc0 713 ldf.fill.nta f78 =[ r3],loc0 714 ldf.fill.nta f86 =[r14],loc0 715 ldf.fill.nta f94 =[r15],loc0 716 ;; 717 ldf.fill.nta f102=[in0],loc1 718 ldf.fill.nta f110=[ r3],loc1 719 ldf.fill.nta f118=[r14],loc1 720 ldf.fill.nta f126=[r15],loc1 721 ;; 722 ldf.fill.nta f39 =[in0],loc0 723 ldf.fill.nta f47 =[ r3],loc0 724 ldf.fill.nta f55 =[r14],loc0 725 ldf.fill.nta f63 =[r15],loc0 726 ;; 727 ldf.fill.nta f71 =[in0],loc0 728 ldf.fill.nta f79 =[ r3],loc0 729 ldf.fill.nta f87 =[r14],loc0 730 ldf.fill.nta f95 =[r15],loc0 731 ;; 732 ldf.fill.nta f103=[in0] 733 ldf.fill.nta f111=[ r3] 734 ldf.fill.nta f119=[r14] 735 ldf.fill.nta f127=[r15] 736 br.ret.sptk.many rp 737END(__ia64_load_fpu) 738 739GLOBAL_ENTRY(__ia64_init_fpu) 740 stf.spill [sp]=f0 // M3 741 mov f32=f0 // F 742 nop.b 0 743 744 ldfps f33,f34=[sp] // M0 745 ldfps f35,f36=[sp] // M1 746 mov f37=f0 // F 747 ;; 748 749 setf.s f38=r0 // M2 750 setf.s f39=r0 // M3 751 mov f40=f0 // F 752 753 ldfps f41,f42=[sp] // M0 754 ldfps f43,f44=[sp] // M1 755 mov f45=f0 // F 756 757 setf.s f46=r0 // M2 758 setf.s f47=r0 // M3 759 mov f48=f0 // F 760 761 ldfps f49,f50=[sp] // M0 762 ldfps f51,f52=[sp] // M1 763 mov f53=f0 // F 764 765 setf.s f54=r0 // M2 766 setf.s f55=r0 // M3 767 mov f56=f0 // F 768 769 ldfps f57,f58=[sp] // M0 770 ldfps f59,f60=[sp] // M1 771 mov f61=f0 // F 772 773 setf.s f62=r0 // M2 774 setf.s f63=r0 // M3 775 mov f64=f0 // F 776 777 ldfps f65,f66=[sp] // M0 778 ldfps f67,f68=[sp] // M1 779 mov f69=f0 // F 780 781 setf.s f70=r0 // M2 782 setf.s f71=r0 // M3 783 mov f72=f0 // F 784 785 ldfps f73,f74=[sp] // M0 786 ldfps f75,f76=[sp] // M1 787 mov f77=f0 // F 788 789 setf.s f78=r0 // M2 790 setf.s f79=r0 // M3 791 mov f80=f0 // F 792 793 ldfps f81,f82=[sp] // M0 794 ldfps f83,f84=[sp] // M1 795 mov f85=f0 // F 796 797 setf.s f86=r0 // M2 798 setf.s f87=r0 // M3 799 mov f88=f0 // F 800 801 /* 802 * When the instructions are cached, it would be faster to initialize 803 * the remaining registers with simply mov instructions (F-unit). 804 * This gets the time down to ~29 cycles. However, this would use up 805 * 33 bundles, whereas continuing with the above pattern yields 806 * 10 bundles and ~30 cycles. 807 */ 808 809 ldfps f89,f90=[sp] // M0 810 ldfps f91,f92=[sp] // M1 811 mov f93=f0 // F 812 813 setf.s f94=r0 // M2 814 setf.s f95=r0 // M3 815 mov f96=f0 // F 816 817 ldfps f97,f98=[sp] // M0 818 ldfps f99,f100=[sp] // M1 819 mov f101=f0 // F 820 821 setf.s f102=r0 // M2 822 setf.s f103=r0 // M3 823 mov f104=f0 // F 824 825 ldfps f105,f106=[sp] // M0 826 ldfps f107,f108=[sp] // M1 827 mov f109=f0 // F 828 829 setf.s f110=r0 // M2 830 setf.s f111=r0 // M3 831 mov f112=f0 // F 832 833 ldfps f113,f114=[sp] // M0 834 ldfps f115,f116=[sp] // M1 835 mov f117=f0 // F 836 837 setf.s f118=r0 // M2 838 setf.s f119=r0 // M3 839 mov f120=f0 // F 840 841 ldfps f121,f122=[sp] // M0 842 ldfps f123,f124=[sp] // M1 843 mov f125=f0 // F 844 845 setf.s f126=r0 // M2 846 setf.s f127=r0 // M3 847 br.ret.sptk.many rp // F 848END(__ia64_init_fpu) 849 850/* 851 * Switch execution mode from virtual to physical 852 * 853 * Inputs: 854 * r16 = new psr to establish 855 * Output: 856 * r19 = old virtual address of ar.bsp 857 * r20 = old virtual address of sp 858 * 859 * Note: RSE must already be in enforced lazy mode 860 */ 861GLOBAL_ENTRY(ia64_switch_mode_phys) 862 { 863 rsm psr.i | psr.ic // disable interrupts and interrupt collection 864 mov r15=ip 865 } 866 ;; 867 { 868 flushrs // must be first insn in group 869 srlz.i 870 } 871 ;; 872 mov cr.ipsr=r16 // set new PSR 873 add r3=1f-ia64_switch_mode_phys,r15 874 875 mov r19=ar.bsp 876 mov r20=sp 877 mov r14=rp // get return address into a general register 878 ;; 879 880 // going to physical mode, use tpa to translate virt->phys 881 tpa r17=r19 882 tpa r3=r3 883 tpa sp=sp 884 tpa r14=r14 885 ;; 886 887 mov r18=ar.rnat // save ar.rnat 888 mov ar.bspstore=r17 // this steps on ar.rnat 889 mov cr.iip=r3 890 mov cr.ifs=r0 891 ;; 892 mov ar.rnat=r18 // restore ar.rnat 893 rfi // must be last insn in group 894 ;; 8951: mov rp=r14 896 br.ret.sptk.many rp 897END(ia64_switch_mode_phys) 898 899/* 900 * Switch execution mode from physical to virtual 901 * 902 * Inputs: 903 * r16 = new psr to establish 904 * r19 = new bspstore to establish 905 * r20 = new sp to establish 906 * 907 * Note: RSE must already be in enforced lazy mode 908 */ 909GLOBAL_ENTRY(ia64_switch_mode_virt) 910 { 911 rsm psr.i | psr.ic // disable interrupts and interrupt collection 912 mov r15=ip 913 } 914 ;; 915 { 916 flushrs // must be first insn in group 917 srlz.i 918 } 919 ;; 920 mov cr.ipsr=r16 // set new PSR 921 add r3=1f-ia64_switch_mode_virt,r15 922 923 mov r14=rp // get return address into a general register 924 ;; 925 926 // going to virtual 927 // - for code addresses, set upper bits of addr to KERNEL_START 928 // - for stack addresses, copy from input argument 929 movl r18=KERNEL_START 930 dep r3=0,r3,KERNEL_TR_PAGE_SHIFT,64-KERNEL_TR_PAGE_SHIFT 931 dep r14=0,r14,KERNEL_TR_PAGE_SHIFT,64-KERNEL_TR_PAGE_SHIFT 932 mov sp=r20 933 ;; 934 or r3=r3,r18 935 or r14=r14,r18 936 ;; 937 938 mov r18=ar.rnat // save ar.rnat 939 mov ar.bspstore=r19 // this steps on ar.rnat 940 mov cr.iip=r3 941 mov cr.ifs=r0 942 ;; 943 mov ar.rnat=r18 // restore ar.rnat 944 rfi // must be last insn in group 945 ;; 9461: mov rp=r14 947 br.ret.sptk.many rp 948END(ia64_switch_mode_virt) 949 950GLOBAL_ENTRY(ia64_delay_loop) 951 .prologue 952{ nop 0 // work around GAS unwind info generation bug... 953 .save ar.lc,r2 954 mov r2=ar.lc 955 .body 956 ;; 957 mov ar.lc=r32 958} 959 ;; 960 // force loop to be 32-byte aligned (GAS bug means we cannot use .align 961 // inside function body without corrupting unwind info). 962{ nop 0 } 9631: br.cloop.sptk.few 1b 964 ;; 965 mov ar.lc=r2 966 br.ret.sptk.many rp 967END(ia64_delay_loop) 968 969/* 970 * Return a CPU-local timestamp in nano-seconds. This timestamp is 971 * NOT synchronized across CPUs its return value must never be 972 * compared against the values returned on another CPU. The usage in 973 * kernel/sched.c ensures that. 974 * 975 * The return-value of sched_clock() is NOT supposed to wrap-around. 976 * If it did, it would cause some scheduling hiccups (at the worst). 977 * Fortunately, with a 64-bit cycle-counter ticking at 100GHz, even 978 * that would happen only once every 5+ years. 979 * 980 * The code below basically calculates: 981 * 982 * (ia64_get_itc() * local_cpu_data->nsec_per_cyc) >> IA64_NSEC_PER_CYC_SHIFT 983 * 984 * except that the multiplication and the shift are done with 128-bit 985 * intermediate precision so that we can produce a full 64-bit result. 986 */ 987GLOBAL_ENTRY(sched_clock) 988 addl r8=THIS_CPU(cpu_info) + IA64_CPUINFO_NSEC_PER_CYC_OFFSET,r0 989 mov.m r9=ar.itc // fetch cycle-counter (35 cyc) 990 ;; 991 ldf8 f8=[r8] 992 ;; 993 setf.sig f9=r9 // certain to stall, so issue it _after_ ldf8... 994 ;; 995 xmpy.lu f10=f9,f8 // calculate low 64 bits of 128-bit product (4 cyc) 996 xmpy.hu f11=f9,f8 // calculate high 64 bits of 128-bit product 997 ;; 998 getf.sig r8=f10 // (5 cyc) 999 getf.sig r9=f11 1000 ;; 1001 shrp r8=r9,r8,IA64_NSEC_PER_CYC_SHIFT 1002 br.ret.sptk.many rp 1003END(sched_clock) 1004 1005#ifdef CONFIG_VIRT_CPU_ACCOUNTING 1006GLOBAL_ENTRY(cycle_to_cputime) 1007 alloc r16=ar.pfs,1,0,0,0 1008 addl r8=THIS_CPU(cpu_info) + IA64_CPUINFO_NSEC_PER_CYC_OFFSET,r0 1009 ;; 1010 ldf8 f8=[r8] 1011 ;; 1012 setf.sig f9=r32 1013 ;; 1014 xmpy.lu f10=f9,f8 // calculate low 64 bits of 128-bit product (4 cyc) 1015 xmpy.hu f11=f9,f8 // calculate high 64 bits of 128-bit product 1016 ;; 1017 getf.sig r8=f10 // (5 cyc) 1018 getf.sig r9=f11 1019 ;; 1020 shrp r8=r9,r8,IA64_NSEC_PER_CYC_SHIFT 1021 br.ret.sptk.many rp 1022END(cycle_to_cputime) 1023#endif /* CONFIG_VIRT_CPU_ACCOUNTING */ 1024 1025GLOBAL_ENTRY(start_kernel_thread) 1026 .prologue 1027 .save rp, r0 // this is the end of the call-chain 1028 .body 1029 alloc r2 = ar.pfs, 0, 0, 2, 0 1030 mov out0 = r9 1031 mov out1 = r11;; 1032 br.call.sptk.many rp = kernel_thread_helper;; 1033 mov out0 = r8 1034 br.call.sptk.many rp = sys_exit;; 10351: br.sptk.few 1b // not reached 1036END(start_kernel_thread) 1037 1038#ifdef CONFIG_IA64_BRL_EMU 1039 1040/* 1041 * Assembly routines used by brl_emu.c to set preserved register state. 1042 */ 1043 1044#define SET_REG(reg) \ 1045 GLOBAL_ENTRY(ia64_set_##reg); \ 1046 alloc r16=ar.pfs,1,0,0,0; \ 1047 mov reg=r32; \ 1048 ;; \ 1049 br.ret.sptk.many rp; \ 1050 END(ia64_set_##reg) 1051 1052SET_REG(b1); 1053SET_REG(b2); 1054SET_REG(b3); 1055SET_REG(b4); 1056SET_REG(b5); 1057 1058#endif /* CONFIG_IA64_BRL_EMU */ 1059 1060#ifdef CONFIG_SMP 1061 /* 1062 * This routine handles spinlock contention. It uses a non-standard calling 1063 * convention to avoid converting leaf routines into interior routines. Because 1064 * of this special convention, there are several restrictions: 1065 * 1066 * - do not use gp relative variables, this code is called from the kernel 1067 * and from modules, r1 is undefined. 1068 * - do not use stacked registers, the caller owns them. 1069 * - do not use the scratch stack space, the caller owns it. 1070 * - do not use any registers other than the ones listed below 1071 * 1072 * Inputs: 1073 * ar.pfs - saved CFM of caller 1074 * ar.ccv - 0 (and available for use) 1075 * r27 - flags from spin_lock_irqsave or 0. Must be preserved. 1076 * r28 - available for use. 1077 * r29 - available for use. 1078 * r30 - available for use. 1079 * r31 - address of lock, available for use. 1080 * b6 - return address 1081 * p14 - available for use. 1082 * p15 - used to track flag status. 1083 * 1084 * If you patch this code to use more registers, do not forget to update 1085 * the clobber lists for spin_lock() in include/asm-ia64/spinlock.h. 1086 */ 1087 1088#if (__GNUC__ == 3 && __GNUC_MINOR__ < 3) 1089 1090GLOBAL_ENTRY(ia64_spinlock_contention_pre3_4) 1091 .prologue 1092 .save ar.pfs, r0 // this code effectively has a zero frame size 1093 .save rp, r28 1094 .body 1095 nop 0 1096 tbit.nz p15,p0=r27,IA64_PSR_I_BIT 1097 .restore sp // pop existing prologue after next insn 1098 mov b6 = r28 1099 .prologue 1100 .save ar.pfs, r0 1101 .altrp b6 1102 .body 1103 ;; 1104(p15) ssm psr.i // reenable interrupts if they were on 1105 // DavidM says that srlz.d is slow and is not required in this case 1106.wait: 1107 // exponential backoff, kdb, lockmeter etc. go in here 1108 hint @pause 1109 ld4 r30=[r31] // don't use ld4.bias; if it's contended, we won't write the word 1110 nop 0 1111 ;; 1112 cmp4.ne p14,p0=r30,r0 1113(p14) br.cond.sptk.few .wait 1114(p15) rsm psr.i // disable interrupts if we reenabled them 1115 br.cond.sptk.few b6 // lock is now free, try to acquire 1116 .global ia64_spinlock_contention_pre3_4_end // for kernprof 1117ia64_spinlock_contention_pre3_4_end: 1118END(ia64_spinlock_contention_pre3_4) 1119 1120#else 1121 1122GLOBAL_ENTRY(ia64_spinlock_contention) 1123 .prologue 1124 .altrp b6 1125 .body 1126 tbit.nz p15,p0=r27,IA64_PSR_I_BIT 1127 ;; 1128.wait: 1129(p15) ssm psr.i // reenable interrupts if they were on 1130 // DavidM says that srlz.d is slow and is not required in this case 1131.wait2: 1132 // exponential backoff, kdb, lockmeter etc. go in here 1133 hint @pause 1134 ld4 r30=[r31] // don't use ld4.bias; if it's contended, we won't write the word 1135 ;; 1136 cmp4.ne p14,p0=r30,r0 1137 mov r30 = 1 1138(p14) br.cond.sptk.few .wait2 1139(p15) rsm psr.i // disable interrupts if we reenabled them 1140 ;; 1141 cmpxchg4.acq r30=[r31], r30, ar.ccv 1142 ;; 1143 cmp4.ne p14,p0=r0,r30 1144(p14) br.cond.sptk.few .wait 1145 1146 br.ret.sptk.many b6 // lock is now taken 1147END(ia64_spinlock_contention) 1148 1149#endif 1150 1151#ifdef CONFIG_HOTPLUG_CPU 1152GLOBAL_ENTRY(ia64_jump_to_sal) 1153 alloc r16=ar.pfs,1,0,0,0;; 1154 rsm psr.i | psr.ic 1155{ 1156 flushrs 1157 srlz.i 1158} 1159 tpa r25=in0 1160 movl r18=tlb_purge_done;; 1161 DATA_VA_TO_PA(r18);; 1162 mov b1=r18 // Return location 1163 movl r18=ia64_do_tlb_purge;; 1164 DATA_VA_TO_PA(r18);; 1165 mov b2=r18 // doing tlb_flush work 1166 mov ar.rsc=0 // Put RSE in enforced lazy, LE mode 1167 movl r17=1f;; 1168 DATA_VA_TO_PA(r17);; 1169 mov cr.iip=r17 1170 movl r16=SAL_PSR_BITS_TO_SET;; 1171 mov cr.ipsr=r16 1172 mov cr.ifs=r0;; 1173 rfi;; 11741: 1175 /* 1176 * Invalidate all TLB data/inst 1177 */ 1178 br.sptk.many b2;; // jump to tlb purge code 1179 1180tlb_purge_done: 1181 RESTORE_REGION_REGS(r25, r17,r18,r19);; 1182 RESTORE_REG(b0, r25, r17);; 1183 RESTORE_REG(b1, r25, r17);; 1184 RESTORE_REG(b2, r25, r17);; 1185 RESTORE_REG(b3, r25, r17);; 1186 RESTORE_REG(b4, r25, r17);; 1187 RESTORE_REG(b5, r25, r17);; 1188 ld8 r1=[r25],0x08;; 1189 ld8 r12=[r25],0x08;; 1190 ld8 r13=[r25],0x08;; 1191 RESTORE_REG(ar.fpsr, r25, r17);; 1192 RESTORE_REG(ar.pfs, r25, r17);; 1193 RESTORE_REG(ar.rnat, r25, r17);; 1194 RESTORE_REG(ar.unat, r25, r17);; 1195 RESTORE_REG(ar.bspstore, r25, r17);; 1196 RESTORE_REG(cr.dcr, r25, r17);; 1197 RESTORE_REG(cr.iva, r25, r17);; 1198 RESTORE_REG(cr.pta, r25, r17);; 1199 srlz.d;; // required not to violate RAW dependency 1200 RESTORE_REG(cr.itv, r25, r17);; 1201 RESTORE_REG(cr.pmv, r25, r17);; 1202 RESTORE_REG(cr.cmcv, r25, r17);; 1203 RESTORE_REG(cr.lrr0, r25, r17);; 1204 RESTORE_REG(cr.lrr1, r25, r17);; 1205 ld8 r4=[r25],0x08;; 1206 ld8 r5=[r25],0x08;; 1207 ld8 r6=[r25],0x08;; 1208 ld8 r7=[r25],0x08;; 1209 ld8 r17=[r25],0x08;; 1210 mov pr=r17,-1;; 1211 RESTORE_REG(ar.lc, r25, r17);; 1212 /* 1213 * Now Restore floating point regs 1214 */ 1215 ldf.fill.nta f2=[r25],16;; 1216 ldf.fill.nta f3=[r25],16;; 1217 ldf.fill.nta f4=[r25],16;; 1218 ldf.fill.nta f5=[r25],16;; 1219 ldf.fill.nta f16=[r25],16;; 1220 ldf.fill.nta f17=[r25],16;; 1221 ldf.fill.nta f18=[r25],16;; 1222 ldf.fill.nta f19=[r25],16;; 1223 ldf.fill.nta f20=[r25],16;; 1224 ldf.fill.nta f21=[r25],16;; 1225 ldf.fill.nta f22=[r25],16;; 1226 ldf.fill.nta f23=[r25],16;; 1227 ldf.fill.nta f24=[r25],16;; 1228 ldf.fill.nta f25=[r25],16;; 1229 ldf.fill.nta f26=[r25],16;; 1230 ldf.fill.nta f27=[r25],16;; 1231 ldf.fill.nta f28=[r25],16;; 1232 ldf.fill.nta f29=[r25],16;; 1233 ldf.fill.nta f30=[r25],16;; 1234 ldf.fill.nta f31=[r25],16;; 1235 1236 /* 1237 * Now that we have done all the register restores 1238 * we are now ready for the big DIVE to SAL Land 1239 */ 1240 ssm psr.ic;; 1241 srlz.d;; 1242 br.ret.sptk.many b0;; 1243END(ia64_jump_to_sal) 1244#endif /* CONFIG_HOTPLUG_CPU */ 1245 1246#endif /* CONFIG_SMP */ 1247