1/* 2 * This file contains the code that gets mapped at the upper end of each task's text 3 * region. For now, it contains the signal trampoline code only. 4 * 5 * Copyright (C) 1999-2003 Hewlett-Packard Co 6 * David Mosberger-Tang <davidm@hpl.hp.com> 7 */ 8 9#include <linux/config.h> 10 11#include <asm/asmmacro.h> 12#include <asm/errno.h> 13#include <asm/asm-offsets.h> 14#include <asm/sigcontext.h> 15#include <asm/system.h> 16#include <asm/unistd.h> 17 18/* 19 * We can't easily refer to symbols inside the kernel. To avoid full runtime relocation, 20 * complications with the linker (which likes to create PLT stubs for branches 21 * to targets outside the shared object) and to avoid multi-phase kernel builds, we 22 * simply create minimalistic "patch lists" in special ELF sections. 23 */ 24 .section ".data.patch.fsyscall_table", "a" 25 .previous 26#define LOAD_FSYSCALL_TABLE(reg) \ 27[1:] movl reg=0; \ 28 .xdata4 ".data.patch.fsyscall_table", 1b-. 29 30 .section ".data.patch.brl_fsys_bubble_down", "a" 31 .previous 32#define BRL_COND_FSYS_BUBBLE_DOWN(pr) \ 33[1:](pr)brl.cond.sptk 0; \ 34 .xdata4 ".data.patch.brl_fsys_bubble_down", 1b-. 35 36GLOBAL_ENTRY(__kernel_syscall_via_break) 37 .prologue 38 .altrp b6 39 .body 40 /* 41 * Note: for (fast) syscall restart to work, the break instruction must be 42 * the first one in the bundle addressed by syscall_via_break. 43 */ 44{ .mib 45 break 0x100000 46 nop.i 0 47 br.ret.sptk.many b6 48} 49END(__kernel_syscall_via_break) 50 51/* 52 * On entry: 53 * r11 = saved ar.pfs 54 * r15 = system call # 55 * b0 = saved return address 56 * b6 = return address 57 * On exit: 58 * r11 = saved ar.pfs 59 * r15 = system call # 60 * b0 = saved return address 61 * all other "scratch" registers: undefined 62 * all "preserved" registers: same as on entry 63 */ 64 65GLOBAL_ENTRY(__kernel_syscall_via_epc) 66 .prologue 67 .altrp b6 68 .body 69{ 70 /* 71 * Note: the kernel cannot assume that the first two instructions in this 72 * bundle get executed. The remaining code must be safe even if 73 * they do not get executed. 74 */ 75 adds r17=-1024,r15 // A 76 mov r10=0 // A default to successful syscall execution 77 epc // B causes split-issue 78} 79 ;; 80 rsm psr.be | psr.i // M2 (5 cyc to srlz.d) 81 LOAD_FSYSCALL_TABLE(r14) // X 82 ;; 83 mov r16=IA64_KR(CURRENT) // M2 (12 cyc) 84 shladd r18=r17,3,r14 // A 85 mov r19=NR_syscalls-1 // A 86 ;; 87 lfetch [r18] // M0|1 88 mov r29=psr // M2 (12 cyc) 89 // If r17 is a NaT, p6 will be zero 90 cmp.geu p6,p7=r19,r17 // A (sysnr > 0 && sysnr < 1024+NR_syscalls)? 91 ;; 92 mov r21=ar.fpsr // M2 (12 cyc) 93 tnat.nz p10,p9=r15 // I0 94 mov.i r26=ar.pfs // I0 (would stall anyhow due to srlz.d...) 95 ;; 96 srlz.d // M0 (forces split-issue) ensure PSR.BE==0 97(p6) ld8 r18=[r18] // M0|1 98 nop.i 0 99 ;; 100 nop.m 0 101(p6) tbit.z.unc p8,p0=r18,0 // I0 (dual-issues with "mov b7=r18"!) 102 nop.i 0 103 ;; 104(p8) ssm psr.i 105(p6) mov b7=r18 // I0 106(p8) br.dptk.many b7 // B 107 108 mov r27=ar.rsc // M2 (12 cyc) 109/* 110 * brl.cond doesn't work as intended because the linker would convert this branch 111 * into a branch to a PLT. Perhaps there will be a way to avoid this with some 112 * future version of the linker. In the meantime, we just use an indirect branch 113 * instead. 114 */ 115#ifdef CONFIG_ITANIUM 116(p6) add r14=-8,r14 // r14 <- addr of fsys_bubble_down entry 117 ;; 118(p6) ld8 r14=[r14] // r14 <- fsys_bubble_down 119 ;; 120(p6) mov b7=r14 121(p6) br.sptk.many b7 122#else 123 BRL_COND_FSYS_BUBBLE_DOWN(p6) 124#endif 125 ssm psr.i 126 mov r10=-1 127(p10) mov r8=EINVAL 128(p9) mov r8=ENOSYS 129 FSYS_RETURN 130END(__kernel_syscall_via_epc) 131 132# define ARG0_OFF (16 + IA64_SIGFRAME_ARG0_OFFSET) 133# define ARG1_OFF (16 + IA64_SIGFRAME_ARG1_OFFSET) 134# define ARG2_OFF (16 + IA64_SIGFRAME_ARG2_OFFSET) 135# define SIGHANDLER_OFF (16 + IA64_SIGFRAME_HANDLER_OFFSET) 136# define SIGCONTEXT_OFF (16 + IA64_SIGFRAME_SIGCONTEXT_OFFSET) 137 138# define FLAGS_OFF IA64_SIGCONTEXT_FLAGS_OFFSET 139# define CFM_OFF IA64_SIGCONTEXT_CFM_OFFSET 140# define FR6_OFF IA64_SIGCONTEXT_FR6_OFFSET 141# define BSP_OFF IA64_SIGCONTEXT_AR_BSP_OFFSET 142# define RNAT_OFF IA64_SIGCONTEXT_AR_RNAT_OFFSET 143# define UNAT_OFF IA64_SIGCONTEXT_AR_UNAT_OFFSET 144# define FPSR_OFF IA64_SIGCONTEXT_AR_FPSR_OFFSET 145# define PR_OFF IA64_SIGCONTEXT_PR_OFFSET 146# define RP_OFF IA64_SIGCONTEXT_IP_OFFSET 147# define SP_OFF IA64_SIGCONTEXT_R12_OFFSET 148# define RBS_BASE_OFF IA64_SIGCONTEXT_RBS_BASE_OFFSET 149# define LOADRS_OFF IA64_SIGCONTEXT_LOADRS_OFFSET 150# define base0 r2 151# define base1 r3 152 /* 153 * When we get here, the memory stack looks like this: 154 * 155 * +===============================+ 156 * | | 157 * // struct sigframe // 158 * | | 159 * +-------------------------------+ <-- sp+16 160 * | 16 byte of scratch | 161 * | space | 162 * +-------------------------------+ <-- sp 163 * 164 * The register stack looks _exactly_ the way it looked at the time the signal 165 * occurred. In other words, we're treading on a potential mine-field: each 166 * incoming general register may be a NaT value (including sp, in which case the 167 * process ends up dying with a SIGSEGV). 168 * 169 * The first thing need to do is a cover to get the registers onto the backing 170 * store. Once that is done, we invoke the signal handler which may modify some 171 * of the machine state. After returning from the signal handler, we return 172 * control to the previous context by executing a sigreturn system call. A signal 173 * handler may call the rt_sigreturn() function to directly return to a given 174 * sigcontext. However, the user-level sigreturn() needs to do much more than 175 * calling the rt_sigreturn() system call as it needs to unwind the stack to 176 * restore preserved registers that may have been saved on the signal handler's 177 * call stack. 178 */ 179 180#define SIGTRAMP_SAVES \ 181 .unwabi 3, 's'; /* mark this as a sigtramp handler (saves scratch regs) */ \ 182 .unwabi @svr4, 's'; /* backwards compatibility with old unwinders (remove in v2.7) */ \ 183 .savesp ar.unat, UNAT_OFF+SIGCONTEXT_OFF; \ 184 .savesp ar.fpsr, FPSR_OFF+SIGCONTEXT_OFF; \ 185 .savesp pr, PR_OFF+SIGCONTEXT_OFF; \ 186 .savesp rp, RP_OFF+SIGCONTEXT_OFF; \ 187 .savesp ar.pfs, CFM_OFF+SIGCONTEXT_OFF; \ 188 .vframesp SP_OFF+SIGCONTEXT_OFF 189 190GLOBAL_ENTRY(__kernel_sigtramp) 191 // describe the state that is active when we get here: 192 .prologue 193 SIGTRAMP_SAVES 194 .body 195 196 .label_state 1 197 198 adds base0=SIGHANDLER_OFF,sp 199 adds base1=RBS_BASE_OFF+SIGCONTEXT_OFF,sp 200 br.call.sptk.many rp=1f 2011: 202 ld8 r17=[base0],(ARG0_OFF-SIGHANDLER_OFF) // get pointer to signal handler's plabel 203 ld8 r15=[base1] // get address of new RBS base (or NULL) 204 cover // push args in interrupted frame onto backing store 205 ;; 206 cmp.ne p1,p0=r15,r0 // do we need to switch rbs? (note: pr is saved by kernel) 207 mov.m r9=ar.bsp // fetch ar.bsp 208 .spillsp.p p1, ar.rnat, RNAT_OFF+SIGCONTEXT_OFF 209(p1) br.cond.spnt setup_rbs // yup -> (clobbers p8, r14-r16, and r18-r20) 210back_from_setup_rbs: 211 alloc r8=ar.pfs,0,0,3,0 212 ld8 out0=[base0],16 // load arg0 (signum) 213 adds base1=(ARG1_OFF-(RBS_BASE_OFF+SIGCONTEXT_OFF)),base1 214 ;; 215 ld8 out1=[base1] // load arg1 (siginfop) 216 ld8 r10=[r17],8 // get signal handler entry point 217 ;; 218 ld8 out2=[base0] // load arg2 (sigcontextp) 219 ld8 gp=[r17] // get signal handler's global pointer 220 adds base0=(BSP_OFF+SIGCONTEXT_OFF),sp 221 ;; 222 .spillsp ar.bsp, BSP_OFF+SIGCONTEXT_OFF 223 st8 [base0]=r9 // save sc_ar_bsp 224 adds base0=(FR6_OFF+SIGCONTEXT_OFF),sp 225 adds base1=(FR6_OFF+16+SIGCONTEXT_OFF),sp 226 ;; 227 stf.spill [base0]=f6,32 228 stf.spill [base1]=f7,32 229 ;; 230 stf.spill [base0]=f8,32 231 stf.spill [base1]=f9,32 232 mov b6=r10 233 ;; 234 stf.spill [base0]=f10,32 235 stf.spill [base1]=f11,32 236 ;; 237 stf.spill [base0]=f12,32 238 stf.spill [base1]=f13,32 239 ;; 240 stf.spill [base0]=f14,32 241 stf.spill [base1]=f15,32 242 br.call.sptk.many rp=b6 // call the signal handler 243.ret0: adds base0=(BSP_OFF+SIGCONTEXT_OFF),sp 244 ;; 245 ld8 r15=[base0] // fetch sc_ar_bsp 246 mov r14=ar.bsp 247 ;; 248 cmp.ne p1,p0=r14,r15 // do we need to restore the rbs? 249(p1) br.cond.spnt restore_rbs // yup -> (clobbers r14-r18, f6 & f7) 250 ;; 251back_from_restore_rbs: 252 adds base0=(FR6_OFF+SIGCONTEXT_OFF),sp 253 adds base1=(FR6_OFF+16+SIGCONTEXT_OFF),sp 254 ;; 255 ldf.fill f6=[base0],32 256 ldf.fill f7=[base1],32 257 ;; 258 ldf.fill f8=[base0],32 259 ldf.fill f9=[base1],32 260 ;; 261 ldf.fill f10=[base0],32 262 ldf.fill f11=[base1],32 263 ;; 264 ldf.fill f12=[base0],32 265 ldf.fill f13=[base1],32 266 ;; 267 ldf.fill f14=[base0],32 268 ldf.fill f15=[base1],32 269 mov r15=__NR_rt_sigreturn 270 .restore sp // pop .prologue 271 break __BREAK_SYSCALL 272 273 .prologue 274 SIGTRAMP_SAVES 275setup_rbs: 276 mov ar.rsc=0 // put RSE into enforced lazy mode 277 ;; 278 .save ar.rnat, r19 279 mov r19=ar.rnat // save RNaT before switching backing store area 280 adds r14=(RNAT_OFF+SIGCONTEXT_OFF),sp 281 282 mov r18=ar.bspstore 283 mov ar.bspstore=r15 // switch over to new register backing store area 284 ;; 285 286 .spillsp ar.rnat, RNAT_OFF+SIGCONTEXT_OFF 287 st8 [r14]=r19 // save sc_ar_rnat 288 .body 289 mov.m r16=ar.bsp // sc_loadrs <- (new bsp - new bspstore) << 16 290 adds r14=(LOADRS_OFF+SIGCONTEXT_OFF),sp 291 ;; 292 invala 293 sub r15=r16,r15 294 extr.u r20=r18,3,6 295 ;; 296 mov ar.rsc=0xf // set RSE into eager mode, pl 3 297 cmp.eq p8,p0=63,r20 298 shl r15=r15,16 299 ;; 300 st8 [r14]=r15 // save sc_loadrs 301(p8) st8 [r18]=r19 // if bspstore points at RNaT slot, store RNaT there now 302 .restore sp // pop .prologue 303 br.cond.sptk back_from_setup_rbs 304 305 .prologue 306 SIGTRAMP_SAVES 307 .spillsp ar.rnat, RNAT_OFF+SIGCONTEXT_OFF 308 .body 309restore_rbs: 310 // On input: 311 // r14 = bsp1 (bsp at the time of return from signal handler) 312 // r15 = bsp0 (bsp at the time the signal occurred) 313 // 314 // Here, we need to calculate bspstore0, the value that ar.bspstore needs 315 // to be set to, based on bsp0 and the size of the dirty partition on 316 // the alternate stack (sc_loadrs >> 16). This can be done with the 317 // following algorithm: 318 // 319 // bspstore0 = rse_skip_regs(bsp0, -rse_num_regs(bsp1 - (loadrs >> 19), bsp1)); 320 // 321 // This is what the code below does. 322 // 323 alloc r2=ar.pfs,0,0,0,0 // alloc null frame 324 adds r16=(LOADRS_OFF+SIGCONTEXT_OFF),sp 325 adds r18=(RNAT_OFF+SIGCONTEXT_OFF),sp 326 ;; 327 ld8 r17=[r16] 328 ld8 r16=[r18] // get new rnat 329 extr.u r18=r15,3,6 // r18 <- rse_slot_num(bsp0) 330 ;; 331 mov ar.rsc=r17 // put RSE into enforced lazy mode 332 shr.u r17=r17,16 333 ;; 334 sub r14=r14,r17 // r14 (bspstore1) <- bsp1 - (sc_loadrs >> 16) 335 shr.u r17=r17,3 // r17 <- (sc_loadrs >> 19) 336 ;; 337 loadrs // restore dirty partition 338 extr.u r14=r14,3,6 // r14 <- rse_slot_num(bspstore1) 339 ;; 340 add r14=r14,r17 // r14 <- rse_slot_num(bspstore1) + (sc_loadrs >> 19) 341 ;; 342 shr.u r14=r14,6 // r14 <- (rse_slot_num(bspstore1) + (sc_loadrs >> 19))/0x40 343 ;; 344 sub r14=r14,r17 // r14 <- -rse_num_regs(bspstore1, bsp1) 345 movl r17=0x8208208208208209 346 ;; 347 add r18=r18,r14 // r18 (delta) <- rse_slot_num(bsp0) - rse_num_regs(bspstore1,bsp1) 348 setf.sig f7=r17 349 cmp.lt p7,p0=r14,r0 // p7 <- (r14 < 0)? 350 ;; 351(p7) adds r18=-62,r18 // delta -= 62 352 ;; 353 setf.sig f6=r18 354 ;; 355 xmpy.h f6=f6,f7 356 ;; 357 getf.sig r17=f6 358 ;; 359 add r17=r17,r18 360 shr r18=r18,63 361 ;; 362 shr r17=r17,5 363 ;; 364 sub r17=r17,r18 // r17 = delta/63 365 ;; 366 add r17=r14,r17 // r17 <- delta/63 - rse_num_regs(bspstore1, bsp1) 367 ;; 368 shladd r15=r17,3,r15 // r15 <- bsp0 + 8*(delta/63 - rse_num_regs(bspstore1, bsp1)) 369 ;; 370 mov ar.bspstore=r15 // switch back to old register backing store area 371 ;; 372 mov ar.rnat=r16 // restore RNaT 373 mov ar.rsc=0xf // (will be restored later on from sc_ar_rsc) 374 // invala not necessary as that will happen when returning to user-mode 375 br.cond.sptk back_from_restore_rbs 376END(__kernel_sigtramp) 377