1/* 2 * ia64/kernel/entry.S 3 * 4 * Kernel entry points. 5 * 6 * Copyright (C) 1998-2003, 2005 Hewlett-Packard Co 7 * David Mosberger-Tang <davidm@hpl.hp.com> 8 * Copyright (C) 1999, 2002-2003 9 * Asit Mallick <Asit.K.Mallick@intel.com> 10 * Don Dugger <Don.Dugger@intel.com> 11 * Suresh Siddha <suresh.b.siddha@intel.com> 12 * Fenghua Yu <fenghua.yu@intel.com> 13 * Copyright (C) 1999 VA Linux Systems 14 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com> 15 */ 16/* 17 * ia64_switch_to now places correct virtual mapping in in TR2 for 18 * kernel stack. This allows us to handle interrupts without changing 19 * to physical mode. 20 * 21 * Jonathan Nicklin <nicklin@missioncriticallinux.com> 22 * Patrick O'Rourke <orourke@missioncriticallinux.com> 23 * 11/07/2000 24 */ 25/* 26 * Global (preserved) predicate usage on syscall entry/exit path: 27 * 28 * pKStk: See entry.h. 29 * pUStk: See entry.h. 30 * pSys: See entry.h. 31 * pNonSys: !pSys 32 */ 33 34#include <linux/config.h> 35 36#include <asm/asmmacro.h> 37#include <asm/cache.h> 38#include <asm/errno.h> 39#include <asm/kregs.h> 40#include <asm/asm-offsets.h> 41#include <asm/pgtable.h> 42#include <asm/percpu.h> 43#include <asm/processor.h> 44#include <asm/thread_info.h> 45#include <asm/unistd.h> 46 47#include "minstate.h" 48 49 /* 50 * execve() is special because in case of success, we need to 51 * setup a null register window frame. 52 */ 53ENTRY(ia64_execve) 54 /* 55 * Allocate 8 input registers since ptrace() may clobber them 56 */ 57 .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8) 58 alloc loc1=ar.pfs,8,2,4,0 59 mov loc0=rp 60 .body 61 mov out0=in0 // filename 62 ;; // stop bit between alloc and call 63 mov out1=in1 // argv 64 mov out2=in2 // envp 65 add out3=16,sp // regs 66 br.call.sptk.many rp=sys_execve 67.ret0: 68#ifdef CONFIG_IA32_SUPPORT 69 /* 70 * Check if we're returning to ia32 mode. If so, we need to restore ia32 registers 71 * from pt_regs. 72 */ 73 adds r16=PT(CR_IPSR)+16,sp 74 ;; 75 ld8 r16=[r16] 76#endif 77 cmp4.ge p6,p7=r8,r0 78 mov ar.pfs=loc1 // restore ar.pfs 79 sxt4 r8=r8 // return 64-bit result 80 ;; 81 stf.spill [sp]=f0 82(p6) cmp.ne pKStk,pUStk=r0,r0 // a successful execve() lands us in user-mode... 83 mov rp=loc0 84(p6) mov ar.pfs=r0 // clear ar.pfs on success 85(p7) br.ret.sptk.many rp 86 87 /* 88 * In theory, we'd have to zap this state only to prevent leaking of 89 * security sensitive state (e.g., if current->mm->dumpable is zero). However, 90 * this executes in less than 20 cycles even on Itanium, so it's not worth 91 * optimizing for...). 92 */ 93 mov ar.unat=0; mov ar.lc=0 94 mov r4=0; mov f2=f0; mov b1=r0 95 mov r5=0; mov f3=f0; mov b2=r0 96 mov r6=0; mov f4=f0; mov b3=r0 97 mov r7=0; mov f5=f0; mov b4=r0 98 ldf.fill f12=[sp]; mov f13=f0; mov b5=r0 99 ldf.fill f14=[sp]; ldf.fill f15=[sp]; mov f16=f0 100 ldf.fill f17=[sp]; ldf.fill f18=[sp]; mov f19=f0 101 ldf.fill f20=[sp]; ldf.fill f21=[sp]; mov f22=f0 102 ldf.fill f23=[sp]; ldf.fill f24=[sp]; mov f25=f0 103 ldf.fill f26=[sp]; ldf.fill f27=[sp]; mov f28=f0 104 ldf.fill f29=[sp]; ldf.fill f30=[sp]; mov f31=f0 105#ifdef CONFIG_IA32_SUPPORT 106 tbit.nz p6,p0=r16, IA64_PSR_IS_BIT 107 movl loc0=ia64_ret_from_ia32_execve 108 ;; 109(p6) mov rp=loc0 110#endif 111 br.ret.sptk.many rp 112END(ia64_execve) 113 114/* 115 * sys_clone2(u64 flags, u64 ustack_base, u64 ustack_size, u64 parent_tidptr, u64 child_tidptr, 116 * u64 tls) 117 */ 118GLOBAL_ENTRY(sys_clone2) 119 /* 120 * Allocate 8 input registers since ptrace() may clobber them 121 */ 122 .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8) 123 alloc r16=ar.pfs,8,2,6,0 124 DO_SAVE_SWITCH_STACK 125 adds r2=PT(R16)+IA64_SWITCH_STACK_SIZE+16,sp 126 mov loc0=rp 127 mov loc1=r16 // save ar.pfs across do_fork 128 .body 129 mov out1=in1 130 mov out3=in2 131 tbit.nz p6,p0=in0,CLONE_SETTLS_BIT 132 mov out4=in3 // parent_tidptr: valid only w/CLONE_PARENT_SETTID 133 ;; 134(p6) st8 [r2]=in5 // store TLS in r16 for copy_thread() 135 mov out5=in4 // child_tidptr: valid only w/CLONE_CHILD_SETTID or CLONE_CHILD_CLEARTID 136 adds out2=IA64_SWITCH_STACK_SIZE+16,sp // out2 = ®s 137 mov out0=in0 // out0 = clone_flags 138 br.call.sptk.many rp=do_fork 139.ret1: .restore sp 140 adds sp=IA64_SWITCH_STACK_SIZE,sp // pop the switch stack 141 mov ar.pfs=loc1 142 mov rp=loc0 143 br.ret.sptk.many rp 144END(sys_clone2) 145 146/* 147 * sys_clone(u64 flags, u64 ustack_base, u64 parent_tidptr, u64 child_tidptr, u64 tls) 148 * Deprecated. Use sys_clone2() instead. 149 */ 150GLOBAL_ENTRY(sys_clone) 151 /* 152 * Allocate 8 input registers since ptrace() may clobber them 153 */ 154 .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8) 155 alloc r16=ar.pfs,8,2,6,0 156 DO_SAVE_SWITCH_STACK 157 adds r2=PT(R16)+IA64_SWITCH_STACK_SIZE+16,sp 158 mov loc0=rp 159 mov loc1=r16 // save ar.pfs across do_fork 160 .body 161 mov out1=in1 162 mov out3=16 // stacksize (compensates for 16-byte scratch area) 163 tbit.nz p6,p0=in0,CLONE_SETTLS_BIT 164 mov out4=in2 // parent_tidptr: valid only w/CLONE_PARENT_SETTID 165 ;; 166(p6) st8 [r2]=in4 // store TLS in r13 (tp) 167 mov out5=in3 // child_tidptr: valid only w/CLONE_CHILD_SETTID or CLONE_CHILD_CLEARTID 168 adds out2=IA64_SWITCH_STACK_SIZE+16,sp // out2 = ®s 169 mov out0=in0 // out0 = clone_flags 170 br.call.sptk.many rp=do_fork 171.ret2: .restore sp 172 adds sp=IA64_SWITCH_STACK_SIZE,sp // pop the switch stack 173 mov ar.pfs=loc1 174 mov rp=loc0 175 br.ret.sptk.many rp 176END(sys_clone) 177 178/* 179 * prev_task <- ia64_switch_to(struct task_struct *next) 180 * With Ingo's new scheduler, interrupts are disabled when this routine gets 181 * called. The code starting at .map relies on this. The rest of the code 182 * doesn't care about the interrupt masking status. 183 */ 184GLOBAL_ENTRY(ia64_switch_to) 185 .prologue 186 alloc r16=ar.pfs,1,0,0,0 187 DO_SAVE_SWITCH_STACK 188 .body 189 190 adds r22=IA64_TASK_THREAD_KSP_OFFSET,r13 191 movl r25=init_task 192 mov r27=IA64_KR(CURRENT_STACK) 193 adds r21=IA64_TASK_THREAD_KSP_OFFSET,in0 194 dep r20=0,in0,61,3 // physical address of "next" 195 ;; 196 st8 [r22]=sp // save kernel stack pointer of old task 197 shr.u r26=r20,IA64_GRANULE_SHIFT 198 cmp.eq p7,p6=r25,in0 199 ;; 200 /* 201 * If we've already mapped this task's page, we can skip doing it again. 202 */ 203(p6) cmp.eq p7,p6=r26,r27 204(p6) br.cond.dpnt .map 205 ;; 206.done: 207 ld8 sp=[r21] // load kernel stack pointer of new task 208 mov IA64_KR(CURRENT)=in0 // update "current" application register 209 mov r8=r13 // return pointer to previously running task 210 mov r13=in0 // set "current" pointer 211 ;; 212 DO_LOAD_SWITCH_STACK 213 214#ifdef CONFIG_SMP 215 sync.i // ensure "fc"s done by this CPU are visible on other CPUs 216#endif 217 br.ret.sptk.many rp // boogie on out in new context 218 219.map: 220 rsm psr.ic // interrupts (psr.i) are already disabled here 221 movl r25=PAGE_KERNEL 222 ;; 223 srlz.d 224 or r23=r25,r20 // construct PA | page properties 225 mov r25=IA64_GRANULE_SHIFT<<2 226 ;; 227 mov cr.itir=r25 228 mov cr.ifa=in0 // VA of next task... 229 ;; 230 mov r25=IA64_TR_CURRENT_STACK 231 mov IA64_KR(CURRENT_STACK)=r26 // remember last page we mapped... 232 ;; 233 itr.d dtr[r25]=r23 // wire in new mapping... 234 ssm psr.ic // reenable the psr.ic bit 235 ;; 236 srlz.d 237 br.cond.sptk .done 238END(ia64_switch_to) 239 240/* 241 * Note that interrupts are enabled during save_switch_stack and load_switch_stack. This 242 * means that we may get an interrupt with "sp" pointing to the new kernel stack while 243 * ar.bspstore is still pointing to the old kernel backing store area. Since ar.rsc, 244 * ar.rnat, ar.bsp, and ar.bspstore are all preserved by interrupts, this is not a 245 * problem. Also, we don't need to specify unwind information for preserved registers 246 * that are not modified in save_switch_stack as the right unwind information is already 247 * specified at the call-site of save_switch_stack. 248 */ 249 250/* 251 * save_switch_stack: 252 * - r16 holds ar.pfs 253 * - b7 holds address to return to 254 * - rp (b0) holds return address to save 255 */ 256GLOBAL_ENTRY(save_switch_stack) 257 .prologue 258 .altrp b7 259 flushrs // flush dirty regs to backing store (must be first in insn group) 260 .save @priunat,r17 261 mov r17=ar.unat // preserve caller's 262 .body 263#ifdef CONFIG_ITANIUM 264 adds r2=16+128,sp 265 adds r3=16+64,sp 266 adds r14=SW(R4)+16,sp 267 ;; 268 st8.spill [r14]=r4,16 // spill r4 269 lfetch.fault.excl.nt1 [r3],128 270 ;; 271 lfetch.fault.excl.nt1 [r2],128 272 lfetch.fault.excl.nt1 [r3],128 273 ;; 274 lfetch.fault.excl [r2] 275 lfetch.fault.excl [r3] 276 adds r15=SW(R5)+16,sp 277#else 278 add r2=16+3*128,sp 279 add r3=16,sp 280 add r14=SW(R4)+16,sp 281 ;; 282 st8.spill [r14]=r4,SW(R6)-SW(R4) // spill r4 and prefetch offset 0x1c0 283 lfetch.fault.excl.nt1 [r3],128 // prefetch offset 0x010 284 ;; 285 lfetch.fault.excl.nt1 [r3],128 // prefetch offset 0x090 286 lfetch.fault.excl.nt1 [r2],128 // prefetch offset 0x190 287 ;; 288 lfetch.fault.excl.nt1 [r3] // prefetch offset 0x110 289 lfetch.fault.excl.nt1 [r2] // prefetch offset 0x210 290 adds r15=SW(R5)+16,sp 291#endif 292 ;; 293 st8.spill [r15]=r5,SW(R7)-SW(R5) // spill r5 294 mov.m ar.rsc=0 // put RSE in mode: enforced lazy, little endian, pl 0 295 add r2=SW(F2)+16,sp // r2 = &sw->f2 296 ;; 297 st8.spill [r14]=r6,SW(B0)-SW(R6) // spill r6 298 mov.m r18=ar.fpsr // preserve fpsr 299 add r3=SW(F3)+16,sp // r3 = &sw->f3 300 ;; 301 stf.spill [r2]=f2,32 302 mov.m r19=ar.rnat 303 mov r21=b0 304 305 stf.spill [r3]=f3,32 306 st8.spill [r15]=r7,SW(B2)-SW(R7) // spill r7 307 mov r22=b1 308 ;; 309 // since we're done with the spills, read and save ar.unat: 310 mov.m r29=ar.unat 311 mov.m r20=ar.bspstore 312 mov r23=b2 313 stf.spill [r2]=f4,32 314 stf.spill [r3]=f5,32 315 mov r24=b3 316 ;; 317 st8 [r14]=r21,SW(B1)-SW(B0) // save b0 318 st8 [r15]=r23,SW(B3)-SW(B2) // save b2 319 mov r25=b4 320 mov r26=b5 321 ;; 322 st8 [r14]=r22,SW(B4)-SW(B1) // save b1 323 st8 [r15]=r24,SW(AR_PFS)-SW(B3) // save b3 324 mov r21=ar.lc // I-unit 325 stf.spill [r2]=f12,32 326 stf.spill [r3]=f13,32 327 ;; 328 st8 [r14]=r25,SW(B5)-SW(B4) // save b4 329 st8 [r15]=r16,SW(AR_LC)-SW(AR_PFS) // save ar.pfs 330 stf.spill [r2]=f14,32 331 stf.spill [r3]=f15,32 332 ;; 333 st8 [r14]=r26 // save b5 334 st8 [r15]=r21 // save ar.lc 335 stf.spill [r2]=f16,32 336 stf.spill [r3]=f17,32 337 ;; 338 stf.spill [r2]=f18,32 339 stf.spill [r3]=f19,32 340 ;; 341 stf.spill [r2]=f20,32 342 stf.spill [r3]=f21,32 343 ;; 344 stf.spill [r2]=f22,32 345 stf.spill [r3]=f23,32 346 ;; 347 stf.spill [r2]=f24,32 348 stf.spill [r3]=f25,32 349 ;; 350 stf.spill [r2]=f26,32 351 stf.spill [r3]=f27,32 352 ;; 353 stf.spill [r2]=f28,32 354 stf.spill [r3]=f29,32 355 ;; 356 stf.spill [r2]=f30,SW(AR_UNAT)-SW(F30) 357 stf.spill [r3]=f31,SW(PR)-SW(F31) 358 add r14=SW(CALLER_UNAT)+16,sp 359 ;; 360 st8 [r2]=r29,SW(AR_RNAT)-SW(AR_UNAT) // save ar.unat 361 st8 [r14]=r17,SW(AR_FPSR)-SW(CALLER_UNAT) // save caller_unat 362 mov r21=pr 363 ;; 364 st8 [r2]=r19,SW(AR_BSPSTORE)-SW(AR_RNAT) // save ar.rnat 365 st8 [r3]=r21 // save predicate registers 366 ;; 367 st8 [r2]=r20 // save ar.bspstore 368 st8 [r14]=r18 // save fpsr 369 mov ar.rsc=3 // put RSE back into eager mode, pl 0 370 br.cond.sptk.many b7 371END(save_switch_stack) 372 373/* 374 * load_switch_stack: 375 * - "invala" MUST be done at call site (normally in DO_LOAD_SWITCH_STACK) 376 * - b7 holds address to return to 377 * - must not touch r8-r11 378 */ 379ENTRY(load_switch_stack) 380 .prologue 381 .altrp b7 382 383 .body 384 lfetch.fault.nt1 [sp] 385 adds r2=SW(AR_BSPSTORE)+16,sp 386 adds r3=SW(AR_UNAT)+16,sp 387 mov ar.rsc=0 // put RSE into enforced lazy mode 388 adds r14=SW(CALLER_UNAT)+16,sp 389 adds r15=SW(AR_FPSR)+16,sp 390 ;; 391 ld8 r27=[r2],(SW(B0)-SW(AR_BSPSTORE)) // bspstore 392 ld8 r29=[r3],(SW(B1)-SW(AR_UNAT)) // unat 393 ;; 394 ld8 r21=[r2],16 // restore b0 395 ld8 r22=[r3],16 // restore b1 396 ;; 397 ld8 r23=[r2],16 // restore b2 398 ld8 r24=[r3],16 // restore b3 399 ;; 400 ld8 r25=[r2],16 // restore b4 401 ld8 r26=[r3],16 // restore b5 402 ;; 403 ld8 r16=[r2],(SW(PR)-SW(AR_PFS)) // ar.pfs 404 ld8 r17=[r3],(SW(AR_RNAT)-SW(AR_LC)) // ar.lc 405 ;; 406 ld8 r28=[r2] // restore pr 407 ld8 r30=[r3] // restore rnat 408 ;; 409 ld8 r18=[r14],16 // restore caller's unat 410 ld8 r19=[r15],24 // restore fpsr 411 ;; 412 ldf.fill f2=[r14],32 413 ldf.fill f3=[r15],32 414 ;; 415 ldf.fill f4=[r14],32 416 ldf.fill f5=[r15],32 417 ;; 418 ldf.fill f12=[r14],32 419 ldf.fill f13=[r15],32 420 ;; 421 ldf.fill f14=[r14],32 422 ldf.fill f15=[r15],32 423 ;; 424 ldf.fill f16=[r14],32 425 ldf.fill f17=[r15],32 426 ;; 427 ldf.fill f18=[r14],32 428 ldf.fill f19=[r15],32 429 mov b0=r21 430 ;; 431 ldf.fill f20=[r14],32 432 ldf.fill f21=[r15],32 433 mov b1=r22 434 ;; 435 ldf.fill f22=[r14],32 436 ldf.fill f23=[r15],32 437 mov b2=r23 438 ;; 439 mov ar.bspstore=r27 440 mov ar.unat=r29 // establish unat holding the NaT bits for r4-r7 441 mov b3=r24 442 ;; 443 ldf.fill f24=[r14],32 444 ldf.fill f25=[r15],32 445 mov b4=r25 446 ;; 447 ldf.fill f26=[r14],32 448 ldf.fill f27=[r15],32 449 mov b5=r26 450 ;; 451 ldf.fill f28=[r14],32 452 ldf.fill f29=[r15],32 453 mov ar.pfs=r16 454 ;; 455 ldf.fill f30=[r14],32 456 ldf.fill f31=[r15],24 457 mov ar.lc=r17 458 ;; 459 ld8.fill r4=[r14],16 460 ld8.fill r5=[r15],16 461 mov pr=r28,-1 462 ;; 463 ld8.fill r6=[r14],16 464 ld8.fill r7=[r15],16 465 466 mov ar.unat=r18 // restore caller's unat 467 mov ar.rnat=r30 // must restore after bspstore but before rsc! 468 mov ar.fpsr=r19 // restore fpsr 469 mov ar.rsc=3 // put RSE back into eager mode, pl 0 470 br.cond.sptk.many b7 471END(load_switch_stack) 472 473GLOBAL_ENTRY(prefetch_stack) 474 add r14 = -IA64_SWITCH_STACK_SIZE, sp 475 add r15 = IA64_TASK_THREAD_KSP_OFFSET, in0 476 ;; 477 ld8 r16 = [r15] // load next's stack pointer 478 lfetch.fault.excl [r14], 128 479 ;; 480 lfetch.fault.excl [r14], 128 481 lfetch.fault [r16], 128 482 ;; 483 lfetch.fault.excl [r14], 128 484 lfetch.fault [r16], 128 485 ;; 486 lfetch.fault.excl [r14], 128 487 lfetch.fault [r16], 128 488 ;; 489 lfetch.fault.excl [r14], 128 490 lfetch.fault [r16], 128 491 ;; 492 lfetch.fault [r16], 128 493 br.ret.sptk.many rp 494END(prefetch_stack) 495 496GLOBAL_ENTRY(execve) 497 mov r15=__NR_execve // put syscall number in place 498 break __BREAK_SYSCALL 499 br.ret.sptk.many rp 500END(execve) 501 502GLOBAL_ENTRY(clone) 503 mov r15=__NR_clone // put syscall number in place 504 break __BREAK_SYSCALL 505 br.ret.sptk.many rp 506END(clone) 507 508 /* 509 * Invoke a system call, but do some tracing before and after the call. 510 * We MUST preserve the current register frame throughout this routine 511 * because some system calls (such as ia64_execve) directly 512 * manipulate ar.pfs. 513 */ 514GLOBAL_ENTRY(ia64_trace_syscall) 515 PT_REGS_UNWIND_INFO(0) 516 /* 517 * We need to preserve the scratch registers f6-f11 in case the system 518 * call is sigreturn. 519 */ 520 adds r16=PT(F6)+16,sp 521 adds r17=PT(F7)+16,sp 522 ;; 523 stf.spill [r16]=f6,32 524 stf.spill [r17]=f7,32 525 ;; 526 stf.spill [r16]=f8,32 527 stf.spill [r17]=f9,32 528 ;; 529 stf.spill [r16]=f10 530 stf.spill [r17]=f11 531 br.call.sptk.many rp=syscall_trace_enter // give parent a chance to catch syscall args 532 adds r16=PT(F6)+16,sp 533 adds r17=PT(F7)+16,sp 534 ;; 535 ldf.fill f6=[r16],32 536 ldf.fill f7=[r17],32 537 ;; 538 ldf.fill f8=[r16],32 539 ldf.fill f9=[r17],32 540 ;; 541 ldf.fill f10=[r16] 542 ldf.fill f11=[r17] 543 // the syscall number may have changed, so re-load it and re-calculate the 544 // syscall entry-point: 545 adds r15=PT(R15)+16,sp // r15 = &pt_regs.r15 (syscall #) 546 ;; 547 ld8 r15=[r15] 548 mov r3=NR_syscalls - 1 549 ;; 550 adds r15=-1024,r15 551 movl r16=sys_call_table 552 ;; 553 shladd r20=r15,3,r16 // r20 = sys_call_table + 8*(syscall-1024) 554 cmp.leu p6,p7=r15,r3 555 ;; 556(p6) ld8 r20=[r20] // load address of syscall entry point 557(p7) movl r20=sys_ni_syscall 558 ;; 559 mov b6=r20 560 br.call.sptk.many rp=b6 // do the syscall 561.strace_check_retval: 562 cmp.lt p6,p0=r8,r0 // syscall failed? 563 adds r2=PT(R8)+16,sp // r2 = &pt_regs.r8 564 adds r3=PT(R10)+16,sp // r3 = &pt_regs.r10 565 mov r10=0 566(p6) br.cond.sptk strace_error // syscall failed -> 567 ;; // avoid RAW on r10 568.strace_save_retval: 569.mem.offset 0,0; st8.spill [r2]=r8 // store return value in slot for r8 570.mem.offset 8,0; st8.spill [r3]=r10 // clear error indication in slot for r10 571 br.call.sptk.many rp=syscall_trace_leave // give parent a chance to catch return value 572.ret3: br.cond.sptk .work_pending_syscall_end 573 574strace_error: 575 ld8 r3=[r2] // load pt_regs.r8 576 sub r9=0,r8 // negate return value to get errno value 577 ;; 578 cmp.ne p6,p0=r3,r0 // is pt_regs.r8!=0? 579 adds r3=16,r2 // r3=&pt_regs.r10 580 ;; 581(p6) mov r10=-1 582(p6) mov r8=r9 583 br.cond.sptk .strace_save_retval 584END(ia64_trace_syscall) 585 586 /* 587 * When traced and returning from sigreturn, we invoke syscall_trace but then 588 * go straight to ia64_leave_kernel rather than ia64_leave_syscall. 589 */ 590GLOBAL_ENTRY(ia64_strace_leave_kernel) 591 PT_REGS_UNWIND_INFO(0) 592{ /* 593 * Some versions of gas generate bad unwind info if the first instruction of a 594 * procedure doesn't go into the first slot of a bundle. This is a workaround. 595 */ 596 nop.m 0 597 nop.i 0 598 br.call.sptk.many rp=syscall_trace_leave // give parent a chance to catch return value 599} 600.ret4: br.cond.sptk ia64_leave_kernel 601END(ia64_strace_leave_kernel) 602 603GLOBAL_ENTRY(ia64_ret_from_clone) 604 PT_REGS_UNWIND_INFO(0) 605{ /* 606 * Some versions of gas generate bad unwind info if the first instruction of a 607 * procedure doesn't go into the first slot of a bundle. This is a workaround. 608 */ 609 nop.m 0 610 nop.i 0 611 /* 612 * We need to call schedule_tail() to complete the scheduling process. 613 * Called by ia64_switch_to() after do_fork()->copy_thread(). r8 contains the 614 * address of the previously executing task. 615 */ 616 br.call.sptk.many rp=ia64_invoke_schedule_tail 617} 618.ret8: 619 adds r2=TI_FLAGS+IA64_TASK_SIZE,r13 620 ;; 621 ld4 r2=[r2] 622 ;; 623 mov r8=0 624 and r2=_TIF_SYSCALL_TRACEAUDIT,r2 625 ;; 626 cmp.ne p6,p0=r2,r0 627(p6) br.cond.spnt .strace_check_retval 628 ;; // added stop bits to prevent r8 dependency 629END(ia64_ret_from_clone) 630 // fall through 631GLOBAL_ENTRY(ia64_ret_from_syscall) 632 PT_REGS_UNWIND_INFO(0) 633 cmp.ge p6,p7=r8,r0 // syscall executed successfully? 634 adds r2=PT(R8)+16,sp // r2 = &pt_regs.r8 635 mov r10=r0 // clear error indication in r10 636(p7) br.cond.spnt handle_syscall_error // handle potential syscall failure 637END(ia64_ret_from_syscall) 638 // fall through 639/* 640 * ia64_leave_syscall(): Same as ia64_leave_kernel, except that it doesn't 641 * need to switch to bank 0 and doesn't restore the scratch registers. 642 * To avoid leaking kernel bits, the scratch registers are set to 643 * the following known-to-be-safe values: 644 * 645 * r1: restored (global pointer) 646 * r2: cleared 647 * r3: 1 (when returning to user-level) 648 * r8-r11: restored (syscall return value(s)) 649 * r12: restored (user-level stack pointer) 650 * r13: restored (user-level thread pointer) 651 * r14: set to __kernel_syscall_via_epc 652 * r15: restored (syscall #) 653 * r16-r17: cleared 654 * r18: user-level b6 655 * r19: cleared 656 * r20: user-level ar.fpsr 657 * r21: user-level b0 658 * r22: cleared 659 * r23: user-level ar.bspstore 660 * r24: user-level ar.rnat 661 * r25: user-level ar.unat 662 * r26: user-level ar.pfs 663 * r27: user-level ar.rsc 664 * r28: user-level ip 665 * r29: user-level psr 666 * r30: user-level cfm 667 * r31: user-level pr 668 * f6-f11: cleared 669 * pr: restored (user-level pr) 670 * b0: restored (user-level rp) 671 * b6: restored 672 * b7: set to __kernel_syscall_via_epc 673 * ar.unat: restored (user-level ar.unat) 674 * ar.pfs: restored (user-level ar.pfs) 675 * ar.rsc: restored (user-level ar.rsc) 676 * ar.rnat: restored (user-level ar.rnat) 677 * ar.bspstore: restored (user-level ar.bspstore) 678 * ar.fpsr: restored (user-level ar.fpsr) 679 * ar.ccv: cleared 680 * ar.csd: cleared 681 * ar.ssd: cleared 682 */ 683ENTRY(ia64_leave_syscall) 684 PT_REGS_UNWIND_INFO(0) 685 /* 686 * work.need_resched etc. mustn't get changed by this CPU before it returns to 687 * user- or fsys-mode, hence we disable interrupts early on. 688 * 689 * p6 controls whether current_thread_info()->flags needs to be check for 690 * extra work. We always check for extra work when returning to user-level. 691 * With CONFIG_PREEMPT, we also check for extra work when the preempt_count 692 * is 0. After extra work processing has been completed, execution 693 * resumes at .work_processed_syscall with p6 set to 1 if the extra-work-check 694 * needs to be redone. 695 */ 696#ifdef CONFIG_PREEMPT 697 rsm psr.i // disable interrupts 698 cmp.eq pLvSys,p0=r0,r0 // pLvSys=1: leave from syscall 699(pKStk) adds r20=TI_PRE_COUNT+IA64_TASK_SIZE,r13 700 ;; 701 .pred.rel.mutex pUStk,pKStk 702(pKStk) ld4 r21=[r20] // r21 <- preempt_count 703(pUStk) mov r21=0 // r21 <- 0 704 ;; 705 cmp.eq p6,p0=r21,r0 // p6 <- pUStk || (preempt_count == 0) 706#else /* !CONFIG_PREEMPT */ 707(pUStk) rsm psr.i 708 cmp.eq pLvSys,p0=r0,r0 // pLvSys=1: leave from syscall 709(pUStk) cmp.eq.unc p6,p0=r0,r0 // p6 <- pUStk 710#endif 711.work_processed_syscall: 712 adds r2=PT(LOADRS)+16,r12 713 adds r3=PT(AR_BSPSTORE)+16,r12 714 adds r18=TI_FLAGS+IA64_TASK_SIZE,r13 715 ;; 716(p6) ld4 r31=[r18] // load current_thread_info()->flags 717 ld8 r19=[r2],PT(B6)-PT(LOADRS) // load ar.rsc value for "loadrs" 718 nop.i 0 719 ;; 720 mov r16=ar.bsp // M2 get existing backing store pointer 721 ld8 r18=[r2],PT(R9)-PT(B6) // load b6 722(p6) and r15=TIF_WORK_MASK,r31 // any work other than TIF_SYSCALL_TRACE? 723 ;; 724 ld8 r23=[r3],PT(R11)-PT(AR_BSPSTORE) // load ar.bspstore (may be garbage) 725(p6) cmp4.ne.unc p6,p0=r15, r0 // any special work pending? 726(p6) br.cond.spnt .work_pending_syscall 727 ;; 728 // start restoring the state saved on the kernel stack (struct pt_regs): 729 ld8 r9=[r2],PT(CR_IPSR)-PT(R9) 730 ld8 r11=[r3],PT(CR_IIP)-PT(R11) 731(pNonSys) break 0 // bug check: we shouldn't be here if pNonSys is TRUE! 732 ;; 733 invala // M0|1 invalidate ALAT 734 rsm psr.i | psr.ic // M2 turn off interrupts and interruption collection 735 cmp.eq p9,p0=r0,r0 // A set p9 to indicate that we should restore cr.ifs 736 737 ld8 r29=[r2],16 // M0|1 load cr.ipsr 738 ld8 r28=[r3],16 // M0|1 load cr.iip 739 mov r22=r0 // A clear r22 740 ;; 741 ld8 r30=[r2],16 // M0|1 load cr.ifs 742 ld8 r25=[r3],16 // M0|1 load ar.unat 743(pUStk) add r14=IA64_TASK_THREAD_ON_USTACK_OFFSET,r13 744 ;; 745 ld8 r26=[r2],PT(B0)-PT(AR_PFS) // M0|1 load ar.pfs 746(pKStk) mov r22=psr // M2 read PSR now that interrupts are disabled 747 nop 0 748 ;; 749 ld8 r21=[r2],PT(AR_RNAT)-PT(B0) // M0|1 load b0 750 ld8 r27=[r3],PT(PR)-PT(AR_RSC) // M0|1 load ar.rsc 751 mov f6=f0 // F clear f6 752 ;; 753 ld8 r24=[r2],PT(AR_FPSR)-PT(AR_RNAT) // M0|1 load ar.rnat (may be garbage) 754 ld8 r31=[r3],PT(R1)-PT(PR) // M0|1 load predicates 755 mov f7=f0 // F clear f7 756 ;; 757 ld8 r20=[r2],PT(R12)-PT(AR_FPSR) // M0|1 load ar.fpsr 758 ld8.fill r1=[r3],16 // M0|1 load r1 759(pUStk) mov r17=1 // A 760 ;; 761(pUStk) st1 [r14]=r17 // M2|3 762 ld8.fill r13=[r3],16 // M0|1 763 mov f8=f0 // F clear f8 764 ;; 765 ld8.fill r12=[r2] // M0|1 restore r12 (sp) 766 ld8.fill r15=[r3] // M0|1 restore r15 767 mov b6=r18 // I0 restore b6 768 769 addl r17=THIS_CPU(ia64_phys_stacked_size_p8),r0 // A 770 mov f9=f0 // F clear f9 771(pKStk) br.cond.dpnt.many skip_rbs_switch // B 772 773 srlz.d // M0 ensure interruption collection is off (for cover) 774 shr.u r18=r19,16 // I0|1 get byte size of existing "dirty" partition 775 cover // B add current frame into dirty partition & set cr.ifs 776 ;; 777(pUStk) ld4 r17=[r17] // M0|1 r17 = cpu_data->phys_stacked_size_p8 778 mov r19=ar.bsp // M2 get new backing store pointer 779 mov f10=f0 // F clear f10 780 781 nop.m 0 782 movl r14=__kernel_syscall_via_epc // X 783 ;; 784 mov.m ar.csd=r0 // M2 clear ar.csd 785 mov.m ar.ccv=r0 // M2 clear ar.ccv 786 mov b7=r14 // I0 clear b7 (hint with __kernel_syscall_via_epc) 787 788 mov.m ar.ssd=r0 // M2 clear ar.ssd 789 mov f11=f0 // F clear f11 790 br.cond.sptk.many rbs_switch // B 791END(ia64_leave_syscall) 792 793#ifdef CONFIG_IA32_SUPPORT 794GLOBAL_ENTRY(ia64_ret_from_ia32_execve) 795 PT_REGS_UNWIND_INFO(0) 796 adds r2=PT(R8)+16,sp // r2 = &pt_regs.r8 797 adds r3=PT(R10)+16,sp // r3 = &pt_regs.r10 798 ;; 799 .mem.offset 0,0 800 st8.spill [r2]=r8 // store return value in slot for r8 and set unat bit 801 .mem.offset 8,0 802 st8.spill [r3]=r0 // clear error indication in slot for r10 and set unat bit 803END(ia64_ret_from_ia32_execve) 804 // fall through 805#endif /* CONFIG_IA32_SUPPORT */ 806GLOBAL_ENTRY(ia64_leave_kernel) 807 PT_REGS_UNWIND_INFO(0) 808 /* 809 * work.need_resched etc. mustn't get changed by this CPU before it returns to 810 * user- or fsys-mode, hence we disable interrupts early on. 811 * 812 * p6 controls whether current_thread_info()->flags needs to be check for 813 * extra work. We always check for extra work when returning to user-level. 814 * With CONFIG_PREEMPT, we also check for extra work when the preempt_count 815 * is 0. After extra work processing has been completed, execution 816 * resumes at .work_processed_syscall with p6 set to 1 if the extra-work-check 817 * needs to be redone. 818 */ 819#ifdef CONFIG_PREEMPT 820 rsm psr.i // disable interrupts 821 cmp.eq p0,pLvSys=r0,r0 // pLvSys=0: leave from kernel 822(pKStk) adds r20=TI_PRE_COUNT+IA64_TASK_SIZE,r13 823 ;; 824 .pred.rel.mutex pUStk,pKStk 825(pKStk) ld4 r21=[r20] // r21 <- preempt_count 826(pUStk) mov r21=0 // r21 <- 0 827 ;; 828 cmp.eq p6,p0=r21,r0 // p6 <- pUStk || (preempt_count == 0) 829#else 830(pUStk) rsm psr.i 831 cmp.eq p0,pLvSys=r0,r0 // pLvSys=0: leave from kernel 832(pUStk) cmp.eq.unc p6,p0=r0,r0 // p6 <- pUStk 833#endif 834.work_processed_kernel: 835 adds r17=TI_FLAGS+IA64_TASK_SIZE,r13 836 ;; 837(p6) ld4 r31=[r17] // load current_thread_info()->flags 838 adds r21=PT(PR)+16,r12 839 ;; 840 841 lfetch [r21],PT(CR_IPSR)-PT(PR) 842 adds r2=PT(B6)+16,r12 843 adds r3=PT(R16)+16,r12 844 ;; 845 lfetch [r21] 846 ld8 r28=[r2],8 // load b6 847 adds r29=PT(R24)+16,r12 848 849 ld8.fill r16=[r3],PT(AR_CSD)-PT(R16) 850 adds r30=PT(AR_CCV)+16,r12 851(p6) and r19=TIF_WORK_MASK,r31 // any work other than TIF_SYSCALL_TRACE? 852 ;; 853 ld8.fill r24=[r29] 854 ld8 r15=[r30] // load ar.ccv 855(p6) cmp4.ne.unc p6,p0=r19, r0 // any special work pending? 856 ;; 857 ld8 r29=[r2],16 // load b7 858 ld8 r30=[r3],16 // load ar.csd 859(p6) br.cond.spnt .work_pending 860 ;; 861 ld8 r31=[r2],16 // load ar.ssd 862 ld8.fill r8=[r3],16 863 ;; 864 ld8.fill r9=[r2],16 865 ld8.fill r10=[r3],PT(R17)-PT(R10) 866 ;; 867 ld8.fill r11=[r2],PT(R18)-PT(R11) 868 ld8.fill r17=[r3],16 869 ;; 870 ld8.fill r18=[r2],16 871 ld8.fill r19=[r3],16 872 ;; 873 ld8.fill r20=[r2],16 874 ld8.fill r21=[r3],16 875 mov ar.csd=r30 876 mov ar.ssd=r31 877 ;; 878 rsm psr.i | psr.ic // initiate turning off of interrupt and interruption collection 879 invala // invalidate ALAT 880 ;; 881 ld8.fill r22=[r2],24 882 ld8.fill r23=[r3],24 883 mov b6=r28 884 ;; 885 ld8.fill r25=[r2],16 886 ld8.fill r26=[r3],16 887 mov b7=r29 888 ;; 889 ld8.fill r27=[r2],16 890 ld8.fill r28=[r3],16 891 ;; 892 ld8.fill r29=[r2],16 893 ld8.fill r30=[r3],24 894 ;; 895 ld8.fill r31=[r2],PT(F9)-PT(R31) 896 adds r3=PT(F10)-PT(F6),r3 897 ;; 898 ldf.fill f9=[r2],PT(F6)-PT(F9) 899 ldf.fill f10=[r3],PT(F8)-PT(F10) 900 ;; 901 ldf.fill f6=[r2],PT(F7)-PT(F6) 902 ;; 903 ldf.fill f7=[r2],PT(F11)-PT(F7) 904 ldf.fill f8=[r3],32 905 ;; 906 srlz.d // ensure that inter. collection is off (VHPT is don't care, since text is pinned) 907 mov ar.ccv=r15 908 ;; 909 ldf.fill f11=[r2] 910 bsw.0 // switch back to bank 0 (no stop bit required beforehand...) 911 ;; 912(pUStk) mov r18=IA64_KR(CURRENT)// M2 (12 cycle read latency) 913 adds r16=PT(CR_IPSR)+16,r12 914 adds r17=PT(CR_IIP)+16,r12 915 916(pKStk) mov r22=psr // M2 read PSR now that interrupts are disabled 917 nop.i 0 918 nop.i 0 919 ;; 920 ld8 r29=[r16],16 // load cr.ipsr 921 ld8 r28=[r17],16 // load cr.iip 922 ;; 923 ld8 r30=[r16],16 // load cr.ifs 924 ld8 r25=[r17],16 // load ar.unat 925 ;; 926 ld8 r26=[r16],16 // load ar.pfs 927 ld8 r27=[r17],16 // load ar.rsc 928 cmp.eq p9,p0=r0,r0 // set p9 to indicate that we should restore cr.ifs 929 ;; 930 ld8 r24=[r16],16 // load ar.rnat (may be garbage) 931 ld8 r23=[r17],16 // load ar.bspstore (may be garbage) 932 ;; 933 ld8 r31=[r16],16 // load predicates 934 ld8 r21=[r17],16 // load b0 935 ;; 936 ld8 r19=[r16],16 // load ar.rsc value for "loadrs" 937 ld8.fill r1=[r17],16 // load r1 938 ;; 939 ld8.fill r12=[r16],16 940 ld8.fill r13=[r17],16 941(pUStk) adds r18=IA64_TASK_THREAD_ON_USTACK_OFFSET,r18 942 ;; 943 ld8 r20=[r16],16 // ar.fpsr 944 ld8.fill r15=[r17],16 945 ;; 946 ld8.fill r14=[r16],16 947 ld8.fill r2=[r17] 948(pUStk) mov r17=1 949 ;; 950 ld8.fill r3=[r16] 951(pUStk) st1 [r18]=r17 // restore current->thread.on_ustack 952 shr.u r18=r19,16 // get byte size of existing "dirty" partition 953 ;; 954 mov r16=ar.bsp // get existing backing store pointer 955 addl r17=THIS_CPU(ia64_phys_stacked_size_p8),r0 956 ;; 957 ld4 r17=[r17] // r17 = cpu_data->phys_stacked_size_p8 958(pKStk) br.cond.dpnt skip_rbs_switch 959 960 /* 961 * Restore user backing store. 962 * 963 * NOTE: alloc, loadrs, and cover can't be predicated. 964 */ 965(pNonSys) br.cond.dpnt dont_preserve_current_frame 966 cover // add current frame into dirty partition and set cr.ifs 967 ;; 968 mov r19=ar.bsp // get new backing store pointer 969rbs_switch: 970 sub r16=r16,r18 // krbs = old bsp - size of dirty partition 971 cmp.ne p9,p0=r0,r0 // clear p9 to skip restore of cr.ifs 972 ;; 973 sub r19=r19,r16 // calculate total byte size of dirty partition 974 add r18=64,r18 // don't force in0-in7 into memory... 975 ;; 976 shl r19=r19,16 // shift size of dirty partition into loadrs position 977 ;; 978dont_preserve_current_frame: 979 /* 980 * To prevent leaking bits between the kernel and user-space, 981 * we must clear the stacked registers in the "invalid" partition here. 982 * Not pretty, but at least it's fast (3.34 registers/cycle on Itanium, 983 * 5 registers/cycle on McKinley). 984 */ 985# define pRecurse p6 986# define pReturn p7 987#ifdef CONFIG_ITANIUM 988# define Nregs 10 989#else 990# define Nregs 14 991#endif 992 alloc loc0=ar.pfs,2,Nregs-2,2,0 993 shr.u loc1=r18,9 // RNaTslots <= floor(dirtySize / (64*8)) 994 sub r17=r17,r18 // r17 = (physStackedSize + 8) - dirtySize 995 ;; 996 mov ar.rsc=r19 // load ar.rsc to be used for "loadrs" 997 shladd in0=loc1,3,r17 998 mov in1=0 999 ;; 1000 TEXT_ALIGN(32) 1001rse_clear_invalid: 1002#ifdef CONFIG_ITANIUM 1003 // cycle 0 1004 { .mii 1005 alloc loc0=ar.pfs,2,Nregs-2,2,0 1006 cmp.lt pRecurse,p0=Nregs*8,in0 // if more than Nregs regs left to clear, (re)curse 1007 add out0=-Nregs*8,in0 1008}{ .mfb 1009 add out1=1,in1 // increment recursion count 1010 nop.f 0 1011 nop.b 0 // can't do br.call here because of alloc (WAW on CFM) 1012 ;; 1013}{ .mfi // cycle 1 1014 mov loc1=0 1015 nop.f 0 1016 mov loc2=0 1017}{ .mib 1018 mov loc3=0 1019 mov loc4=0 1020(pRecurse) br.call.sptk.many b0=rse_clear_invalid 1021 1022}{ .mfi // cycle 2 1023 mov loc5=0 1024 nop.f 0 1025 cmp.ne pReturn,p0=r0,in1 // if recursion count != 0, we need to do a br.ret 1026}{ .mib 1027 mov loc6=0 1028 mov loc7=0 1029(pReturn) br.ret.sptk.many b0 1030} 1031#else /* !CONFIG_ITANIUM */ 1032 alloc loc0=ar.pfs,2,Nregs-2,2,0 1033 cmp.lt pRecurse,p0=Nregs*8,in0 // if more than Nregs regs left to clear, (re)curse 1034 add out0=-Nregs*8,in0 1035 add out1=1,in1 // increment recursion count 1036 mov loc1=0 1037 mov loc2=0 1038 ;; 1039 mov loc3=0 1040 mov loc4=0 1041 mov loc5=0 1042 mov loc6=0 1043 mov loc7=0 1044(pRecurse) br.call.dptk.few b0=rse_clear_invalid 1045 ;; 1046 mov loc8=0 1047 mov loc9=0 1048 cmp.ne pReturn,p0=r0,in1 // if recursion count != 0, we need to do a br.ret 1049 mov loc10=0 1050 mov loc11=0 1051(pReturn) br.ret.dptk.many b0 1052#endif /* !CONFIG_ITANIUM */ 1053# undef pRecurse 1054# undef pReturn 1055 ;; 1056 alloc r17=ar.pfs,0,0,0,0 // drop current register frame 1057 ;; 1058 loadrs 1059 ;; 1060skip_rbs_switch: 1061 mov ar.unat=r25 // M2 1062(pKStk) extr.u r22=r22,21,1 // I0 extract current value of psr.pp from r22 1063(pLvSys)mov r19=r0 // A clear r19 for leave_syscall, no-op otherwise 1064 ;; 1065(pUStk) mov ar.bspstore=r23 // M2 1066(pKStk) dep r29=r22,r29,21,1 // I0 update ipsr.pp with psr.pp 1067(pLvSys)mov r16=r0 // A clear r16 for leave_syscall, no-op otherwise 1068 ;; 1069 mov cr.ipsr=r29 // M2 1070 mov ar.pfs=r26 // I0 1071(pLvSys)mov r17=r0 // A clear r17 for leave_syscall, no-op otherwise 1072 1073(p9) mov cr.ifs=r30 // M2 1074 mov b0=r21 // I0 1075(pLvSys)mov r18=r0 // A clear r18 for leave_syscall, no-op otherwise 1076 1077 mov ar.fpsr=r20 // M2 1078 mov cr.iip=r28 // M2 1079 nop 0 1080 ;; 1081(pUStk) mov ar.rnat=r24 // M2 must happen with RSE in lazy mode 1082 nop 0 1083(pLvSys)mov r2=r0 1084 1085 mov ar.rsc=r27 // M2 1086 mov pr=r31,-1 // I0 1087 rfi // B 1088 1089 /* 1090 * On entry: 1091 * r20 = ¤t->thread_info->pre_count (if CONFIG_PREEMPT) 1092 * r31 = current->thread_info->flags 1093 * On exit: 1094 * p6 = TRUE if work-pending-check needs to be redone 1095 */ 1096.work_pending_syscall: 1097 add r2=-8,r2 1098 add r3=-8,r3 1099 ;; 1100 st8 [r2]=r8 1101 st8 [r3]=r10 1102.work_pending: 1103 tbit.nz p6,p0=r31,TIF_SIGDELAYED // signal delayed from MCA/INIT/NMI/PMI context? 1104(p6) br.cond.sptk.few .sigdelayed 1105 ;; 1106 tbit.z p6,p0=r31,TIF_NEED_RESCHED // current_thread_info()->need_resched==0? 1107(p6) br.cond.sptk.few .notify 1108#ifdef CONFIG_PREEMPT 1109(pKStk) dep r21=-1,r0,PREEMPT_ACTIVE_BIT,1 1110 ;; 1111(pKStk) st4 [r20]=r21 1112 ssm psr.i // enable interrupts 1113#endif 1114 br.call.spnt.many rp=schedule 1115.ret9: cmp.eq p6,p0=r0,r0 // p6 <- 1 1116 rsm psr.i // disable interrupts 1117 ;; 1118#ifdef CONFIG_PREEMPT 1119(pKStk) adds r20=TI_PRE_COUNT+IA64_TASK_SIZE,r13 1120 ;; 1121(pKStk) st4 [r20]=r0 // preempt_count() <- 0 1122#endif 1123(pLvSys)br.cond.sptk.few .work_pending_syscall_end 1124 br.cond.sptk.many .work_processed_kernel // re-check 1125 1126.notify: 1127(pUStk) br.call.spnt.many rp=notify_resume_user 1128.ret10: cmp.ne p6,p0=r0,r0 // p6 <- 0 1129(pLvSys)br.cond.sptk.few .work_pending_syscall_end 1130 br.cond.sptk.many .work_processed_kernel // don't re-check 1131 1132// There is a delayed signal that was detected in MCA/INIT/NMI/PMI context where 1133// it could not be delivered. Deliver it now. The signal might be for us and 1134// may set TIF_SIGPENDING, so redrive ia64_leave_* after processing the delayed 1135// signal. 1136 1137.sigdelayed: 1138 br.call.sptk.many rp=do_sigdelayed 1139 cmp.eq p6,p0=r0,r0 // p6 <- 1, always re-check 1140(pLvSys)br.cond.sptk.few .work_pending_syscall_end 1141 br.cond.sptk.many .work_processed_kernel // re-check 1142 1143.work_pending_syscall_end: 1144 adds r2=PT(R8)+16,r12 1145 adds r3=PT(R10)+16,r12 1146 ;; 1147 ld8 r8=[r2] 1148 ld8 r10=[r3] 1149 br.cond.sptk.many .work_processed_syscall // re-check 1150 1151END(ia64_leave_kernel) 1152 1153ENTRY(handle_syscall_error) 1154 /* 1155 * Some system calls (e.g., ptrace, mmap) can return arbitrary values which could 1156 * lead us to mistake a negative return value as a failed syscall. Those syscall 1157 * must deposit a non-zero value in pt_regs.r8 to indicate an error. If 1158 * pt_regs.r8 is zero, we assume that the call completed successfully. 1159 */ 1160 PT_REGS_UNWIND_INFO(0) 1161 ld8 r3=[r2] // load pt_regs.r8 1162 ;; 1163 cmp.eq p6,p7=r3,r0 // is pt_regs.r8==0? 1164 ;; 1165(p7) mov r10=-1 1166(p7) sub r8=0,r8 // negate return value to get errno 1167 br.cond.sptk ia64_leave_syscall 1168END(handle_syscall_error) 1169 1170 /* 1171 * Invoke schedule_tail(task) while preserving in0-in7, which may be needed 1172 * in case a system call gets restarted. 1173 */ 1174GLOBAL_ENTRY(ia64_invoke_schedule_tail) 1175 .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8) 1176 alloc loc1=ar.pfs,8,2,1,0 1177 mov loc0=rp 1178 mov out0=r8 // Address of previous task 1179 ;; 1180 br.call.sptk.many rp=schedule_tail 1181.ret11: mov ar.pfs=loc1 1182 mov rp=loc0 1183 br.ret.sptk.many rp 1184END(ia64_invoke_schedule_tail) 1185 1186 /* 1187 * Setup stack and call do_notify_resume_user(). Note that pSys and pNonSys need to 1188 * be set up by the caller. We declare 8 input registers so the system call 1189 * args get preserved, in case we need to restart a system call. 1190 */ 1191ENTRY(notify_resume_user) 1192 .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8) 1193 alloc loc1=ar.pfs,8,2,3,0 // preserve all eight input regs in case of syscall restart! 1194 mov r9=ar.unat 1195 mov loc0=rp // save return address 1196 mov out0=0 // there is no "oldset" 1197 adds out1=8,sp // out1=&sigscratch->ar_pfs 1198(pSys) mov out2=1 // out2==1 => we're in a syscall 1199 ;; 1200(pNonSys) mov out2=0 // out2==0 => not a syscall 1201 .fframe 16 1202 .spillsp ar.unat, 16 1203 st8 [sp]=r9,-16 // allocate space for ar.unat and save it 1204 st8 [out1]=loc1,-8 // save ar.pfs, out1=&sigscratch 1205 .body 1206 br.call.sptk.many rp=do_notify_resume_user 1207.ret15: .restore sp 1208 adds sp=16,sp // pop scratch stack space 1209 ;; 1210 ld8 r9=[sp] // load new unat from sigscratch->scratch_unat 1211 mov rp=loc0 1212 ;; 1213 mov ar.unat=r9 1214 mov ar.pfs=loc1 1215 br.ret.sptk.many rp 1216END(notify_resume_user) 1217 1218GLOBAL_ENTRY(sys_rt_sigsuspend) 1219 .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8) 1220 alloc loc1=ar.pfs,8,2,3,0 // preserve all eight input regs in case of syscall restart! 1221 mov r9=ar.unat 1222 mov loc0=rp // save return address 1223 mov out0=in0 // mask 1224 mov out1=in1 // sigsetsize 1225 adds out2=8,sp // out2=&sigscratch->ar_pfs 1226 ;; 1227 .fframe 16 1228 .spillsp ar.unat, 16 1229 st8 [sp]=r9,-16 // allocate space for ar.unat and save it 1230 st8 [out2]=loc1,-8 // save ar.pfs, out2=&sigscratch 1231 .body 1232 br.call.sptk.many rp=ia64_rt_sigsuspend 1233.ret17: .restore sp 1234 adds sp=16,sp // pop scratch stack space 1235 ;; 1236 ld8 r9=[sp] // load new unat from sw->caller_unat 1237 mov rp=loc0 1238 ;; 1239 mov ar.unat=r9 1240 mov ar.pfs=loc1 1241 br.ret.sptk.many rp 1242END(sys_rt_sigsuspend) 1243 1244ENTRY(sys_rt_sigreturn) 1245 PT_REGS_UNWIND_INFO(0) 1246 /* 1247 * Allocate 8 input registers since ptrace() may clobber them 1248 */ 1249 alloc r2=ar.pfs,8,0,1,0 1250 .prologue 1251 PT_REGS_SAVES(16) 1252 adds sp=-16,sp 1253 .body 1254 cmp.eq pNonSys,pSys=r0,r0 // sigreturn isn't a normal syscall... 1255 ;; 1256 /* 1257 * leave_kernel() restores f6-f11 from pt_regs, but since the streamlined 1258 * syscall-entry path does not save them we save them here instead. Note: we 1259 * don't need to save any other registers that are not saved by the stream-lined 1260 * syscall path, because restore_sigcontext() restores them. 1261 */ 1262 adds r16=PT(F6)+32,sp 1263 adds r17=PT(F7)+32,sp 1264 ;; 1265 stf.spill [r16]=f6,32 1266 stf.spill [r17]=f7,32 1267 ;; 1268 stf.spill [r16]=f8,32 1269 stf.spill [r17]=f9,32 1270 ;; 1271 stf.spill [r16]=f10 1272 stf.spill [r17]=f11 1273 adds out0=16,sp // out0 = &sigscratch 1274 br.call.sptk.many rp=ia64_rt_sigreturn 1275.ret19: .restore sp,0 1276 adds sp=16,sp 1277 ;; 1278 ld8 r9=[sp] // load new ar.unat 1279 mov.sptk b7=r8,ia64_leave_kernel 1280 ;; 1281 mov ar.unat=r9 1282 br.many b7 1283END(sys_rt_sigreturn) 1284 1285GLOBAL_ENTRY(ia64_prepare_handle_unaligned) 1286 .prologue 1287 /* 1288 * r16 = fake ar.pfs, we simply need to make sure privilege is still 0 1289 */ 1290 mov r16=r0 1291 DO_SAVE_SWITCH_STACK 1292 br.call.sptk.many rp=ia64_handle_unaligned // stack frame setup in ivt 1293.ret21: .body 1294 DO_LOAD_SWITCH_STACK 1295 br.cond.sptk.many rp // goes to ia64_leave_kernel 1296END(ia64_prepare_handle_unaligned) 1297 1298 // 1299 // unw_init_running(void (*callback)(info, arg), void *arg) 1300 // 1301# define EXTRA_FRAME_SIZE ((UNW_FRAME_INFO_SIZE+15)&~15) 1302 1303GLOBAL_ENTRY(unw_init_running) 1304 .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(2) 1305 alloc loc1=ar.pfs,2,3,3,0 1306 ;; 1307 ld8 loc2=[in0],8 1308 mov loc0=rp 1309 mov r16=loc1 1310 DO_SAVE_SWITCH_STACK 1311 .body 1312 1313 .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(2) 1314 .fframe IA64_SWITCH_STACK_SIZE+EXTRA_FRAME_SIZE 1315 SWITCH_STACK_SAVES(EXTRA_FRAME_SIZE) 1316 adds sp=-EXTRA_FRAME_SIZE,sp 1317 .body 1318 ;; 1319 adds out0=16,sp // &info 1320 mov out1=r13 // current 1321 adds out2=16+EXTRA_FRAME_SIZE,sp // &switch_stack 1322 br.call.sptk.many rp=unw_init_frame_info 13231: adds out0=16,sp // &info 1324 mov b6=loc2 1325 mov loc2=gp // save gp across indirect function call 1326 ;; 1327 ld8 gp=[in0] 1328 mov out1=in1 // arg 1329 br.call.sptk.many rp=b6 // invoke the callback function 13301: mov gp=loc2 // restore gp 1331 1332 // For now, we don't allow changing registers from within 1333 // unw_init_running; if we ever want to allow that, we'd 1334 // have to do a load_switch_stack here: 1335 .restore sp 1336 adds sp=IA64_SWITCH_STACK_SIZE+EXTRA_FRAME_SIZE,sp 1337 1338 mov ar.pfs=loc1 1339 mov rp=loc0 1340 br.ret.sptk.many rp 1341END(unw_init_running) 1342 1343 .rodata 1344 .align 8 1345 .globl sys_call_table 1346sys_call_table: 1347 data8 sys_ni_syscall // This must be sys_ni_syscall! See ivt.S. 1348 data8 sys_exit // 1025 1349 data8 sys_read 1350 data8 sys_write 1351 data8 sys_open 1352 data8 sys_close 1353 data8 sys_creat // 1030 1354 data8 sys_link 1355 data8 sys_unlink 1356 data8 ia64_execve 1357 data8 sys_chdir 1358 data8 sys_fchdir // 1035 1359 data8 sys_utimes 1360 data8 sys_mknod 1361 data8 sys_chmod 1362 data8 sys_chown 1363 data8 sys_lseek // 1040 1364 data8 sys_getpid 1365 data8 sys_getppid 1366 data8 sys_mount 1367 data8 sys_umount 1368 data8 sys_setuid // 1045 1369 data8 sys_getuid 1370 data8 sys_geteuid 1371 data8 sys_ptrace 1372 data8 sys_access 1373 data8 sys_sync // 1050 1374 data8 sys_fsync 1375 data8 sys_fdatasync 1376 data8 sys_kill 1377 data8 sys_rename 1378 data8 sys_mkdir // 1055 1379 data8 sys_rmdir 1380 data8 sys_dup 1381 data8 sys_pipe 1382 data8 sys_times 1383 data8 ia64_brk // 1060 1384 data8 sys_setgid 1385 data8 sys_getgid 1386 data8 sys_getegid 1387 data8 sys_acct 1388 data8 sys_ioctl // 1065 1389 data8 sys_fcntl 1390 data8 sys_umask 1391 data8 sys_chroot 1392 data8 sys_ustat 1393 data8 sys_dup2 // 1070 1394 data8 sys_setreuid 1395 data8 sys_setregid 1396 data8 sys_getresuid 1397 data8 sys_setresuid 1398 data8 sys_getresgid // 1075 1399 data8 sys_setresgid 1400 data8 sys_getgroups 1401 data8 sys_setgroups 1402 data8 sys_getpgid 1403 data8 sys_setpgid // 1080 1404 data8 sys_setsid 1405 data8 sys_getsid 1406 data8 sys_sethostname 1407 data8 sys_setrlimit 1408 data8 sys_getrlimit // 1085 1409 data8 sys_getrusage 1410 data8 sys_gettimeofday 1411 data8 sys_settimeofday 1412 data8 sys_select 1413 data8 sys_poll // 1090 1414 data8 sys_symlink 1415 data8 sys_readlink 1416 data8 sys_uselib 1417 data8 sys_swapon 1418 data8 sys_swapoff // 1095 1419 data8 sys_reboot 1420 data8 sys_truncate 1421 data8 sys_ftruncate 1422 data8 sys_fchmod 1423 data8 sys_fchown // 1100 1424 data8 ia64_getpriority 1425 data8 sys_setpriority 1426 data8 sys_statfs 1427 data8 sys_fstatfs 1428 data8 sys_gettid // 1105 1429 data8 sys_semget 1430 data8 sys_semop 1431 data8 sys_semctl 1432 data8 sys_msgget 1433 data8 sys_msgsnd // 1110 1434 data8 sys_msgrcv 1435 data8 sys_msgctl 1436 data8 sys_shmget 1437 data8 sys_shmat 1438 data8 sys_shmdt // 1115 1439 data8 sys_shmctl 1440 data8 sys_syslog 1441 data8 sys_setitimer 1442 data8 sys_getitimer 1443 data8 sys_ni_syscall // 1120 /* was: ia64_oldstat */ 1444 data8 sys_ni_syscall /* was: ia64_oldlstat */ 1445 data8 sys_ni_syscall /* was: ia64_oldfstat */ 1446 data8 sys_vhangup 1447 data8 sys_lchown 1448 data8 sys_remap_file_pages // 1125 1449 data8 sys_wait4 1450 data8 sys_sysinfo 1451 data8 sys_clone 1452 data8 sys_setdomainname 1453 data8 sys_newuname // 1130 1454 data8 sys_adjtimex 1455 data8 sys_ni_syscall /* was: ia64_create_module */ 1456 data8 sys_init_module 1457 data8 sys_delete_module 1458 data8 sys_ni_syscall // 1135 /* was: sys_get_kernel_syms */ 1459 data8 sys_ni_syscall /* was: sys_query_module */ 1460 data8 sys_quotactl 1461 data8 sys_bdflush 1462 data8 sys_sysfs 1463 data8 sys_personality // 1140 1464 data8 sys_ni_syscall // sys_afs_syscall 1465 data8 sys_setfsuid 1466 data8 sys_setfsgid 1467 data8 sys_getdents 1468 data8 sys_flock // 1145 1469 data8 sys_readv 1470 data8 sys_writev 1471 data8 sys_pread64 1472 data8 sys_pwrite64 1473 data8 sys_sysctl // 1150 1474 data8 sys_mmap 1475 data8 sys_munmap 1476 data8 sys_mlock 1477 data8 sys_mlockall 1478 data8 sys_mprotect // 1155 1479 data8 ia64_mremap 1480 data8 sys_msync 1481 data8 sys_munlock 1482 data8 sys_munlockall 1483 data8 sys_sched_getparam // 1160 1484 data8 sys_sched_setparam 1485 data8 sys_sched_getscheduler 1486 data8 sys_sched_setscheduler 1487 data8 sys_sched_yield 1488 data8 sys_sched_get_priority_max // 1165 1489 data8 sys_sched_get_priority_min 1490 data8 sys_sched_rr_get_interval 1491 data8 sys_nanosleep 1492 data8 sys_nfsservctl 1493 data8 sys_prctl // 1170 1494 data8 sys_getpagesize 1495 data8 sys_mmap2 1496 data8 sys_pciconfig_read 1497 data8 sys_pciconfig_write 1498 data8 sys_perfmonctl // 1175 1499 data8 sys_sigaltstack 1500 data8 sys_rt_sigaction 1501 data8 sys_rt_sigpending 1502 data8 sys_rt_sigprocmask 1503 data8 sys_rt_sigqueueinfo // 1180 1504 data8 sys_rt_sigreturn 1505 data8 sys_rt_sigsuspend 1506 data8 sys_rt_sigtimedwait 1507 data8 sys_getcwd 1508 data8 sys_capget // 1185 1509 data8 sys_capset 1510 data8 sys_sendfile64 1511 data8 sys_ni_syscall // sys_getpmsg (STREAMS) 1512 data8 sys_ni_syscall // sys_putpmsg (STREAMS) 1513 data8 sys_socket // 1190 1514 data8 sys_bind 1515 data8 sys_connect 1516 data8 sys_listen 1517 data8 sys_accept 1518 data8 sys_getsockname // 1195 1519 data8 sys_getpeername 1520 data8 sys_socketpair 1521 data8 sys_send 1522 data8 sys_sendto 1523 data8 sys_recv // 1200 1524 data8 sys_recvfrom 1525 data8 sys_shutdown 1526 data8 sys_setsockopt 1527 data8 sys_getsockopt 1528 data8 sys_sendmsg // 1205 1529 data8 sys_recvmsg 1530 data8 sys_pivot_root 1531 data8 sys_mincore 1532 data8 sys_madvise 1533 data8 sys_newstat // 1210 1534 data8 sys_newlstat 1535 data8 sys_newfstat 1536 data8 sys_clone2 1537 data8 sys_getdents64 1538 data8 sys_getunwind // 1215 1539 data8 sys_readahead 1540 data8 sys_setxattr 1541 data8 sys_lsetxattr 1542 data8 sys_fsetxattr 1543 data8 sys_getxattr // 1220 1544 data8 sys_lgetxattr 1545 data8 sys_fgetxattr 1546 data8 sys_listxattr 1547 data8 sys_llistxattr 1548 data8 sys_flistxattr // 1225 1549 data8 sys_removexattr 1550 data8 sys_lremovexattr 1551 data8 sys_fremovexattr 1552 data8 sys_tkill 1553 data8 sys_futex // 1230 1554 data8 sys_sched_setaffinity 1555 data8 sys_sched_getaffinity 1556 data8 sys_set_tid_address 1557 data8 sys_fadvise64_64 1558 data8 sys_tgkill // 1235 1559 data8 sys_exit_group 1560 data8 sys_lookup_dcookie 1561 data8 sys_io_setup 1562 data8 sys_io_destroy 1563 data8 sys_io_getevents // 1240 1564 data8 sys_io_submit 1565 data8 sys_io_cancel 1566 data8 sys_epoll_create 1567 data8 sys_epoll_ctl 1568 data8 sys_epoll_wait // 1245 1569 data8 sys_restart_syscall 1570 data8 sys_semtimedop 1571 data8 sys_timer_create 1572 data8 sys_timer_settime 1573 data8 sys_timer_gettime // 1250 1574 data8 sys_timer_getoverrun 1575 data8 sys_timer_delete 1576 data8 sys_clock_settime 1577 data8 sys_clock_gettime 1578 data8 sys_clock_getres // 1255 1579 data8 sys_clock_nanosleep 1580 data8 sys_fstatfs64 1581 data8 sys_statfs64 1582 data8 sys_mbind 1583 data8 sys_get_mempolicy // 1260 1584 data8 sys_set_mempolicy 1585 data8 sys_mq_open 1586 data8 sys_mq_unlink 1587 data8 sys_mq_timedsend 1588 data8 sys_mq_timedreceive // 1265 1589 data8 sys_mq_notify 1590 data8 sys_mq_getsetattr 1591 data8 sys_ni_syscall // reserved for kexec_load 1592 data8 sys_ni_syscall // reserved for vserver 1593 data8 sys_waitid // 1270 1594 data8 sys_add_key 1595 data8 sys_request_key 1596 data8 sys_keyctl 1597 data8 sys_ioprio_set 1598 data8 sys_ioprio_get // 1275 1599 data8 sys_ni_syscall 1600 data8 sys_inotify_init 1601 data8 sys_inotify_add_watch 1602 data8 sys_inotify_rm_watch 1603 data8 sys_migrate_pages // 1280 1604 1605 .org sys_call_table + 8*NR_syscalls // guard against failures to increase NR_syscalls 1606