1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Emulation of the "brl" instruction for IA64 processors that 4 * don't support it in hardware. 5 * Author: Stephan Zeisset, Intel Corp. <Stephan.Zeisset@intel.com> 6 * 7 * 02/22/02 D. Mosberger Clear si_flgs, si_isr, and si_imm to avoid 8 * leaking kernel bits. 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/sched/signal.h> 13 #include <linux/uaccess.h> 14 #include <asm/processor.h> 15 16 extern char ia64_set_b1, ia64_set_b2, ia64_set_b3, ia64_set_b4, ia64_set_b5; 17 18 struct illegal_op_return { 19 unsigned long fkt, arg1, arg2, arg3; 20 }; 21 22 /* 23 * The unimplemented bits of a virtual address must be set 24 * to the value of the most significant implemented bit. 25 * unimpl_va_mask includes all unimplemented bits and 26 * the most significant implemented bit, so the result 27 * of an and operation with the mask must be all 0's 28 * or all 1's for the address to be valid. 29 */ 30 #define unimplemented_virtual_address(va) ( \ 31 ((va) & local_cpu_data->unimpl_va_mask) != 0 && \ 32 ((va) & local_cpu_data->unimpl_va_mask) != local_cpu_data->unimpl_va_mask \ 33 ) 34 35 /* 36 * The unimplemented bits of a physical address must be 0. 37 * unimpl_pa_mask includes all unimplemented bits, so the result 38 * of an and operation with the mask must be all 0's for the 39 * address to be valid. 40 */ 41 #define unimplemented_physical_address(pa) ( \ 42 ((pa) & local_cpu_data->unimpl_pa_mask) != 0 \ 43 ) 44 45 /* 46 * Handle an illegal operation fault that was caused by an 47 * unimplemented "brl" instruction. 48 * If we are not successful (e.g because the illegal operation 49 * wasn't caused by a "brl" after all), we return -1. 50 * If we are successful, we return either 0 or the address 51 * of a "fixup" function for manipulating preserved register 52 * state. 53 */ 54 55 struct illegal_op_return 56 ia64_emulate_brl (struct pt_regs *regs, unsigned long ar_ec) 57 { 58 unsigned long bundle[2]; 59 unsigned long opcode, btype, qp, offset, cpl; 60 unsigned long next_ip; 61 struct siginfo siginfo; 62 struct illegal_op_return rv; 63 long tmp_taken, unimplemented_address; 64 65 clear_siginfo(&siginfo); 66 rv.fkt = (unsigned long) -1; 67 68 /* 69 * Decode the instruction bundle. 70 */ 71 72 if (copy_from_user(bundle, (void *) (regs->cr_iip), sizeof(bundle))) 73 return rv; 74 75 next_ip = (unsigned long) regs->cr_iip + 16; 76 77 /* "brl" must be in slot 2. */ 78 if (ia64_psr(regs)->ri != 1) return rv; 79 80 /* Must be "mlx" template */ 81 if ((bundle[0] & 0x1e) != 0x4) return rv; 82 83 opcode = (bundle[1] >> 60); 84 btype = ((bundle[1] >> 29) & 0x7); 85 qp = ((bundle[1] >> 23) & 0x3f); 86 offset = ((bundle[1] & 0x0800000000000000L) << 4) 87 | ((bundle[1] & 0x00fffff000000000L) >> 32) 88 | ((bundle[1] & 0x00000000007fffffL) << 40) 89 | ((bundle[0] & 0xffff000000000000L) >> 24); 90 91 tmp_taken = regs->pr & (1L << qp); 92 93 switch(opcode) { 94 95 case 0xC: 96 /* 97 * Long Branch. 98 */ 99 if (btype != 0) return rv; 100 rv.fkt = 0; 101 if (!(tmp_taken)) { 102 /* 103 * Qualifying predicate is 0. 104 * Skip instruction. 105 */ 106 regs->cr_iip = next_ip; 107 ia64_psr(regs)->ri = 0; 108 return rv; 109 } 110 break; 111 112 case 0xD: 113 /* 114 * Long Call. 115 */ 116 rv.fkt = 0; 117 if (!(tmp_taken)) { 118 /* 119 * Qualifying predicate is 0. 120 * Skip instruction. 121 */ 122 regs->cr_iip = next_ip; 123 ia64_psr(regs)->ri = 0; 124 return rv; 125 } 126 127 /* 128 * BR[btype] = IP+16 129 */ 130 switch(btype) { 131 case 0: 132 regs->b0 = next_ip; 133 break; 134 case 1: 135 rv.fkt = (unsigned long) &ia64_set_b1; 136 break; 137 case 2: 138 rv.fkt = (unsigned long) &ia64_set_b2; 139 break; 140 case 3: 141 rv.fkt = (unsigned long) &ia64_set_b3; 142 break; 143 case 4: 144 rv.fkt = (unsigned long) &ia64_set_b4; 145 break; 146 case 5: 147 rv.fkt = (unsigned long) &ia64_set_b5; 148 break; 149 case 6: 150 regs->b6 = next_ip; 151 break; 152 case 7: 153 regs->b7 = next_ip; 154 break; 155 } 156 rv.arg1 = next_ip; 157 158 /* 159 * AR[PFS].pfm = CFM 160 * AR[PFS].pec = AR[EC] 161 * AR[PFS].ppl = PSR.cpl 162 */ 163 cpl = ia64_psr(regs)->cpl; 164 regs->ar_pfs = ((regs->cr_ifs & 0x3fffffffff) 165 | (ar_ec << 52) | (cpl << 62)); 166 167 /* 168 * CFM.sof -= CFM.sol 169 * CFM.sol = 0 170 * CFM.sor = 0 171 * CFM.rrb.gr = 0 172 * CFM.rrb.fr = 0 173 * CFM.rrb.pr = 0 174 */ 175 regs->cr_ifs = ((regs->cr_ifs & 0xffffffc00000007f) 176 - ((regs->cr_ifs >> 7) & 0x7f)); 177 178 break; 179 180 default: 181 /* 182 * Unknown opcode. 183 */ 184 return rv; 185 186 } 187 188 regs->cr_iip += offset; 189 ia64_psr(regs)->ri = 0; 190 191 if (ia64_psr(regs)->it == 0) 192 unimplemented_address = unimplemented_physical_address(regs->cr_iip); 193 else 194 unimplemented_address = unimplemented_virtual_address(regs->cr_iip); 195 196 if (unimplemented_address) { 197 /* 198 * The target address contains unimplemented bits. 199 */ 200 printk(KERN_DEBUG "Woah! Unimplemented Instruction Address Trap!\n"); 201 siginfo.si_signo = SIGILL; 202 siginfo.si_errno = 0; 203 siginfo.si_flags = 0; 204 siginfo.si_isr = 0; 205 siginfo.si_imm = 0; 206 siginfo.si_code = ILL_BADIADDR; 207 force_sig_info(SIGILL, &siginfo, current); 208 } else if (ia64_psr(regs)->tb) { 209 /* 210 * Branch Tracing is enabled. 211 * Force a taken branch signal. 212 */ 213 siginfo.si_signo = SIGTRAP; 214 siginfo.si_errno = 0; 215 siginfo.si_code = TRAP_BRANCH; 216 siginfo.si_flags = 0; 217 siginfo.si_isr = 0; 218 siginfo.si_addr = 0; 219 siginfo.si_imm = 0; 220 force_sig_info(SIGTRAP, &siginfo, current); 221 } else if (ia64_psr(regs)->ss) { 222 /* 223 * Single Step is enabled. 224 * Force a trace signal. 225 */ 226 siginfo.si_signo = SIGTRAP; 227 siginfo.si_errno = 0; 228 siginfo.si_code = TRAP_TRACE; 229 siginfo.si_flags = 0; 230 siginfo.si_isr = 0; 231 siginfo.si_addr = 0; 232 siginfo.si_imm = 0; 233 force_sig_info(SIGTRAP, &siginfo, current); 234 } 235 return rv; 236 } 237