xref: /openbmc/linux/arch/ia64/include/asm/spinlock.h (revision 95e9fd10) 
1 #ifndef _ASM_IA64_SPINLOCK_H
2 #define _ASM_IA64_SPINLOCK_H
3 
4 /*
5  * Copyright (C) 1998-2003 Hewlett-Packard Co
6  *	David Mosberger-Tang <davidm@hpl.hp.com>
7  * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
8  *
9  * This file is used for SMP configurations only.
10  */
11 
12 #include <linux/compiler.h>
13 #include <linux/kernel.h>
14 #include <linux/bitops.h>
15 
16 #include <linux/atomic.h>
17 #include <asm/intrinsics.h>
18 
19 #define arch_spin_lock_init(x)			((x)->lock = 0)
20 
21 /*
22  * Ticket locks are conceptually two parts, one indicating the current head of
23  * the queue, and the other indicating the current tail. The lock is acquired
24  * by atomically noting the tail and incrementing it by one (thus adding
25  * ourself to the queue and noting our position), then waiting until the head
26  * becomes equal to the the initial value of the tail.
27  * The pad bits in the middle are used to prevent the next_ticket number
28  * overflowing into the now_serving number.
29  *
30  *   31             17  16    15  14                    0
31  *  +----------------------------------------------------+
32  *  |  now_serving     | padding |   next_ticket         |
33  *  +----------------------------------------------------+
34  */
35 
36 #define TICKET_SHIFT	17
37 #define TICKET_BITS	15
38 #define	TICKET_MASK	((1 << TICKET_BITS) - 1)
39 
40 static __always_inline void __ticket_spin_lock(arch_spinlock_t *lock)
41 {
42 	int	*p = (int *)&lock->lock, ticket, serve;
43 
44 	ticket = ia64_fetchadd(1, p, acq);
45 
46 	if (!(((ticket >> TICKET_SHIFT) ^ ticket) & TICKET_MASK))
47 		return;
48 
49 	ia64_invala();
50 
51 	for (;;) {
52 		asm volatile ("ld4.c.nc %0=[%1]" : "=r"(serve) : "r"(p) : "memory");
53 
54 		if (!(((serve >> TICKET_SHIFT) ^ ticket) & TICKET_MASK))
55 			return;
56 		cpu_relax();
57 	}
58 }
59 
60 static __always_inline int __ticket_spin_trylock(arch_spinlock_t *lock)
61 {
62 	int tmp = ACCESS_ONCE(lock->lock);
63 
64 	if (!(((tmp >> TICKET_SHIFT) ^ tmp) & TICKET_MASK))
65 		return ia64_cmpxchg(acq, &lock->lock, tmp, tmp + 1, sizeof (tmp)) == tmp;
66 	return 0;
67 }
68 
69 static __always_inline void __ticket_spin_unlock(arch_spinlock_t *lock)
70 {
71 	unsigned short	*p = (unsigned short *)&lock->lock + 1, tmp;
72 
73 	asm volatile ("ld2.bias %0=[%1]" : "=r"(tmp) : "r"(p));
74 	ACCESS_ONCE(*p) = (tmp + 2) & ~1;
75 }
76 
77 static __always_inline void __ticket_spin_unlock_wait(arch_spinlock_t *lock)
78 {
79 	int	*p = (int *)&lock->lock, ticket;
80 
81 	ia64_invala();
82 
83 	for (;;) {
84 		asm volatile ("ld4.c.nc %0=[%1]" : "=r"(ticket) : "r"(p) : "memory");
85 		if (!(((ticket >> TICKET_SHIFT) ^ ticket) & TICKET_MASK))
86 			return;
87 		cpu_relax();
88 	}
89 }
90 
91 static inline int __ticket_spin_is_locked(arch_spinlock_t *lock)
92 {
93 	long tmp = ACCESS_ONCE(lock->lock);
94 
95 	return !!(((tmp >> TICKET_SHIFT) ^ tmp) & TICKET_MASK);
96 }
97 
98 static inline int __ticket_spin_is_contended(arch_spinlock_t *lock)
99 {
100 	long tmp = ACCESS_ONCE(lock->lock);
101 
102 	return ((tmp - (tmp >> TICKET_SHIFT)) & TICKET_MASK) > 1;
103 }
104 
105 static inline int arch_spin_is_locked(arch_spinlock_t *lock)
106 {
107 	return __ticket_spin_is_locked(lock);
108 }
109 
110 static inline int arch_spin_is_contended(arch_spinlock_t *lock)
111 {
112 	return __ticket_spin_is_contended(lock);
113 }
114 #define arch_spin_is_contended	arch_spin_is_contended
115 
116 static __always_inline void arch_spin_lock(arch_spinlock_t *lock)
117 {
118 	__ticket_spin_lock(lock);
119 }
120 
121 static __always_inline int arch_spin_trylock(arch_spinlock_t *lock)
122 {
123 	return __ticket_spin_trylock(lock);
124 }
125 
126 static __always_inline void arch_spin_unlock(arch_spinlock_t *lock)
127 {
128 	__ticket_spin_unlock(lock);
129 }
130 
131 static __always_inline void arch_spin_lock_flags(arch_spinlock_t *lock,
132 						  unsigned long flags)
133 {
134 	arch_spin_lock(lock);
135 }
136 
137 static inline void arch_spin_unlock_wait(arch_spinlock_t *lock)
138 {
139 	__ticket_spin_unlock_wait(lock);
140 }
141 
142 #define arch_read_can_lock(rw)		(*(volatile int *)(rw) >= 0)
143 #define arch_write_can_lock(rw)	(*(volatile int *)(rw) == 0)
144 
145 #ifdef ASM_SUPPORTED
146 
147 static __always_inline void
148 arch_read_lock_flags(arch_rwlock_t *lock, unsigned long flags)
149 {
150 	__asm__ __volatile__ (
151 		"tbit.nz p6, p0 = %1,%2\n"
152 		"br.few 3f\n"
153 		"1:\n"
154 		"fetchadd4.rel r2 = [%0], -1;;\n"
155 		"(p6) ssm psr.i\n"
156 		"2:\n"
157 		"hint @pause\n"
158 		"ld4 r2 = [%0];;\n"
159 		"cmp4.lt p7,p0 = r2, r0\n"
160 		"(p7) br.cond.spnt.few 2b\n"
161 		"(p6) rsm psr.i\n"
162 		";;\n"
163 		"3:\n"
164 		"fetchadd4.acq r2 = [%0], 1;;\n"
165 		"cmp4.lt p7,p0 = r2, r0\n"
166 		"(p7) br.cond.spnt.few 1b\n"
167 		: : "r"(lock), "r"(flags), "i"(IA64_PSR_I_BIT)
168 		: "p6", "p7", "r2", "memory");
169 }
170 
171 #define arch_read_lock(lock) arch_read_lock_flags(lock, 0)
172 
173 #else /* !ASM_SUPPORTED */
174 
175 #define arch_read_lock_flags(rw, flags) arch_read_lock(rw)
176 
177 #define arch_read_lock(rw)								\
178 do {											\
179 	arch_rwlock_t *__read_lock_ptr = (rw);						\
180 											\
181 	while (unlikely(ia64_fetchadd(1, (int *) __read_lock_ptr, acq) < 0)) {		\
182 		ia64_fetchadd(-1, (int *) __read_lock_ptr, rel);			\
183 		while (*(volatile int *)__read_lock_ptr < 0)				\
184 			cpu_relax();							\
185 	}										\
186 } while (0)
187 
188 #endif /* !ASM_SUPPORTED */
189 
190 #define arch_read_unlock(rw)					\
191 do {								\
192 	arch_rwlock_t *__read_lock_ptr = (rw);			\
193 	ia64_fetchadd(-1, (int *) __read_lock_ptr, rel);	\
194 } while (0)
195 
196 #ifdef ASM_SUPPORTED
197 
198 static __always_inline void
199 arch_write_lock_flags(arch_rwlock_t *lock, unsigned long flags)
200 {
201 	__asm__ __volatile__ (
202 		"tbit.nz p6, p0 = %1, %2\n"
203 		"mov ar.ccv = r0\n"
204 		"dep r29 = -1, r0, 31, 1\n"
205 		"br.few 3f;;\n"
206 		"1:\n"
207 		"(p6) ssm psr.i\n"
208 		"2:\n"
209 		"hint @pause\n"
210 		"ld4 r2 = [%0];;\n"
211 		"cmp4.eq p0,p7 = r0, r2\n"
212 		"(p7) br.cond.spnt.few 2b\n"
213 		"(p6) rsm psr.i\n"
214 		";;\n"
215 		"3:\n"
216 		"cmpxchg4.acq r2 = [%0], r29, ar.ccv;;\n"
217 		"cmp4.eq p0,p7 = r0, r2\n"
218 		"(p7) br.cond.spnt.few 1b;;\n"
219 		: : "r"(lock), "r"(flags), "i"(IA64_PSR_I_BIT)
220 		: "ar.ccv", "p6", "p7", "r2", "r29", "memory");
221 }
222 
223 #define arch_write_lock(rw) arch_write_lock_flags(rw, 0)
224 
225 #define arch_write_trylock(rw)							\
226 ({										\
227 	register long result;							\
228 										\
229 	__asm__ __volatile__ (							\
230 		"mov ar.ccv = r0\n"						\
231 		"dep r29 = -1, r0, 31, 1;;\n"					\
232 		"cmpxchg4.acq %0 = [%1], r29, ar.ccv\n"				\
233 		: "=r"(result) : "r"(rw) : "ar.ccv", "r29", "memory");		\
234 	(result == 0);								\
235 })
236 
237 static inline void arch_write_unlock(arch_rwlock_t *x)
238 {
239 	u8 *y = (u8 *)x;
240 	barrier();
241 	asm volatile ("st1.rel.nta [%0] = r0\n\t" :: "r"(y+3) : "memory" );
242 }
243 
244 #else /* !ASM_SUPPORTED */
245 
246 #define arch_write_lock_flags(l, flags) arch_write_lock(l)
247 
248 #define arch_write_lock(l)								\
249 ({											\
250 	__u64 ia64_val, ia64_set_val = ia64_dep_mi(-1, 0, 31, 1);			\
251 	__u32 *ia64_write_lock_ptr = (__u32 *) (l);					\
252 	do {										\
253 		while (*ia64_write_lock_ptr)						\
254 			ia64_barrier();							\
255 		ia64_val = ia64_cmpxchg4_acq(ia64_write_lock_ptr, ia64_set_val, 0);	\
256 	} while (ia64_val);								\
257 })
258 
259 #define arch_write_trylock(rw)						\
260 ({									\
261 	__u64 ia64_val;							\
262 	__u64 ia64_set_val = ia64_dep_mi(-1, 0, 31,1);			\
263 	ia64_val = ia64_cmpxchg4_acq((__u32 *)(rw), ia64_set_val, 0);	\
264 	(ia64_val == 0);						\
265 })
266 
267 static inline void arch_write_unlock(arch_rwlock_t *x)
268 {
269 	barrier();
270 	x->write_lock = 0;
271 }
272 
273 #endif /* !ASM_SUPPORTED */
274 
275 static inline int arch_read_trylock(arch_rwlock_t *x)
276 {
277 	union {
278 		arch_rwlock_t lock;
279 		__u32 word;
280 	} old, new;
281 	old.lock = new.lock = *x;
282 	old.lock.write_lock = new.lock.write_lock = 0;
283 	++new.lock.read_counter;
284 	return (u32)ia64_cmpxchg4_acq((__u32 *)(x), new.word, old.word) == old.word;
285 }
286 
287 #define arch_spin_relax(lock)	cpu_relax()
288 #define arch_read_relax(lock)	cpu_relax()
289 #define arch_write_relax(lock)	cpu_relax()
290 
291 #endif /*  _ASM_IA64_SPINLOCK_H */
292