xref: /openbmc/linux/arch/ia64/include/asm/spinlock.h (revision 160b8e75) 
1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_IA64_SPINLOCK_H
3 #define _ASM_IA64_SPINLOCK_H
4 
5 /*
6  * Copyright (C) 1998-2003 Hewlett-Packard Co
7  *	David Mosberger-Tang <davidm@hpl.hp.com>
8  * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
9  *
10  * This file is used for SMP configurations only.
11  */
12 
13 #include <linux/compiler.h>
14 #include <linux/kernel.h>
15 #include <linux/bitops.h>
16 
17 #include <linux/atomic.h>
18 #include <asm/intrinsics.h>
19 #include <asm/barrier.h>
20 #include <asm/processor.h>
21 
22 #define arch_spin_lock_init(x)			((x)->lock = 0)
23 
24 /*
25  * Ticket locks are conceptually two parts, one indicating the current head of
26  * the queue, and the other indicating the current tail. The lock is acquired
27  * by atomically noting the tail and incrementing it by one (thus adding
28  * ourself to the queue and noting our position), then waiting until the head
29  * becomes equal to the the initial value of the tail.
30  * The pad bits in the middle are used to prevent the next_ticket number
31  * overflowing into the now_serving number.
32  *
33  *   31             17  16    15  14                    0
34  *  +----------------------------------------------------+
35  *  |  now_serving     | padding |   next_ticket         |
36  *  +----------------------------------------------------+
37  */
38 
39 #define TICKET_SHIFT	17
40 #define TICKET_BITS	15
41 #define	TICKET_MASK	((1 << TICKET_BITS) - 1)
42 
43 static __always_inline void __ticket_spin_lock(arch_spinlock_t *lock)
44 {
45 	int	*p = (int *)&lock->lock, ticket, serve;
46 
47 	ticket = ia64_fetchadd(1, p, acq);
48 
49 	if (!(((ticket >> TICKET_SHIFT) ^ ticket) & TICKET_MASK))
50 		return;
51 
52 	ia64_invala();
53 
54 	for (;;) {
55 		asm volatile ("ld4.c.nc %0=[%1]" : "=r"(serve) : "r"(p) : "memory");
56 
57 		if (!(((serve >> TICKET_SHIFT) ^ ticket) & TICKET_MASK))
58 			return;
59 		cpu_relax();
60 	}
61 }
62 
63 static __always_inline int __ticket_spin_trylock(arch_spinlock_t *lock)
64 {
65 	int tmp = READ_ONCE(lock->lock);
66 
67 	if (!(((tmp >> TICKET_SHIFT) ^ tmp) & TICKET_MASK))
68 		return ia64_cmpxchg(acq, &lock->lock, tmp, tmp + 1, sizeof (tmp)) == tmp;
69 	return 0;
70 }
71 
72 static __always_inline void __ticket_spin_unlock(arch_spinlock_t *lock)
73 {
74 	unsigned short	*p = (unsigned short *)&lock->lock + 1, tmp;
75 
76 	asm volatile ("ld2.bias %0=[%1]" : "=r"(tmp) : "r"(p));
77 	WRITE_ONCE(*p, (tmp + 2) & ~1);
78 }
79 
80 static inline int __ticket_spin_is_locked(arch_spinlock_t *lock)
81 {
82 	long tmp = READ_ONCE(lock->lock);
83 
84 	return !!(((tmp >> TICKET_SHIFT) ^ tmp) & TICKET_MASK);
85 }
86 
87 static inline int __ticket_spin_is_contended(arch_spinlock_t *lock)
88 {
89 	long tmp = READ_ONCE(lock->lock);
90 
91 	return ((tmp - (tmp >> TICKET_SHIFT)) & TICKET_MASK) > 1;
92 }
93 
94 static __always_inline int arch_spin_value_unlocked(arch_spinlock_t lock)
95 {
96 	return !(((lock.lock >> TICKET_SHIFT) ^ lock.lock) & TICKET_MASK);
97 }
98 
99 static inline int arch_spin_is_locked(arch_spinlock_t *lock)
100 {
101 	return __ticket_spin_is_locked(lock);
102 }
103 
104 static inline int arch_spin_is_contended(arch_spinlock_t *lock)
105 {
106 	return __ticket_spin_is_contended(lock);
107 }
108 #define arch_spin_is_contended	arch_spin_is_contended
109 
110 static __always_inline void arch_spin_lock(arch_spinlock_t *lock)
111 {
112 	__ticket_spin_lock(lock);
113 }
114 
115 static __always_inline int arch_spin_trylock(arch_spinlock_t *lock)
116 {
117 	return __ticket_spin_trylock(lock);
118 }
119 
120 static __always_inline void arch_spin_unlock(arch_spinlock_t *lock)
121 {
122 	__ticket_spin_unlock(lock);
123 }
124 
125 static __always_inline void arch_spin_lock_flags(arch_spinlock_t *lock,
126 						  unsigned long flags)
127 {
128 	arch_spin_lock(lock);
129 }
130 #define arch_spin_lock_flags	arch_spin_lock_flags
131 
132 #ifdef ASM_SUPPORTED
133 
134 static __always_inline void
135 arch_read_lock_flags(arch_rwlock_t *lock, unsigned long flags)
136 {
137 	__asm__ __volatile__ (
138 		"tbit.nz p6, p0 = %1,%2\n"
139 		"br.few 3f\n"
140 		"1:\n"
141 		"fetchadd4.rel r2 = [%0], -1;;\n"
142 		"(p6) ssm psr.i\n"
143 		"2:\n"
144 		"hint @pause\n"
145 		"ld4 r2 = [%0];;\n"
146 		"cmp4.lt p7,p0 = r2, r0\n"
147 		"(p7) br.cond.spnt.few 2b\n"
148 		"(p6) rsm psr.i\n"
149 		";;\n"
150 		"3:\n"
151 		"fetchadd4.acq r2 = [%0], 1;;\n"
152 		"cmp4.lt p7,p0 = r2, r0\n"
153 		"(p7) br.cond.spnt.few 1b\n"
154 		: : "r"(lock), "r"(flags), "i"(IA64_PSR_I_BIT)
155 		: "p6", "p7", "r2", "memory");
156 }
157 
158 #define arch_read_lock_flags arch_read_lock_flags
159 #define arch_read_lock(lock) arch_read_lock_flags(lock, 0)
160 
161 #else /* !ASM_SUPPORTED */
162 
163 #define arch_read_lock_flags(rw, flags) arch_read_lock(rw)
164 
165 #define arch_read_lock(rw)								\
166 do {											\
167 	arch_rwlock_t *__read_lock_ptr = (rw);						\
168 											\
169 	while (unlikely(ia64_fetchadd(1, (int *) __read_lock_ptr, acq) < 0)) {		\
170 		ia64_fetchadd(-1, (int *) __read_lock_ptr, rel);			\
171 		while (*(volatile int *)__read_lock_ptr < 0)				\
172 			cpu_relax();							\
173 	}										\
174 } while (0)
175 
176 #endif /* !ASM_SUPPORTED */
177 
178 #define arch_read_unlock(rw)					\
179 do {								\
180 	arch_rwlock_t *__read_lock_ptr = (rw);			\
181 	ia64_fetchadd(-1, (int *) __read_lock_ptr, rel);	\
182 } while (0)
183 
184 #ifdef ASM_SUPPORTED
185 
186 static __always_inline void
187 arch_write_lock_flags(arch_rwlock_t *lock, unsigned long flags)
188 {
189 	__asm__ __volatile__ (
190 		"tbit.nz p6, p0 = %1, %2\n"
191 		"mov ar.ccv = r0\n"
192 		"dep r29 = -1, r0, 31, 1\n"
193 		"br.few 3f;;\n"
194 		"1:\n"
195 		"(p6) ssm psr.i\n"
196 		"2:\n"
197 		"hint @pause\n"
198 		"ld4 r2 = [%0];;\n"
199 		"cmp4.eq p0,p7 = r0, r2\n"
200 		"(p7) br.cond.spnt.few 2b\n"
201 		"(p6) rsm psr.i\n"
202 		";;\n"
203 		"3:\n"
204 		"cmpxchg4.acq r2 = [%0], r29, ar.ccv;;\n"
205 		"cmp4.eq p0,p7 = r0, r2\n"
206 		"(p7) br.cond.spnt.few 1b;;\n"
207 		: : "r"(lock), "r"(flags), "i"(IA64_PSR_I_BIT)
208 		: "ar.ccv", "p6", "p7", "r2", "r29", "memory");
209 }
210 
211 #define arch_write_lock_flags arch_write_lock_flags
212 #define arch_write_lock(rw) arch_write_lock_flags(rw, 0)
213 
214 #define arch_write_trylock(rw)							\
215 ({										\
216 	register long result;							\
217 										\
218 	__asm__ __volatile__ (							\
219 		"mov ar.ccv = r0\n"						\
220 		"dep r29 = -1, r0, 31, 1;;\n"					\
221 		"cmpxchg4.acq %0 = [%1], r29, ar.ccv\n"				\
222 		: "=r"(result) : "r"(rw) : "ar.ccv", "r29", "memory");		\
223 	(result == 0);								\
224 })
225 
226 static inline void arch_write_unlock(arch_rwlock_t *x)
227 {
228 	u8 *y = (u8 *)x;
229 	barrier();
230 	asm volatile ("st1.rel.nta [%0] = r0\n\t" :: "r"(y+3) : "memory" );
231 }
232 
233 #else /* !ASM_SUPPORTED */
234 
235 #define arch_write_lock(l)								\
236 ({											\
237 	__u64 ia64_val, ia64_set_val = ia64_dep_mi(-1, 0, 31, 1);			\
238 	__u32 *ia64_write_lock_ptr = (__u32 *) (l);					\
239 	do {										\
240 		while (*ia64_write_lock_ptr)						\
241 			ia64_barrier();							\
242 		ia64_val = ia64_cmpxchg4_acq(ia64_write_lock_ptr, ia64_set_val, 0);	\
243 	} while (ia64_val);								\
244 })
245 
246 #define arch_write_trylock(rw)						\
247 ({									\
248 	__u64 ia64_val;							\
249 	__u64 ia64_set_val = ia64_dep_mi(-1, 0, 31,1);			\
250 	ia64_val = ia64_cmpxchg4_acq((__u32 *)(rw), ia64_set_val, 0);	\
251 	(ia64_val == 0);						\
252 })
253 
254 static inline void arch_write_unlock(arch_rwlock_t *x)
255 {
256 	barrier();
257 	x->write_lock = 0;
258 }
259 
260 #endif /* !ASM_SUPPORTED */
261 
262 static inline int arch_read_trylock(arch_rwlock_t *x)
263 {
264 	union {
265 		arch_rwlock_t lock;
266 		__u32 word;
267 	} old, new;
268 	old.lock = new.lock = *x;
269 	old.lock.write_lock = new.lock.write_lock = 0;
270 	++new.lock.read_counter;
271 	return (u32)ia64_cmpxchg4_acq((__u32 *)(x), new.word, old.word) == old.word;
272 }
273 
274 #endif /*  _ASM_IA64_SPINLOCK_H */
275