1 #ifndef _ASM_IA64_PROCESSOR_H 2 #define _ASM_IA64_PROCESSOR_H 3 4 /* 5 * Copyright (C) 1998-2004 Hewlett-Packard Co 6 * David Mosberger-Tang <davidm@hpl.hp.com> 7 * Stephane Eranian <eranian@hpl.hp.com> 8 * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com> 9 * Copyright (C) 1999 Don Dugger <don.dugger@intel.com> 10 * 11 * 11/24/98 S.Eranian added ia64_set_iva() 12 * 12/03/99 D. Mosberger implement thread_saved_pc() via kernel unwind API 13 * 06/16/00 A. Mallick added csd/ssd/tssd for ia32 support 14 */ 15 16 17 #include <asm/intrinsics.h> 18 #include <asm/kregs.h> 19 #include <asm/ptrace.h> 20 #include <asm/ustack.h> 21 22 #define __ARCH_WANT_UNLOCKED_CTXSW 23 #define ARCH_HAS_PREFETCH_SWITCH_STACK 24 25 #define IA64_NUM_PHYS_STACK_REG 96 26 #define IA64_NUM_DBG_REGS 8 27 28 #define DEFAULT_MAP_BASE __IA64_UL_CONST(0x2000000000000000) 29 #define DEFAULT_TASK_SIZE __IA64_UL_CONST(0xa000000000000000) 30 31 /* 32 * TASK_SIZE really is a mis-named. It really is the maximum user 33 * space address (plus one). On IA-64, there are five regions of 2TB 34 * each (assuming 8KB page size), for a total of 8TB of user virtual 35 * address space. 36 */ 37 #define TASK_SIZE DEFAULT_TASK_SIZE 38 39 /* 40 * This decides where the kernel will search for a free chunk of vm 41 * space during mmap's. 42 */ 43 #define TASK_UNMAPPED_BASE (current->thread.map_base) 44 45 #define IA64_THREAD_FPH_VALID (__IA64_UL(1) << 0) /* floating-point high state valid? */ 46 #define IA64_THREAD_DBG_VALID (__IA64_UL(1) << 1) /* debug registers valid? */ 47 #define IA64_THREAD_PM_VALID (__IA64_UL(1) << 2) /* performance registers valid? */ 48 #define IA64_THREAD_UAC_NOPRINT (__IA64_UL(1) << 3) /* don't log unaligned accesses */ 49 #define IA64_THREAD_UAC_SIGBUS (__IA64_UL(1) << 4) /* generate SIGBUS on unaligned acc. */ 50 #define IA64_THREAD_MIGRATION (__IA64_UL(1) << 5) /* require migration 51 sync at ctx sw */ 52 #define IA64_THREAD_FPEMU_NOPRINT (__IA64_UL(1) << 6) /* don't log any fpswa faults */ 53 #define IA64_THREAD_FPEMU_SIGFPE (__IA64_UL(1) << 7) /* send a SIGFPE for fpswa faults */ 54 55 #define IA64_THREAD_UAC_SHIFT 3 56 #define IA64_THREAD_UAC_MASK (IA64_THREAD_UAC_NOPRINT | IA64_THREAD_UAC_SIGBUS) 57 #define IA64_THREAD_FPEMU_SHIFT 6 58 #define IA64_THREAD_FPEMU_MASK (IA64_THREAD_FPEMU_NOPRINT | IA64_THREAD_FPEMU_SIGFPE) 59 60 61 /* 62 * This shift should be large enough to be able to represent 1000000000/itc_freq with good 63 * accuracy while being small enough to fit 10*1000000000<<IA64_NSEC_PER_CYC_SHIFT in 64 bits 64 * (this will give enough slack to represent 10 seconds worth of time as a scaled number). 65 */ 66 #define IA64_NSEC_PER_CYC_SHIFT 30 67 68 #ifndef __ASSEMBLY__ 69 70 #include <linux/cache.h> 71 #include <linux/compiler.h> 72 #include <linux/threads.h> 73 #include <linux/types.h> 74 75 #include <asm/fpu.h> 76 #include <asm/page.h> 77 #include <asm/percpu.h> 78 #include <asm/rse.h> 79 #include <asm/unwind.h> 80 #include <linux/atomic.h> 81 #ifdef CONFIG_NUMA 82 #include <asm/nodedata.h> 83 #endif 84 85 /* like above but expressed as bitfields for more efficient access: */ 86 struct ia64_psr { 87 __u64 reserved0 : 1; 88 __u64 be : 1; 89 __u64 up : 1; 90 __u64 ac : 1; 91 __u64 mfl : 1; 92 __u64 mfh : 1; 93 __u64 reserved1 : 7; 94 __u64 ic : 1; 95 __u64 i : 1; 96 __u64 pk : 1; 97 __u64 reserved2 : 1; 98 __u64 dt : 1; 99 __u64 dfl : 1; 100 __u64 dfh : 1; 101 __u64 sp : 1; 102 __u64 pp : 1; 103 __u64 di : 1; 104 __u64 si : 1; 105 __u64 db : 1; 106 __u64 lp : 1; 107 __u64 tb : 1; 108 __u64 rt : 1; 109 __u64 reserved3 : 4; 110 __u64 cpl : 2; 111 __u64 is : 1; 112 __u64 mc : 1; 113 __u64 it : 1; 114 __u64 id : 1; 115 __u64 da : 1; 116 __u64 dd : 1; 117 __u64 ss : 1; 118 __u64 ri : 2; 119 __u64 ed : 1; 120 __u64 bn : 1; 121 __u64 reserved4 : 19; 122 }; 123 124 union ia64_isr { 125 __u64 val; 126 struct { 127 __u64 code : 16; 128 __u64 vector : 8; 129 __u64 reserved1 : 8; 130 __u64 x : 1; 131 __u64 w : 1; 132 __u64 r : 1; 133 __u64 na : 1; 134 __u64 sp : 1; 135 __u64 rs : 1; 136 __u64 ir : 1; 137 __u64 ni : 1; 138 __u64 so : 1; 139 __u64 ei : 2; 140 __u64 ed : 1; 141 __u64 reserved2 : 20; 142 }; 143 }; 144 145 union ia64_lid { 146 __u64 val; 147 struct { 148 __u64 rv : 16; 149 __u64 eid : 8; 150 __u64 id : 8; 151 __u64 ig : 32; 152 }; 153 }; 154 155 union ia64_tpr { 156 __u64 val; 157 struct { 158 __u64 ig0 : 4; 159 __u64 mic : 4; 160 __u64 rsv : 8; 161 __u64 mmi : 1; 162 __u64 ig1 : 47; 163 }; 164 }; 165 166 union ia64_itir { 167 __u64 val; 168 struct { 169 __u64 rv3 : 2; /* 0-1 */ 170 __u64 ps : 6; /* 2-7 */ 171 __u64 key : 24; /* 8-31 */ 172 __u64 rv4 : 32; /* 32-63 */ 173 }; 174 }; 175 176 union ia64_rr { 177 __u64 val; 178 struct { 179 __u64 ve : 1; /* enable hw walker */ 180 __u64 reserved0: 1; /* reserved */ 181 __u64 ps : 6; /* log page size */ 182 __u64 rid : 24; /* region id */ 183 __u64 reserved1: 32; /* reserved */ 184 }; 185 }; 186 187 /* 188 * CPU type, hardware bug flags, and per-CPU state. Frequently used 189 * state comes earlier: 190 */ 191 struct cpuinfo_ia64 { 192 unsigned int softirq_pending; 193 unsigned long itm_delta; /* # of clock cycles between clock ticks */ 194 unsigned long itm_next; /* interval timer mask value to use for next clock tick */ 195 unsigned long nsec_per_cyc; /* (1000000000<<IA64_NSEC_PER_CYC_SHIFT)/itc_freq */ 196 unsigned long unimpl_va_mask; /* mask of unimplemented virtual address bits (from PAL) */ 197 unsigned long unimpl_pa_mask; /* mask of unimplemented physical address bits (from PAL) */ 198 unsigned long itc_freq; /* frequency of ITC counter */ 199 unsigned long proc_freq; /* frequency of processor */ 200 unsigned long cyc_per_usec; /* itc_freq/1000000 */ 201 unsigned long ptce_base; 202 unsigned int ptce_count[2]; 203 unsigned int ptce_stride[2]; 204 struct task_struct *ksoftirqd; /* kernel softirq daemon for this CPU */ 205 206 #ifdef CONFIG_SMP 207 unsigned long loops_per_jiffy; 208 int cpu; 209 unsigned int socket_id; /* physical processor socket id */ 210 unsigned short core_id; /* core id */ 211 unsigned short thread_id; /* thread id */ 212 unsigned short num_log; /* Total number of logical processors on 213 * this socket that were successfully booted */ 214 unsigned char cores_per_socket; /* Cores per processor socket */ 215 unsigned char threads_per_core; /* Threads per core */ 216 #endif 217 218 /* CPUID-derived information: */ 219 unsigned long ppn; 220 unsigned long features; 221 unsigned char number; 222 unsigned char revision; 223 unsigned char model; 224 unsigned char family; 225 unsigned char archrev; 226 char vendor[16]; 227 char *model_name; 228 229 #ifdef CONFIG_NUMA 230 struct ia64_node_data *node_data; 231 #endif 232 }; 233 234 DECLARE_PER_CPU(struct cpuinfo_ia64, ia64_cpu_info); 235 236 /* 237 * The "local" data variable. It refers to the per-CPU data of the currently executing 238 * CPU, much like "current" points to the per-task data of the currently executing task. 239 * Do not use the address of local_cpu_data, since it will be different from 240 * cpu_data(smp_processor_id())! 241 */ 242 #define local_cpu_data (&__ia64_per_cpu_var(ia64_cpu_info)) 243 #define cpu_data(cpu) (&per_cpu(ia64_cpu_info, cpu)) 244 245 extern void print_cpu_info (struct cpuinfo_ia64 *); 246 247 typedef struct { 248 unsigned long seg; 249 } mm_segment_t; 250 251 #define SET_UNALIGN_CTL(task,value) \ 252 ({ \ 253 (task)->thread.flags = (((task)->thread.flags & ~IA64_THREAD_UAC_MASK) \ 254 | (((value) << IA64_THREAD_UAC_SHIFT) & IA64_THREAD_UAC_MASK)); \ 255 0; \ 256 }) 257 #define GET_UNALIGN_CTL(task,addr) \ 258 ({ \ 259 put_user(((task)->thread.flags & IA64_THREAD_UAC_MASK) >> IA64_THREAD_UAC_SHIFT, \ 260 (int __user *) (addr)); \ 261 }) 262 263 #define SET_FPEMU_CTL(task,value) \ 264 ({ \ 265 (task)->thread.flags = (((task)->thread.flags & ~IA64_THREAD_FPEMU_MASK) \ 266 | (((value) << IA64_THREAD_FPEMU_SHIFT) & IA64_THREAD_FPEMU_MASK)); \ 267 0; \ 268 }) 269 #define GET_FPEMU_CTL(task,addr) \ 270 ({ \ 271 put_user(((task)->thread.flags & IA64_THREAD_FPEMU_MASK) >> IA64_THREAD_FPEMU_SHIFT, \ 272 (int __user *) (addr)); \ 273 }) 274 275 struct thread_struct { 276 __u32 flags; /* various thread flags (see IA64_THREAD_*) */ 277 /* writing on_ustack is performance-critical, so it's worth spending 8 bits on it... */ 278 __u8 on_ustack; /* executing on user-stacks? */ 279 __u8 pad[3]; 280 __u64 ksp; /* kernel stack pointer */ 281 __u64 map_base; /* base address for get_unmapped_area() */ 282 __u64 rbs_bot; /* the base address for the RBS */ 283 int last_fph_cpu; /* CPU that may hold the contents of f32-f127 */ 284 285 #ifdef CONFIG_PERFMON 286 void *pfm_context; /* pointer to detailed PMU context */ 287 unsigned long pfm_needs_checking; /* when >0, pending perfmon work on kernel exit */ 288 # define INIT_THREAD_PM .pfm_context = NULL, \ 289 .pfm_needs_checking = 0UL, 290 #else 291 # define INIT_THREAD_PM 292 #endif 293 unsigned long dbr[IA64_NUM_DBG_REGS]; 294 unsigned long ibr[IA64_NUM_DBG_REGS]; 295 struct ia64_fpreg fph[96]; /* saved/loaded on demand */ 296 }; 297 298 #define INIT_THREAD { \ 299 .flags = 0, \ 300 .on_ustack = 0, \ 301 .ksp = 0, \ 302 .map_base = DEFAULT_MAP_BASE, \ 303 .rbs_bot = STACK_TOP - DEFAULT_USER_STACK_SIZE, \ 304 .last_fph_cpu = -1, \ 305 INIT_THREAD_PM \ 306 .dbr = {0, }, \ 307 .ibr = {0, }, \ 308 .fph = {{{{0}}}, } \ 309 } 310 311 #define start_thread(regs,new_ip,new_sp) do { \ 312 regs->cr_ipsr = ((regs->cr_ipsr | (IA64_PSR_BITS_TO_SET | IA64_PSR_CPL)) \ 313 & ~(IA64_PSR_BITS_TO_CLEAR | IA64_PSR_RI | IA64_PSR_IS)); \ 314 regs->cr_iip = new_ip; \ 315 regs->ar_rsc = 0xf; /* eager mode, privilege level 3 */ \ 316 regs->ar_rnat = 0; \ 317 regs->ar_bspstore = current->thread.rbs_bot; \ 318 regs->ar_fpsr = FPSR_DEFAULT; \ 319 regs->loadrs = 0; \ 320 regs->r8 = get_dumpable(current->mm); /* set "don't zap registers" flag */ \ 321 regs->r12 = new_sp - 16; /* allocate 16 byte scratch area */ \ 322 if (unlikely(get_dumpable(current->mm) != SUID_DUMP_USER)) { \ 323 /* \ 324 * Zap scratch regs to avoid leaking bits between processes with different \ 325 * uid/privileges. \ 326 */ \ 327 regs->ar_pfs = 0; regs->b0 = 0; regs->pr = 0; \ 328 regs->r1 = 0; regs->r9 = 0; regs->r11 = 0; regs->r13 = 0; regs->r15 = 0; \ 329 } \ 330 } while (0) 331 332 /* Forward declarations, a strange C thing... */ 333 struct mm_struct; 334 struct task_struct; 335 336 /* 337 * Free all resources held by a thread. This is called after the 338 * parent of DEAD_TASK has collected the exit status of the task via 339 * wait(). 340 */ 341 #define release_thread(dead_task) 342 343 /* Get wait channel for task P. */ 344 extern unsigned long get_wchan (struct task_struct *p); 345 346 /* Return instruction pointer of blocked task TSK. */ 347 #define KSTK_EIP(tsk) \ 348 ({ \ 349 struct pt_regs *_regs = task_pt_regs(tsk); \ 350 _regs->cr_iip + ia64_psr(_regs)->ri; \ 351 }) 352 353 /* Return stack pointer of blocked task TSK. */ 354 #define KSTK_ESP(tsk) ((tsk)->thread.ksp) 355 356 extern void ia64_getreg_unknown_kr (void); 357 extern void ia64_setreg_unknown_kr (void); 358 359 #define ia64_get_kr(regnum) \ 360 ({ \ 361 unsigned long r = 0; \ 362 \ 363 switch (regnum) { \ 364 case 0: r = ia64_getreg(_IA64_REG_AR_KR0); break; \ 365 case 1: r = ia64_getreg(_IA64_REG_AR_KR1); break; \ 366 case 2: r = ia64_getreg(_IA64_REG_AR_KR2); break; \ 367 case 3: r = ia64_getreg(_IA64_REG_AR_KR3); break; \ 368 case 4: r = ia64_getreg(_IA64_REG_AR_KR4); break; \ 369 case 5: r = ia64_getreg(_IA64_REG_AR_KR5); break; \ 370 case 6: r = ia64_getreg(_IA64_REG_AR_KR6); break; \ 371 case 7: r = ia64_getreg(_IA64_REG_AR_KR7); break; \ 372 default: ia64_getreg_unknown_kr(); break; \ 373 } \ 374 r; \ 375 }) 376 377 #define ia64_set_kr(regnum, r) \ 378 ({ \ 379 switch (regnum) { \ 380 case 0: ia64_setreg(_IA64_REG_AR_KR0, r); break; \ 381 case 1: ia64_setreg(_IA64_REG_AR_KR1, r); break; \ 382 case 2: ia64_setreg(_IA64_REG_AR_KR2, r); break; \ 383 case 3: ia64_setreg(_IA64_REG_AR_KR3, r); break; \ 384 case 4: ia64_setreg(_IA64_REG_AR_KR4, r); break; \ 385 case 5: ia64_setreg(_IA64_REG_AR_KR5, r); break; \ 386 case 6: ia64_setreg(_IA64_REG_AR_KR6, r); break; \ 387 case 7: ia64_setreg(_IA64_REG_AR_KR7, r); break; \ 388 default: ia64_setreg_unknown_kr(); break; \ 389 } \ 390 }) 391 392 /* 393 * The following three macros can't be inline functions because we don't have struct 394 * task_struct at this point. 395 */ 396 397 /* 398 * Return TRUE if task T owns the fph partition of the CPU we're running on. 399 * Must be called from code that has preemption disabled. 400 */ 401 #define ia64_is_local_fpu_owner(t) \ 402 ({ \ 403 struct task_struct *__ia64_islfo_task = (t); \ 404 (__ia64_islfo_task->thread.last_fph_cpu == smp_processor_id() \ 405 && __ia64_islfo_task == (struct task_struct *) ia64_get_kr(IA64_KR_FPU_OWNER)); \ 406 }) 407 408 /* 409 * Mark task T as owning the fph partition of the CPU we're running on. 410 * Must be called from code that has preemption disabled. 411 */ 412 #define ia64_set_local_fpu_owner(t) do { \ 413 struct task_struct *__ia64_slfo_task = (t); \ 414 __ia64_slfo_task->thread.last_fph_cpu = smp_processor_id(); \ 415 ia64_set_kr(IA64_KR_FPU_OWNER, (unsigned long) __ia64_slfo_task); \ 416 } while (0) 417 418 /* Mark the fph partition of task T as being invalid on all CPUs. */ 419 #define ia64_drop_fpu(t) ((t)->thread.last_fph_cpu = -1) 420 421 extern void __ia64_init_fpu (void); 422 extern void __ia64_save_fpu (struct ia64_fpreg *fph); 423 extern void __ia64_load_fpu (struct ia64_fpreg *fph); 424 extern void ia64_save_debug_regs (unsigned long *save_area); 425 extern void ia64_load_debug_regs (unsigned long *save_area); 426 427 #define ia64_fph_enable() do { ia64_rsm(IA64_PSR_DFH); ia64_srlz_d(); } while (0) 428 #define ia64_fph_disable() do { ia64_ssm(IA64_PSR_DFH); ia64_srlz_d(); } while (0) 429 430 /* load fp 0.0 into fph */ 431 static inline void 432 ia64_init_fpu (void) { 433 ia64_fph_enable(); 434 __ia64_init_fpu(); 435 ia64_fph_disable(); 436 } 437 438 /* save f32-f127 at FPH */ 439 static inline void 440 ia64_save_fpu (struct ia64_fpreg *fph) { 441 ia64_fph_enable(); 442 __ia64_save_fpu(fph); 443 ia64_fph_disable(); 444 } 445 446 /* load f32-f127 from FPH */ 447 static inline void 448 ia64_load_fpu (struct ia64_fpreg *fph) { 449 ia64_fph_enable(); 450 __ia64_load_fpu(fph); 451 ia64_fph_disable(); 452 } 453 454 static inline __u64 455 ia64_clear_ic (void) 456 { 457 __u64 psr; 458 psr = ia64_getreg(_IA64_REG_PSR); 459 ia64_stop(); 460 ia64_rsm(IA64_PSR_I | IA64_PSR_IC); 461 ia64_srlz_i(); 462 return psr; 463 } 464 465 /* 466 * Restore the psr. 467 */ 468 static inline void 469 ia64_set_psr (__u64 psr) 470 { 471 ia64_stop(); 472 ia64_setreg(_IA64_REG_PSR_L, psr); 473 ia64_srlz_i(); 474 } 475 476 /* 477 * Insert a translation into an instruction and/or data translation 478 * register. 479 */ 480 static inline void 481 ia64_itr (__u64 target_mask, __u64 tr_num, 482 __u64 vmaddr, __u64 pte, 483 __u64 log_page_size) 484 { 485 ia64_setreg(_IA64_REG_CR_ITIR, (log_page_size << 2)); 486 ia64_setreg(_IA64_REG_CR_IFA, vmaddr); 487 ia64_stop(); 488 if (target_mask & 0x1) 489 ia64_itri(tr_num, pte); 490 if (target_mask & 0x2) 491 ia64_itrd(tr_num, pte); 492 } 493 494 /* 495 * Insert a translation into the instruction and/or data translation 496 * cache. 497 */ 498 static inline void 499 ia64_itc (__u64 target_mask, __u64 vmaddr, __u64 pte, 500 __u64 log_page_size) 501 { 502 ia64_setreg(_IA64_REG_CR_ITIR, (log_page_size << 2)); 503 ia64_setreg(_IA64_REG_CR_IFA, vmaddr); 504 ia64_stop(); 505 /* as per EAS2.6, itc must be the last instruction in an instruction group */ 506 if (target_mask & 0x1) 507 ia64_itci(pte); 508 if (target_mask & 0x2) 509 ia64_itcd(pte); 510 } 511 512 /* 513 * Purge a range of addresses from instruction and/or data translation 514 * register(s). 515 */ 516 static inline void 517 ia64_ptr (__u64 target_mask, __u64 vmaddr, __u64 log_size) 518 { 519 if (target_mask & 0x1) 520 ia64_ptri(vmaddr, (log_size << 2)); 521 if (target_mask & 0x2) 522 ia64_ptrd(vmaddr, (log_size << 2)); 523 } 524 525 /* Set the interrupt vector address. The address must be suitably aligned (32KB). */ 526 static inline void 527 ia64_set_iva (void *ivt_addr) 528 { 529 ia64_setreg(_IA64_REG_CR_IVA, (__u64) ivt_addr); 530 ia64_srlz_i(); 531 } 532 533 /* Set the page table address and control bits. */ 534 static inline void 535 ia64_set_pta (__u64 pta) 536 { 537 /* Note: srlz.i implies srlz.d */ 538 ia64_setreg(_IA64_REG_CR_PTA, pta); 539 ia64_srlz_i(); 540 } 541 542 static inline void 543 ia64_eoi (void) 544 { 545 ia64_setreg(_IA64_REG_CR_EOI, 0); 546 ia64_srlz_d(); 547 } 548 549 #define cpu_relax() ia64_hint(ia64_hint_pause) 550 551 static inline int 552 ia64_get_irr(unsigned int vector) 553 { 554 unsigned int reg = vector / 64; 555 unsigned int bit = vector % 64; 556 u64 irr; 557 558 switch (reg) { 559 case 0: irr = ia64_getreg(_IA64_REG_CR_IRR0); break; 560 case 1: irr = ia64_getreg(_IA64_REG_CR_IRR1); break; 561 case 2: irr = ia64_getreg(_IA64_REG_CR_IRR2); break; 562 case 3: irr = ia64_getreg(_IA64_REG_CR_IRR3); break; 563 } 564 565 return test_bit(bit, &irr); 566 } 567 568 static inline void 569 ia64_set_lrr0 (unsigned long val) 570 { 571 ia64_setreg(_IA64_REG_CR_LRR0, val); 572 ia64_srlz_d(); 573 } 574 575 static inline void 576 ia64_set_lrr1 (unsigned long val) 577 { 578 ia64_setreg(_IA64_REG_CR_LRR1, val); 579 ia64_srlz_d(); 580 } 581 582 583 /* 584 * Given the address to which a spill occurred, return the unat bit 585 * number that corresponds to this address. 586 */ 587 static inline __u64 588 ia64_unat_pos (void *spill_addr) 589 { 590 return ((__u64) spill_addr >> 3) & 0x3f; 591 } 592 593 /* 594 * Set the NaT bit of an integer register which was spilled at address 595 * SPILL_ADDR. UNAT is the mask to be updated. 596 */ 597 static inline void 598 ia64_set_unat (__u64 *unat, void *spill_addr, unsigned long nat) 599 { 600 __u64 bit = ia64_unat_pos(spill_addr); 601 __u64 mask = 1UL << bit; 602 603 *unat = (*unat & ~mask) | (nat << bit); 604 } 605 606 /* 607 * Return saved PC of a blocked thread. 608 * Note that the only way T can block is through a call to schedule() -> switch_to(). 609 */ 610 static inline unsigned long 611 thread_saved_pc (struct task_struct *t) 612 { 613 struct unw_frame_info info; 614 unsigned long ip; 615 616 unw_init_from_blocked_task(&info, t); 617 if (unw_unwind(&info) < 0) 618 return 0; 619 unw_get_ip(&info, &ip); 620 return ip; 621 } 622 623 /* 624 * Get the current instruction/program counter value. 625 */ 626 #define current_text_addr() \ 627 ({ void *_pc; _pc = (void *)ia64_getreg(_IA64_REG_IP); _pc; }) 628 629 static inline __u64 630 ia64_get_ivr (void) 631 { 632 __u64 r; 633 ia64_srlz_d(); 634 r = ia64_getreg(_IA64_REG_CR_IVR); 635 ia64_srlz_d(); 636 return r; 637 } 638 639 static inline void 640 ia64_set_dbr (__u64 regnum, __u64 value) 641 { 642 __ia64_set_dbr(regnum, value); 643 #ifdef CONFIG_ITANIUM 644 ia64_srlz_d(); 645 #endif 646 } 647 648 static inline __u64 649 ia64_get_dbr (__u64 regnum) 650 { 651 __u64 retval; 652 653 retval = __ia64_get_dbr(regnum); 654 #ifdef CONFIG_ITANIUM 655 ia64_srlz_d(); 656 #endif 657 return retval; 658 } 659 660 static inline __u64 661 ia64_rotr (__u64 w, __u64 n) 662 { 663 return (w >> n) | (w << (64 - n)); 664 } 665 666 #define ia64_rotl(w,n) ia64_rotr((w), (64) - (n)) 667 668 /* 669 * Take a mapped kernel address and return the equivalent address 670 * in the region 7 identity mapped virtual area. 671 */ 672 static inline void * 673 ia64_imva (void *addr) 674 { 675 void *result; 676 result = (void *) ia64_tpa(addr); 677 return __va(result); 678 } 679 680 #define ARCH_HAS_PREFETCH 681 #define ARCH_HAS_PREFETCHW 682 #define ARCH_HAS_SPINLOCK_PREFETCH 683 #define PREFETCH_STRIDE L1_CACHE_BYTES 684 685 static inline void 686 prefetch (const void *x) 687 { 688 ia64_lfetch(ia64_lfhint_none, x); 689 } 690 691 static inline void 692 prefetchw (const void *x) 693 { 694 ia64_lfetch_excl(ia64_lfhint_none, x); 695 } 696 697 #define spin_lock_prefetch(x) prefetchw(x) 698 699 extern unsigned long boot_option_idle_override; 700 701 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_FORCE_MWAIT, 702 IDLE_NOMWAIT, IDLE_POLL}; 703 704 void default_idle(void); 705 706 #define ia64_platform_is(x) (strcmp(x, ia64_platform_name) == 0) 707 708 #endif /* !__ASSEMBLY__ */ 709 710 #endif /* _ASM_IA64_PROCESSOR_H */ 711