1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_IA64_PGTABLE_H 3 #define _ASM_IA64_PGTABLE_H 4 5 /* 6 * This file contains the functions and defines necessary to modify and use 7 * the IA-64 page table tree. 8 * 9 * This hopefully works with any (fixed) IA-64 page-size, as defined 10 * in <asm/page.h>. 11 * 12 * Copyright (C) 1998-2005 Hewlett-Packard Co 13 * David Mosberger-Tang <davidm@hpl.hp.com> 14 */ 15 16 17 #include <asm/mman.h> 18 #include <asm/page.h> 19 #include <asm/processor.h> 20 #include <asm/types.h> 21 22 #define IA64_MAX_PHYS_BITS 50 /* max. number of physical address bits (architected) */ 23 24 /* 25 * First, define the various bits in a PTE. Note that the PTE format 26 * matches the VHPT short format, the firt doubleword of the VHPD long 27 * format, and the first doubleword of the TLB insertion format. 28 */ 29 #define _PAGE_P_BIT 0 30 #define _PAGE_A_BIT 5 31 #define _PAGE_D_BIT 6 32 33 #define _PAGE_P (1 << _PAGE_P_BIT) /* page present bit */ 34 #define _PAGE_MA_WB (0x0 << 2) /* write back memory attribute */ 35 #define _PAGE_MA_UC (0x4 << 2) /* uncacheable memory attribute */ 36 #define _PAGE_MA_UCE (0x5 << 2) /* UC exported attribute */ 37 #define _PAGE_MA_WC (0x6 << 2) /* write coalescing memory attribute */ 38 #define _PAGE_MA_NAT (0x7 << 2) /* not-a-thing attribute */ 39 #define _PAGE_MA_MASK (0x7 << 2) 40 #define _PAGE_PL_0 (0 << 7) /* privilege level 0 (kernel) */ 41 #define _PAGE_PL_1 (1 << 7) /* privilege level 1 (unused) */ 42 #define _PAGE_PL_2 (2 << 7) /* privilege level 2 (unused) */ 43 #define _PAGE_PL_3 (3 << 7) /* privilege level 3 (user) */ 44 #define _PAGE_PL_MASK (3 << 7) 45 #define _PAGE_AR_R (0 << 9) /* read only */ 46 #define _PAGE_AR_RX (1 << 9) /* read & execute */ 47 #define _PAGE_AR_RW (2 << 9) /* read & write */ 48 #define _PAGE_AR_RWX (3 << 9) /* read, write & execute */ 49 #define _PAGE_AR_R_RW (4 << 9) /* read / read & write */ 50 #define _PAGE_AR_RX_RWX (5 << 9) /* read & exec / read, write & exec */ 51 #define _PAGE_AR_RWX_RW (6 << 9) /* read, write & exec / read & write */ 52 #define _PAGE_AR_X_RX (7 << 9) /* exec & promote / read & exec */ 53 #define _PAGE_AR_MASK (7 << 9) 54 #define _PAGE_AR_SHIFT 9 55 #define _PAGE_A (1 << _PAGE_A_BIT) /* page accessed bit */ 56 #define _PAGE_D (1 << _PAGE_D_BIT) /* page dirty bit */ 57 #define _PAGE_PPN_MASK (((__IA64_UL(1) << IA64_MAX_PHYS_BITS) - 1) & ~0xfffUL) 58 #define _PAGE_ED (__IA64_UL(1) << 52) /* exception deferral */ 59 #define _PAGE_PROTNONE (__IA64_UL(1) << 63) 60 61 #define _PFN_MASK _PAGE_PPN_MASK 62 /* Mask of bits which may be changed by pte_modify(); the odd bits are there for _PAGE_PROTNONE */ 63 #define _PAGE_CHG_MASK (_PAGE_P | _PAGE_PROTNONE | _PAGE_PL_MASK | _PAGE_AR_MASK | _PAGE_ED) 64 65 #define _PAGE_SIZE_4K 12 66 #define _PAGE_SIZE_8K 13 67 #define _PAGE_SIZE_16K 14 68 #define _PAGE_SIZE_64K 16 69 #define _PAGE_SIZE_256K 18 70 #define _PAGE_SIZE_1M 20 71 #define _PAGE_SIZE_4M 22 72 #define _PAGE_SIZE_16M 24 73 #define _PAGE_SIZE_64M 26 74 #define _PAGE_SIZE_256M 28 75 #define _PAGE_SIZE_1G 30 76 #define _PAGE_SIZE_4G 32 77 78 #define __ACCESS_BITS _PAGE_ED | _PAGE_A | _PAGE_P | _PAGE_MA_WB 79 #define __DIRTY_BITS_NO_ED _PAGE_A | _PAGE_P | _PAGE_D | _PAGE_MA_WB 80 #define __DIRTY_BITS _PAGE_ED | __DIRTY_BITS_NO_ED 81 82 /* 83 * How many pointers will a page table level hold expressed in shift 84 */ 85 #define PTRS_PER_PTD_SHIFT (PAGE_SHIFT-3) 86 87 /* 88 * Definitions for fourth level: 89 */ 90 #define PTRS_PER_PTE (__IA64_UL(1) << (PTRS_PER_PTD_SHIFT)) 91 92 /* 93 * Definitions for third level: 94 * 95 * PMD_SHIFT determines the size of the area a third-level page table 96 * can map. 97 */ 98 #define PMD_SHIFT (PAGE_SHIFT + (PTRS_PER_PTD_SHIFT)) 99 #define PMD_SIZE (1UL << PMD_SHIFT) 100 #define PMD_MASK (~(PMD_SIZE-1)) 101 #define PTRS_PER_PMD (1UL << (PTRS_PER_PTD_SHIFT)) 102 103 #if CONFIG_PGTABLE_LEVELS == 4 104 /* 105 * Definitions for second level: 106 * 107 * PUD_SHIFT determines the size of the area a second-level page table 108 * can map. 109 */ 110 #define PUD_SHIFT (PMD_SHIFT + (PTRS_PER_PTD_SHIFT)) 111 #define PUD_SIZE (1UL << PUD_SHIFT) 112 #define PUD_MASK (~(PUD_SIZE-1)) 113 #define PTRS_PER_PUD (1UL << (PTRS_PER_PTD_SHIFT)) 114 #endif 115 116 /* 117 * Definitions for first level: 118 * 119 * PGDIR_SHIFT determines what a first-level page table entry can map. 120 */ 121 #if CONFIG_PGTABLE_LEVELS == 4 122 #define PGDIR_SHIFT (PUD_SHIFT + (PTRS_PER_PTD_SHIFT)) 123 #else 124 #define PGDIR_SHIFT (PMD_SHIFT + (PTRS_PER_PTD_SHIFT)) 125 #endif 126 #define PGDIR_SIZE (__IA64_UL(1) << PGDIR_SHIFT) 127 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 128 #define PTRS_PER_PGD_SHIFT PTRS_PER_PTD_SHIFT 129 #define PTRS_PER_PGD (1UL << PTRS_PER_PGD_SHIFT) 130 #define USER_PTRS_PER_PGD (5*PTRS_PER_PGD/8) /* regions 0-4 are user regions */ 131 132 /* 133 * All the normal masks have the "page accessed" bits on, as any time 134 * they are used, the page is accessed. They are cleared only by the 135 * page-out routines. 136 */ 137 #define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_A) 138 #define PAGE_SHARED __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RW) 139 #define PAGE_READONLY __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_R) 140 #define PAGE_COPY __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_R) 141 #define PAGE_COPY_EXEC __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX) 142 #define PAGE_GATE __pgprot(__ACCESS_BITS | _PAGE_PL_0 | _PAGE_AR_X_RX) 143 #define PAGE_KERNEL __pgprot(__DIRTY_BITS | _PAGE_PL_0 | _PAGE_AR_RWX) 144 #define PAGE_KERNELRX __pgprot(__ACCESS_BITS | _PAGE_PL_0 | _PAGE_AR_RX) 145 #define PAGE_KERNEL_UC __pgprot(__DIRTY_BITS | _PAGE_PL_0 | _PAGE_AR_RWX | \ 146 _PAGE_MA_UC) 147 148 # ifndef __ASSEMBLY__ 149 150 #include <linux/sched/mm.h> /* for mm_struct */ 151 #include <linux/bitops.h> 152 #include <asm/cacheflush.h> 153 #include <asm/mmu_context.h> 154 155 /* 156 * Next come the mappings that determine how mmap() protection bits 157 * (PROT_EXEC, PROT_READ, PROT_WRITE, PROT_NONE) get implemented. The 158 * _P version gets used for a private shared memory segment, the _S 159 * version gets used for a shared memory segment with MAP_SHARED on. 160 * In a private shared memory segment, we do a copy-on-write if a task 161 * attempts to write to the page. 162 */ 163 /* xwr */ 164 #define __P000 PAGE_NONE 165 #define __P001 PAGE_READONLY 166 #define __P010 PAGE_READONLY /* write to priv pg -> copy & make writable */ 167 #define __P011 PAGE_READONLY /* ditto */ 168 #define __P100 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_X_RX) 169 #define __P101 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX) 170 #define __P110 PAGE_COPY_EXEC 171 #define __P111 PAGE_COPY_EXEC 172 173 #define __S000 PAGE_NONE 174 #define __S001 PAGE_READONLY 175 #define __S010 PAGE_SHARED /* we don't have (and don't need) write-only */ 176 #define __S011 PAGE_SHARED 177 #define __S100 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_X_RX) 178 #define __S101 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX) 179 #define __S110 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RWX) 180 #define __S111 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RWX) 181 182 #define pgd_ERROR(e) printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e)) 183 #if CONFIG_PGTABLE_LEVELS == 4 184 #define pud_ERROR(e) printk("%s:%d: bad pud %016lx.\n", __FILE__, __LINE__, pud_val(e)) 185 #endif 186 #define pmd_ERROR(e) printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e)) 187 #define pte_ERROR(e) printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e)) 188 189 190 /* 191 * Some definitions to translate between mem_map, PTEs, and page addresses: 192 */ 193 194 195 /* Quick test to see if ADDR is a (potentially) valid physical address. */ 196 static inline long 197 ia64_phys_addr_valid (unsigned long addr) 198 { 199 return (addr & (local_cpu_data->unimpl_pa_mask)) == 0; 200 } 201 202 /* 203 * kern_addr_valid(ADDR) tests if ADDR is pointing to valid kernel 204 * memory. For the return value to be meaningful, ADDR must be >= 205 * PAGE_OFFSET. This operation can be relatively expensive (e.g., 206 * require a hash-, or multi-level tree-lookup or something of that 207 * sort) but it guarantees to return TRUE only if accessing the page 208 * at that address does not cause an error. Note that there may be 209 * addresses for which kern_addr_valid() returns FALSE even though an 210 * access would not cause an error (e.g., this is typically true for 211 * memory mapped I/O regions. 212 * 213 * XXX Need to implement this for IA-64. 214 */ 215 #define kern_addr_valid(addr) (1) 216 217 218 /* 219 * Now come the defines and routines to manage and access the three-level 220 * page table. 221 */ 222 223 224 #define VMALLOC_START (RGN_BASE(RGN_GATE) + 0x200000000UL) 225 #if defined(CONFIG_SPARSEMEM) && defined(CONFIG_SPARSEMEM_VMEMMAP) 226 /* SPARSEMEM_VMEMMAP uses half of vmalloc... */ 227 # define VMALLOC_END (RGN_BASE(RGN_GATE) + (1UL << (4*PAGE_SHIFT - 10))) 228 # define vmemmap ((struct page *)VMALLOC_END) 229 #else 230 # define VMALLOC_END (RGN_BASE(RGN_GATE) + (1UL << (4*PAGE_SHIFT - 9))) 231 #endif 232 233 /* fs/proc/kcore.c */ 234 #define kc_vaddr_to_offset(v) ((v) - RGN_BASE(RGN_GATE)) 235 #define kc_offset_to_vaddr(o) ((o) + RGN_BASE(RGN_GATE)) 236 237 #define RGN_MAP_SHIFT (PGDIR_SHIFT + PTRS_PER_PGD_SHIFT - 3) 238 #define RGN_MAP_LIMIT ((1UL << RGN_MAP_SHIFT) - PAGE_SIZE) /* per region addr limit */ 239 240 /* 241 * Conversion functions: convert page frame number (pfn) and a protection value to a page 242 * table entry (pte). 243 */ 244 #define pfn_pte(pfn, pgprot) \ 245 ({ pte_t __pte; pte_val(__pte) = ((pfn) << PAGE_SHIFT) | pgprot_val(pgprot); __pte; }) 246 247 /* Extract pfn from pte. */ 248 #define pte_pfn(_pte) ((pte_val(_pte) & _PFN_MASK) >> PAGE_SHIFT) 249 250 #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) 251 252 /* This takes a physical page address that is used by the remapping functions */ 253 #define mk_pte_phys(physpage, pgprot) \ 254 ({ pte_t __pte; pte_val(__pte) = physpage + pgprot_val(pgprot); __pte; }) 255 256 #define pte_modify(_pte, newprot) \ 257 (__pte((pte_val(_pte) & ~_PAGE_CHG_MASK) | (pgprot_val(newprot) & _PAGE_CHG_MASK))) 258 259 #define pte_none(pte) (!pte_val(pte)) 260 #define pte_present(pte) (pte_val(pte) & (_PAGE_P | _PAGE_PROTNONE)) 261 #define pte_clear(mm,addr,pte) (pte_val(*(pte)) = 0UL) 262 /* pte_page() returns the "struct page *" corresponding to the PTE: */ 263 #define pte_page(pte) virt_to_page(((pte_val(pte) & _PFN_MASK) + PAGE_OFFSET)) 264 265 #define pmd_none(pmd) (!pmd_val(pmd)) 266 #define pmd_bad(pmd) (!ia64_phys_addr_valid(pmd_val(pmd))) 267 #define pmd_present(pmd) (pmd_val(pmd) != 0UL) 268 #define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0UL) 269 #define pmd_page_vaddr(pmd) ((unsigned long) __va(pmd_val(pmd) & _PFN_MASK)) 270 #define pmd_page(pmd) virt_to_page((pmd_val(pmd) + PAGE_OFFSET)) 271 272 #define pud_none(pud) (!pud_val(pud)) 273 #define pud_bad(pud) (!ia64_phys_addr_valid(pud_val(pud))) 274 #define pud_present(pud) (pud_val(pud) != 0UL) 275 #define pud_clear(pudp) (pud_val(*(pudp)) = 0UL) 276 #define pud_pgtable(pud) ((pmd_t *) __va(pud_val(pud) & _PFN_MASK)) 277 #define pud_page(pud) virt_to_page((pud_val(pud) + PAGE_OFFSET)) 278 279 #if CONFIG_PGTABLE_LEVELS == 4 280 #define p4d_none(p4d) (!p4d_val(p4d)) 281 #define p4d_bad(p4d) (!ia64_phys_addr_valid(p4d_val(p4d))) 282 #define p4d_present(p4d) (p4d_val(p4d) != 0UL) 283 #define p4d_clear(p4dp) (p4d_val(*(p4dp)) = 0UL) 284 #define p4d_pgtable(p4d) ((pud_t *) __va(p4d_val(p4d) & _PFN_MASK)) 285 #define p4d_page(p4d) virt_to_page((p4d_val(p4d) + PAGE_OFFSET)) 286 #endif 287 288 /* 289 * The following have defined behavior only work if pte_present() is true. 290 */ 291 #define pte_write(pte) ((unsigned) (((pte_val(pte) & _PAGE_AR_MASK) >> _PAGE_AR_SHIFT) - 2) <= 4) 292 #define pte_exec(pte) ((pte_val(pte) & _PAGE_AR_RX) != 0) 293 #define pte_dirty(pte) ((pte_val(pte) & _PAGE_D) != 0) 294 #define pte_young(pte) ((pte_val(pte) & _PAGE_A) != 0) 295 296 /* 297 * Note: we convert AR_RWX to AR_RX and AR_RW to AR_R by clearing the 2nd bit in the 298 * access rights: 299 */ 300 #define pte_wrprotect(pte) (__pte(pte_val(pte) & ~_PAGE_AR_RW)) 301 #define pte_mkwrite(pte) (__pte(pte_val(pte) | _PAGE_AR_RW)) 302 #define pte_mkold(pte) (__pte(pte_val(pte) & ~_PAGE_A)) 303 #define pte_mkyoung(pte) (__pte(pte_val(pte) | _PAGE_A)) 304 #define pte_mkclean(pte) (__pte(pte_val(pte) & ~_PAGE_D)) 305 #define pte_mkdirty(pte) (__pte(pte_val(pte) | _PAGE_D)) 306 #define pte_mkhuge(pte) (__pte(pte_val(pte))) 307 308 /* 309 * Because ia64's Icache and Dcache is not coherent (on a cpu), we need to 310 * sync icache and dcache when we insert *new* executable page. 311 * __ia64_sync_icache_dcache() check Pg_arch_1 bit and flush icache 312 * if necessary. 313 * 314 * set_pte() is also called by the kernel, but we can expect that the kernel 315 * flushes icache explicitly if necessary. 316 */ 317 #define pte_present_exec_user(pte)\ 318 ((pte_val(pte) & (_PAGE_P | _PAGE_PL_MASK | _PAGE_AR_RX)) == \ 319 (_PAGE_P | _PAGE_PL_3 | _PAGE_AR_RX)) 320 321 extern void __ia64_sync_icache_dcache(pte_t pteval); 322 static inline void set_pte(pte_t *ptep, pte_t pteval) 323 { 324 /* page is present && page is user && page is executable 325 * && (page swapin or new page or page migration 326 * || copy_on_write with page copying.) 327 */ 328 if (pte_present_exec_user(pteval) && 329 (!pte_present(*ptep) || 330 pte_pfn(*ptep) != pte_pfn(pteval))) 331 /* load_module() calles flush_icache_range() explicitly*/ 332 __ia64_sync_icache_dcache(pteval); 333 *ptep = pteval; 334 } 335 336 #define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) 337 338 /* 339 * Make page protection values cacheable, uncacheable, or write- 340 * combining. Note that "protection" is really a misnomer here as the 341 * protection value contains the memory attribute bits, dirty bits, and 342 * various other bits as well. 343 */ 344 #define pgprot_cacheable(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_WB) 345 #define pgprot_noncached(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_UC) 346 #define pgprot_writecombine(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_WC) 347 348 struct file; 349 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 350 unsigned long size, pgprot_t vma_prot); 351 #define __HAVE_PHYS_MEM_ACCESS_PROT 352 353 static inline unsigned long 354 pgd_index (unsigned long address) 355 { 356 unsigned long region = address >> 61; 357 unsigned long l1index = (address >> PGDIR_SHIFT) & ((PTRS_PER_PGD >> 3) - 1); 358 359 return (region << (PAGE_SHIFT - 6)) | l1index; 360 } 361 #define pgd_index pgd_index 362 363 /* 364 * In the kernel's mapped region we know everything is in region number 5, so 365 * as an optimisation its PGD already points to the area for that region. 366 * However, this also means that we cannot use pgd_index() and we must 367 * never add the region here. 368 */ 369 #define pgd_offset_k(addr) \ 370 (init_mm.pgd + (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))) 371 372 /* Look up a pgd entry in the gate area. On IA-64, the gate-area 373 resides in the kernel-mapped segment, hence we use pgd_offset_k() 374 here. */ 375 #define pgd_offset_gate(mm, addr) pgd_offset_k(addr) 376 377 /* atomic versions of the some PTE manipulations: */ 378 379 static inline int 380 ptep_test_and_clear_young (struct vm_area_struct *vma, unsigned long addr, pte_t *ptep) 381 { 382 #ifdef CONFIG_SMP 383 if (!pte_young(*ptep)) 384 return 0; 385 return test_and_clear_bit(_PAGE_A_BIT, ptep); 386 #else 387 pte_t pte = *ptep; 388 if (!pte_young(pte)) 389 return 0; 390 set_pte_at(vma->vm_mm, addr, ptep, pte_mkold(pte)); 391 return 1; 392 #endif 393 } 394 395 static inline pte_t 396 ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 397 { 398 #ifdef CONFIG_SMP 399 return __pte(xchg((long *) ptep, 0)); 400 #else 401 pte_t pte = *ptep; 402 pte_clear(mm, addr, ptep); 403 return pte; 404 #endif 405 } 406 407 static inline void 408 ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 409 { 410 #ifdef CONFIG_SMP 411 unsigned long new, old; 412 413 do { 414 old = pte_val(*ptep); 415 new = pte_val(pte_wrprotect(__pte (old))); 416 } while (cmpxchg((unsigned long *) ptep, old, new) != old); 417 #else 418 pte_t old_pte = *ptep; 419 set_pte_at(mm, addr, ptep, pte_wrprotect(old_pte)); 420 #endif 421 } 422 423 static inline int 424 pte_same (pte_t a, pte_t b) 425 { 426 return pte_val(a) == pte_val(b); 427 } 428 429 #define update_mmu_cache(vma, address, ptep) do { } while (0) 430 431 extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 432 extern void paging_init (void); 433 434 /* 435 * Note: The macros below rely on the fact that MAX_SWAPFILES_SHIFT <= number of 436 * bits in the swap-type field of the swap pte. It would be nice to 437 * enforce that, but we can't easily include <linux/swap.h> here. 438 * (Of course, better still would be to define MAX_SWAPFILES_SHIFT here...). 439 * 440 * Format of swap pte: 441 * bit 0 : present bit (must be zero) 442 * bits 1- 7: swap-type 443 * bits 8-62: swap offset 444 * bit 63 : _PAGE_PROTNONE bit 445 */ 446 #define __swp_type(entry) (((entry).val >> 1) & 0x7f) 447 #define __swp_offset(entry) (((entry).val << 1) >> 9) 448 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 1) | ((long) (offset) << 8) }) 449 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 450 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 451 452 /* 453 * ZERO_PAGE is a global shared page that is always zero: used 454 * for zero-mapped memory areas etc.. 455 */ 456 extern unsigned long empty_zero_page[PAGE_SIZE/sizeof(unsigned long)]; 457 extern struct page *zero_page_memmap_ptr; 458 #define ZERO_PAGE(vaddr) (zero_page_memmap_ptr) 459 460 /* We provide our own get_unmapped_area to cope with VA holes for userland */ 461 #define HAVE_ARCH_UNMAPPED_AREA 462 463 #ifdef CONFIG_HUGETLB_PAGE 464 #define HUGETLB_PGDIR_SHIFT (HPAGE_SHIFT + 2*(PAGE_SHIFT-3)) 465 #define HUGETLB_PGDIR_SIZE (__IA64_UL(1) << HUGETLB_PGDIR_SHIFT) 466 #define HUGETLB_PGDIR_MASK (~(HUGETLB_PGDIR_SIZE-1)) 467 #endif 468 469 470 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 471 /* 472 * Update PTEP with ENTRY, which is guaranteed to be a less 473 * restrictive PTE. That is, ENTRY may have the ACCESSED, DIRTY, and 474 * WRITABLE bits turned on, when the value at PTEP did not. The 475 * WRITABLE bit may only be turned if SAFELY_WRITABLE is TRUE. 476 * 477 * SAFELY_WRITABLE is TRUE if we can update the value at PTEP without 478 * having to worry about races. On SMP machines, there are only two 479 * cases where this is true: 480 * 481 * (1) *PTEP has the PRESENT bit turned OFF 482 * (2) ENTRY has the DIRTY bit turned ON 483 * 484 * On ia64, we could implement this routine with a cmpxchg()-loop 485 * which ORs in the _PAGE_A/_PAGE_D bit if they're set in ENTRY. 486 * However, like on x86, we can get a more streamlined version by 487 * observing that it is OK to drop ACCESSED bit updates when 488 * SAFELY_WRITABLE is FALSE. Besides being rare, all that would do is 489 * result in an extra Access-bit fault, which would then turn on the 490 * ACCESSED bit in the low-level fault handler (iaccess_bit or 491 * daccess_bit in ivt.S). 492 */ 493 #ifdef CONFIG_SMP 494 # define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __safely_writable) \ 495 ({ \ 496 int __changed = !pte_same(*(__ptep), __entry); \ 497 if (__changed && __safely_writable) { \ 498 set_pte(__ptep, __entry); \ 499 flush_tlb_page(__vma, __addr); \ 500 } \ 501 __changed; \ 502 }) 503 #else 504 # define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __safely_writable) \ 505 ({ \ 506 int __changed = !pte_same(*(__ptep), __entry); \ 507 if (__changed) { \ 508 set_pte_at((__vma)->vm_mm, (__addr), __ptep, __entry); \ 509 flush_tlb_page(__vma, __addr); \ 510 } \ 511 __changed; \ 512 }) 513 #endif 514 # endif /* !__ASSEMBLY__ */ 515 516 /* 517 * Identity-mapped regions use a large page size. We'll call such large pages 518 * "granules". If you can think of a better name that's unambiguous, let me 519 * know... 520 */ 521 #if defined(CONFIG_IA64_GRANULE_64MB) 522 # define IA64_GRANULE_SHIFT _PAGE_SIZE_64M 523 #elif defined(CONFIG_IA64_GRANULE_16MB) 524 # define IA64_GRANULE_SHIFT _PAGE_SIZE_16M 525 #endif 526 #define IA64_GRANULE_SIZE (1 << IA64_GRANULE_SHIFT) 527 /* 528 * log2() of the page size we use to map the kernel image (IA64_TR_KERNEL): 529 */ 530 #define KERNEL_TR_PAGE_SHIFT _PAGE_SIZE_64M 531 #define KERNEL_TR_PAGE_SIZE (1 << KERNEL_TR_PAGE_SHIFT) 532 533 /* These tell get_user_pages() that the first gate page is accessible from user-level. */ 534 #define FIXADDR_USER_START GATE_ADDR 535 #ifdef HAVE_BUGGY_SEGREL 536 # define FIXADDR_USER_END (GATE_ADDR + 2*PAGE_SIZE) 537 #else 538 # define FIXADDR_USER_END (GATE_ADDR + 2*PERCPU_PAGE_SIZE) 539 #endif 540 541 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 542 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 543 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 544 #define __HAVE_ARCH_PTE_SAME 545 #define __HAVE_ARCH_PGD_OFFSET_GATE 546 547 548 #if CONFIG_PGTABLE_LEVELS == 3 549 #include <asm-generic/pgtable-nopud.h> 550 #endif 551 #include <asm-generic/pgtable-nop4d.h> 552 553 #endif /* _ASM_IA64_PGTABLE_H */ 554