1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_IA64_PGTABLE_H 3 #define _ASM_IA64_PGTABLE_H 4 5 /* 6 * This file contains the functions and defines necessary to modify and use 7 * the IA-64 page table tree. 8 * 9 * This hopefully works with any (fixed) IA-64 page-size, as defined 10 * in <asm/page.h>. 11 * 12 * Copyright (C) 1998-2005 Hewlett-Packard Co 13 * David Mosberger-Tang <davidm@hpl.hp.com> 14 */ 15 16 17 #include <asm/mman.h> 18 #include <asm/page.h> 19 #include <asm/processor.h> 20 #include <asm/types.h> 21 22 #define IA64_MAX_PHYS_BITS 50 /* max. number of physical address bits (architected) */ 23 24 /* 25 * First, define the various bits in a PTE. Note that the PTE format 26 * matches the VHPT short format, the firt doubleword of the VHPD long 27 * format, and the first doubleword of the TLB insertion format. 28 */ 29 #define _PAGE_P_BIT 0 30 #define _PAGE_A_BIT 5 31 #define _PAGE_D_BIT 6 32 33 #define _PAGE_P (1 << _PAGE_P_BIT) /* page present bit */ 34 #define _PAGE_MA_WB (0x0 << 2) /* write back memory attribute */ 35 #define _PAGE_MA_UC (0x4 << 2) /* uncacheable memory attribute */ 36 #define _PAGE_MA_UCE (0x5 << 2) /* UC exported attribute */ 37 #define _PAGE_MA_WC (0x6 << 2) /* write coalescing memory attribute */ 38 #define _PAGE_MA_NAT (0x7 << 2) /* not-a-thing attribute */ 39 #define _PAGE_MA_MASK (0x7 << 2) 40 #define _PAGE_PL_0 (0 << 7) /* privilege level 0 (kernel) */ 41 #define _PAGE_PL_1 (1 << 7) /* privilege level 1 (unused) */ 42 #define _PAGE_PL_2 (2 << 7) /* privilege level 2 (unused) */ 43 #define _PAGE_PL_3 (3 << 7) /* privilege level 3 (user) */ 44 #define _PAGE_PL_MASK (3 << 7) 45 #define _PAGE_AR_R (0 << 9) /* read only */ 46 #define _PAGE_AR_RX (1 << 9) /* read & execute */ 47 #define _PAGE_AR_RW (2 << 9) /* read & write */ 48 #define _PAGE_AR_RWX (3 << 9) /* read, write & execute */ 49 #define _PAGE_AR_R_RW (4 << 9) /* read / read & write */ 50 #define _PAGE_AR_RX_RWX (5 << 9) /* read & exec / read, write & exec */ 51 #define _PAGE_AR_RWX_RW (6 << 9) /* read, write & exec / read & write */ 52 #define _PAGE_AR_X_RX (7 << 9) /* exec & promote / read & exec */ 53 #define _PAGE_AR_MASK (7 << 9) 54 #define _PAGE_AR_SHIFT 9 55 #define _PAGE_A (1 << _PAGE_A_BIT) /* page accessed bit */ 56 #define _PAGE_D (1 << _PAGE_D_BIT) /* page dirty bit */ 57 #define _PAGE_PPN_MASK (((__IA64_UL(1) << IA64_MAX_PHYS_BITS) - 1) & ~0xfffUL) 58 #define _PAGE_ED (__IA64_UL(1) << 52) /* exception deferral */ 59 #define _PAGE_PROTNONE (__IA64_UL(1) << 63) 60 61 /* We borrow bit 7 to store the exclusive marker in swap PTEs. */ 62 #define _PAGE_SWP_EXCLUSIVE (1 << 7) 63 64 #define _PFN_MASK _PAGE_PPN_MASK 65 /* Mask of bits which may be changed by pte_modify(); the odd bits are there for _PAGE_PROTNONE */ 66 #define _PAGE_CHG_MASK (_PAGE_P | _PAGE_PROTNONE | _PAGE_PL_MASK | _PAGE_AR_MASK | _PAGE_ED) 67 68 #define _PAGE_SIZE_4K 12 69 #define _PAGE_SIZE_8K 13 70 #define _PAGE_SIZE_16K 14 71 #define _PAGE_SIZE_64K 16 72 #define _PAGE_SIZE_256K 18 73 #define _PAGE_SIZE_1M 20 74 #define _PAGE_SIZE_4M 22 75 #define _PAGE_SIZE_16M 24 76 #define _PAGE_SIZE_64M 26 77 #define _PAGE_SIZE_256M 28 78 #define _PAGE_SIZE_1G 30 79 #define _PAGE_SIZE_4G 32 80 81 #define __ACCESS_BITS _PAGE_ED | _PAGE_A | _PAGE_P | _PAGE_MA_WB 82 #define __DIRTY_BITS_NO_ED _PAGE_A | _PAGE_P | _PAGE_D | _PAGE_MA_WB 83 #define __DIRTY_BITS _PAGE_ED | __DIRTY_BITS_NO_ED 84 85 /* 86 * How many pointers will a page table level hold expressed in shift 87 */ 88 #define PTRS_PER_PTD_SHIFT (PAGE_SHIFT-3) 89 90 /* 91 * Definitions for fourth level: 92 */ 93 #define PTRS_PER_PTE (__IA64_UL(1) << (PTRS_PER_PTD_SHIFT)) 94 95 /* 96 * Definitions for third level: 97 * 98 * PMD_SHIFT determines the size of the area a third-level page table 99 * can map. 100 */ 101 #define PMD_SHIFT (PAGE_SHIFT + (PTRS_PER_PTD_SHIFT)) 102 #define PMD_SIZE (1UL << PMD_SHIFT) 103 #define PMD_MASK (~(PMD_SIZE-1)) 104 #define PTRS_PER_PMD (1UL << (PTRS_PER_PTD_SHIFT)) 105 106 #if CONFIG_PGTABLE_LEVELS == 4 107 /* 108 * Definitions for second level: 109 * 110 * PUD_SHIFT determines the size of the area a second-level page table 111 * can map. 112 */ 113 #define PUD_SHIFT (PMD_SHIFT + (PTRS_PER_PTD_SHIFT)) 114 #define PUD_SIZE (1UL << PUD_SHIFT) 115 #define PUD_MASK (~(PUD_SIZE-1)) 116 #define PTRS_PER_PUD (1UL << (PTRS_PER_PTD_SHIFT)) 117 #endif 118 119 /* 120 * Definitions for first level: 121 * 122 * PGDIR_SHIFT determines what a first-level page table entry can map. 123 */ 124 #if CONFIG_PGTABLE_LEVELS == 4 125 #define PGDIR_SHIFT (PUD_SHIFT + (PTRS_PER_PTD_SHIFT)) 126 #else 127 #define PGDIR_SHIFT (PMD_SHIFT + (PTRS_PER_PTD_SHIFT)) 128 #endif 129 #define PGDIR_SIZE (__IA64_UL(1) << PGDIR_SHIFT) 130 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 131 #define PTRS_PER_PGD_SHIFT PTRS_PER_PTD_SHIFT 132 #define PTRS_PER_PGD (1UL << PTRS_PER_PGD_SHIFT) 133 #define USER_PTRS_PER_PGD (5*PTRS_PER_PGD/8) /* regions 0-4 are user regions */ 134 135 /* 136 * All the normal masks have the "page accessed" bits on, as any time 137 * they are used, the page is accessed. They are cleared only by the 138 * page-out routines. 139 */ 140 #define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_A) 141 #define PAGE_SHARED __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RW) 142 #define PAGE_READONLY __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_R) 143 #define PAGE_COPY __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_R) 144 #define PAGE_COPY_EXEC __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX) 145 #define PAGE_GATE __pgprot(__ACCESS_BITS | _PAGE_PL_0 | _PAGE_AR_X_RX) 146 #define PAGE_KERNEL __pgprot(__DIRTY_BITS | _PAGE_PL_0 | _PAGE_AR_RWX) 147 #define PAGE_KERNELRX __pgprot(__ACCESS_BITS | _PAGE_PL_0 | _PAGE_AR_RX) 148 #define PAGE_KERNEL_UC __pgprot(__DIRTY_BITS | _PAGE_PL_0 | _PAGE_AR_RWX | \ 149 _PAGE_MA_UC) 150 151 # ifndef __ASSEMBLY__ 152 153 #include <linux/sched/mm.h> /* for mm_struct */ 154 #include <linux/bitops.h> 155 #include <asm/cacheflush.h> 156 #include <asm/mmu_context.h> 157 158 /* 159 * Next come the mappings that determine how mmap() protection bits 160 * (PROT_EXEC, PROT_READ, PROT_WRITE, PROT_NONE) get implemented. The 161 * _P version gets used for a private shared memory segment, the _S 162 * version gets used for a shared memory segment with MAP_SHARED on. 163 * In a private shared memory segment, we do a copy-on-write if a task 164 * attempts to write to the page. 165 */ 166 /* xwr */ 167 #define pgd_ERROR(e) printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e)) 168 #if CONFIG_PGTABLE_LEVELS == 4 169 #define pud_ERROR(e) printk("%s:%d: bad pud %016lx.\n", __FILE__, __LINE__, pud_val(e)) 170 #endif 171 #define pmd_ERROR(e) printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e)) 172 #define pte_ERROR(e) printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e)) 173 174 175 /* 176 * Some definitions to translate between mem_map, PTEs, and page addresses: 177 */ 178 179 180 /* Quick test to see if ADDR is a (potentially) valid physical address. */ 181 static inline long 182 ia64_phys_addr_valid (unsigned long addr) 183 { 184 return (addr & (local_cpu_data->unimpl_pa_mask)) == 0; 185 } 186 187 /* 188 * Now come the defines and routines to manage and access the three-level 189 * page table. 190 */ 191 192 193 #define VMALLOC_START (RGN_BASE(RGN_GATE) + 0x200000000UL) 194 #if defined(CONFIG_SPARSEMEM) && defined(CONFIG_SPARSEMEM_VMEMMAP) 195 /* SPARSEMEM_VMEMMAP uses half of vmalloc... */ 196 # define VMALLOC_END (RGN_BASE(RGN_GATE) + (1UL << (4*PAGE_SHIFT - 10))) 197 # define vmemmap ((struct page *)VMALLOC_END) 198 #else 199 # define VMALLOC_END (RGN_BASE(RGN_GATE) + (1UL << (4*PAGE_SHIFT - 9))) 200 #endif 201 202 /* fs/proc/kcore.c */ 203 #define kc_vaddr_to_offset(v) ((v) - RGN_BASE(RGN_GATE)) 204 #define kc_offset_to_vaddr(o) ((o) + RGN_BASE(RGN_GATE)) 205 206 #define RGN_MAP_SHIFT (PGDIR_SHIFT + PTRS_PER_PGD_SHIFT - 3) 207 #define RGN_MAP_LIMIT ((1UL << RGN_MAP_SHIFT) - PAGE_SIZE) /* per region addr limit */ 208 209 #define PFN_PTE_SHIFT PAGE_SHIFT 210 /* 211 * Conversion functions: convert page frame number (pfn) and a protection value to a page 212 * table entry (pte). 213 */ 214 #define pfn_pte(pfn, pgprot) \ 215 ({ pte_t __pte; pte_val(__pte) = ((pfn) << PAGE_SHIFT) | pgprot_val(pgprot); __pte; }) 216 217 /* Extract pfn from pte. */ 218 #define pte_pfn(_pte) ((pte_val(_pte) & _PFN_MASK) >> PAGE_SHIFT) 219 220 #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) 221 222 /* This takes a physical page address that is used by the remapping functions */ 223 #define mk_pte_phys(physpage, pgprot) \ 224 ({ pte_t __pte; pte_val(__pte) = physpage + pgprot_val(pgprot); __pte; }) 225 226 #define pte_modify(_pte, newprot) \ 227 (__pte((pte_val(_pte) & ~_PAGE_CHG_MASK) | (pgprot_val(newprot) & _PAGE_CHG_MASK))) 228 229 #define pte_none(pte) (!pte_val(pte)) 230 #define pte_present(pte) (pte_val(pte) & (_PAGE_P | _PAGE_PROTNONE)) 231 #define pte_clear(mm,addr,pte) (pte_val(*(pte)) = 0UL) 232 /* pte_page() returns the "struct page *" corresponding to the PTE: */ 233 #define pte_page(pte) virt_to_page(((pte_val(pte) & _PFN_MASK) + PAGE_OFFSET)) 234 235 #define pmd_none(pmd) (!pmd_val(pmd)) 236 #define pmd_bad(pmd) (!ia64_phys_addr_valid(pmd_val(pmd))) 237 #define pmd_present(pmd) (pmd_val(pmd) != 0UL) 238 #define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0UL) 239 #define pmd_page_vaddr(pmd) ((unsigned long) __va(pmd_val(pmd) & _PFN_MASK)) 240 #define pmd_pfn(pmd) ((pmd_val(pmd) & _PFN_MASK) >> PAGE_SHIFT) 241 #define pmd_page(pmd) virt_to_page((pmd_val(pmd) + PAGE_OFFSET)) 242 243 #define pud_none(pud) (!pud_val(pud)) 244 #define pud_bad(pud) (!ia64_phys_addr_valid(pud_val(pud))) 245 #define pud_present(pud) (pud_val(pud) != 0UL) 246 #define pud_clear(pudp) (pud_val(*(pudp)) = 0UL) 247 #define pud_pgtable(pud) ((pmd_t *) __va(pud_val(pud) & _PFN_MASK)) 248 #define pud_page(pud) virt_to_page((pud_val(pud) + PAGE_OFFSET)) 249 250 #if CONFIG_PGTABLE_LEVELS == 4 251 #define p4d_none(p4d) (!p4d_val(p4d)) 252 #define p4d_bad(p4d) (!ia64_phys_addr_valid(p4d_val(p4d))) 253 #define p4d_present(p4d) (p4d_val(p4d) != 0UL) 254 #define p4d_clear(p4dp) (p4d_val(*(p4dp)) = 0UL) 255 #define p4d_pgtable(p4d) ((pud_t *) __va(p4d_val(p4d) & _PFN_MASK)) 256 #define p4d_page(p4d) virt_to_page((p4d_val(p4d) + PAGE_OFFSET)) 257 #endif 258 259 /* 260 * The following have defined behavior only work if pte_present() is true. 261 */ 262 #define pte_write(pte) ((unsigned) (((pte_val(pte) & _PAGE_AR_MASK) >> _PAGE_AR_SHIFT) - 2) <= 4) 263 #define pte_exec(pte) ((pte_val(pte) & _PAGE_AR_RX) != 0) 264 #define pte_dirty(pte) ((pte_val(pte) & _PAGE_D) != 0) 265 #define pte_young(pte) ((pte_val(pte) & _PAGE_A) != 0) 266 267 /* 268 * Note: we convert AR_RWX to AR_RX and AR_RW to AR_R by clearing the 2nd bit in the 269 * access rights: 270 */ 271 #define pte_wrprotect(pte) (__pte(pte_val(pte) & ~_PAGE_AR_RW)) 272 #define pte_mkwrite_novma(pte) (__pte(pte_val(pte) | _PAGE_AR_RW)) 273 #define pte_mkold(pte) (__pte(pte_val(pte) & ~_PAGE_A)) 274 #define pte_mkyoung(pte) (__pte(pte_val(pte) | _PAGE_A)) 275 #define pte_mkclean(pte) (__pte(pte_val(pte) & ~_PAGE_D)) 276 #define pte_mkdirty(pte) (__pte(pte_val(pte) | _PAGE_D)) 277 #define pte_mkhuge(pte) (__pte(pte_val(pte))) 278 279 /* 280 * Because ia64's Icache and Dcache is not coherent (on a cpu), we need to 281 * sync icache and dcache when we insert *new* executable page. 282 * __ia64_sync_icache_dcache() check Pg_arch_1 bit and flush icache 283 * if necessary. 284 * 285 * set_pte() is also called by the kernel, but we can expect that the kernel 286 * flushes icache explicitly if necessary. 287 */ 288 #define pte_present_exec_user(pte)\ 289 ((pte_val(pte) & (_PAGE_P | _PAGE_PL_MASK | _PAGE_AR_RX)) == \ 290 (_PAGE_P | _PAGE_PL_3 | _PAGE_AR_RX)) 291 292 extern void __ia64_sync_icache_dcache(pte_t pteval); 293 static inline void set_pte(pte_t *ptep, pte_t pteval) 294 { 295 /* page is present && page is user && page is executable 296 * && (page swapin or new page or page migration 297 * || copy_on_write with page copying.) 298 */ 299 if (pte_present_exec_user(pteval) && 300 (!pte_present(*ptep) || 301 pte_pfn(*ptep) != pte_pfn(pteval))) 302 /* load_module() calles flush_icache_range() explicitly*/ 303 __ia64_sync_icache_dcache(pteval); 304 *ptep = pteval; 305 } 306 307 /* 308 * Make page protection values cacheable, uncacheable, or write- 309 * combining. Note that "protection" is really a misnomer here as the 310 * protection value contains the memory attribute bits, dirty bits, and 311 * various other bits as well. 312 */ 313 #define pgprot_cacheable(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_WB) 314 #define pgprot_noncached(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_UC) 315 #define pgprot_writecombine(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_WC) 316 317 struct file; 318 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 319 unsigned long size, pgprot_t vma_prot); 320 #define __HAVE_PHYS_MEM_ACCESS_PROT 321 322 static inline unsigned long 323 pgd_index (unsigned long address) 324 { 325 unsigned long region = address >> 61; 326 unsigned long l1index = (address >> PGDIR_SHIFT) & ((PTRS_PER_PGD >> 3) - 1); 327 328 return (region << (PAGE_SHIFT - 6)) | l1index; 329 } 330 #define pgd_index pgd_index 331 332 /* 333 * In the kernel's mapped region we know everything is in region number 5, so 334 * as an optimisation its PGD already points to the area for that region. 335 * However, this also means that we cannot use pgd_index() and we must 336 * never add the region here. 337 */ 338 #define pgd_offset_k(addr) \ 339 (init_mm.pgd + (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))) 340 341 /* Look up a pgd entry in the gate area. On IA-64, the gate-area 342 resides in the kernel-mapped segment, hence we use pgd_offset_k() 343 here. */ 344 #define pgd_offset_gate(mm, addr) pgd_offset_k(addr) 345 346 /* atomic versions of the some PTE manipulations: */ 347 348 static inline int 349 ptep_test_and_clear_young (struct vm_area_struct *vma, unsigned long addr, pte_t *ptep) 350 { 351 #ifdef CONFIG_SMP 352 if (!pte_young(*ptep)) 353 return 0; 354 return test_and_clear_bit(_PAGE_A_BIT, ptep); 355 #else 356 pte_t pte = *ptep; 357 if (!pte_young(pte)) 358 return 0; 359 set_pte_at(vma->vm_mm, addr, ptep, pte_mkold(pte)); 360 return 1; 361 #endif 362 } 363 364 static inline pte_t 365 ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 366 { 367 #ifdef CONFIG_SMP 368 return __pte(xchg((long *) ptep, 0)); 369 #else 370 pte_t pte = *ptep; 371 pte_clear(mm, addr, ptep); 372 return pte; 373 #endif 374 } 375 376 static inline void 377 ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 378 { 379 #ifdef CONFIG_SMP 380 unsigned long new, old; 381 382 do { 383 old = pte_val(*ptep); 384 new = pte_val(pte_wrprotect(__pte (old))); 385 } while (cmpxchg((unsigned long *) ptep, old, new) != old); 386 #else 387 pte_t old_pte = *ptep; 388 set_pte_at(mm, addr, ptep, pte_wrprotect(old_pte)); 389 #endif 390 } 391 392 static inline int 393 pte_same (pte_t a, pte_t b) 394 { 395 return pte_val(a) == pte_val(b); 396 } 397 398 #define update_mmu_cache_range(vmf, vma, address, ptep, nr) do { } while (0) 399 #define update_mmu_cache(vma, address, ptep) do { } while (0) 400 401 extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 402 extern void paging_init (void); 403 404 /* 405 * Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that 406 * are !pte_none() && !pte_present(). 407 * 408 * Note: The macros below rely on the fact that MAX_SWAPFILES_SHIFT <= number of 409 * bits in the swap-type field of the swap pte. It would be nice to 410 * enforce that, but we can't easily include <linux/swap.h> here. 411 * (Of course, better still would be to define MAX_SWAPFILES_SHIFT here...). 412 * 413 * Format of swap pte: 414 * bit 0 : present bit (must be zero) 415 * bits 1- 6: swap type 416 * bit 7 : exclusive marker 417 * bits 8-62: swap offset 418 * bit 63 : _PAGE_PROTNONE bit 419 */ 420 #define __swp_type(entry) (((entry).val >> 1) & 0x3f) 421 #define __swp_offset(entry) (((entry).val << 1) >> 9) 422 #define __swp_entry(type, offset) ((swp_entry_t) { ((type & 0x3f) << 1) | \ 423 ((long) (offset) << 8) }) 424 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 425 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 426 427 static inline int pte_swp_exclusive(pte_t pte) 428 { 429 return pte_val(pte) & _PAGE_SWP_EXCLUSIVE; 430 } 431 432 static inline pte_t pte_swp_mkexclusive(pte_t pte) 433 { 434 pte_val(pte) |= _PAGE_SWP_EXCLUSIVE; 435 return pte; 436 } 437 438 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 439 { 440 pte_val(pte) &= ~_PAGE_SWP_EXCLUSIVE; 441 return pte; 442 } 443 444 /* 445 * ZERO_PAGE is a global shared page that is always zero: used 446 * for zero-mapped memory areas etc.. 447 */ 448 extern unsigned long empty_zero_page[PAGE_SIZE/sizeof(unsigned long)]; 449 extern struct page *zero_page_memmap_ptr; 450 #define ZERO_PAGE(vaddr) (zero_page_memmap_ptr) 451 452 /* We provide our own get_unmapped_area to cope with VA holes for userland */ 453 #define HAVE_ARCH_UNMAPPED_AREA 454 455 #ifdef CONFIG_HUGETLB_PAGE 456 #define HUGETLB_PGDIR_SHIFT (HPAGE_SHIFT + 2*(PAGE_SHIFT-3)) 457 #define HUGETLB_PGDIR_SIZE (__IA64_UL(1) << HUGETLB_PGDIR_SHIFT) 458 #define HUGETLB_PGDIR_MASK (~(HUGETLB_PGDIR_SIZE-1)) 459 #endif 460 461 462 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 463 /* 464 * Update PTEP with ENTRY, which is guaranteed to be a less 465 * restrictive PTE. That is, ENTRY may have the ACCESSED, DIRTY, and 466 * WRITABLE bits turned on, when the value at PTEP did not. The 467 * WRITABLE bit may only be turned if SAFELY_WRITABLE is TRUE. 468 * 469 * SAFELY_WRITABLE is TRUE if we can update the value at PTEP without 470 * having to worry about races. On SMP machines, there are only two 471 * cases where this is true: 472 * 473 * (1) *PTEP has the PRESENT bit turned OFF 474 * (2) ENTRY has the DIRTY bit turned ON 475 * 476 * On ia64, we could implement this routine with a cmpxchg()-loop 477 * which ORs in the _PAGE_A/_PAGE_D bit if they're set in ENTRY. 478 * However, like on x86, we can get a more streamlined version by 479 * observing that it is OK to drop ACCESSED bit updates when 480 * SAFELY_WRITABLE is FALSE. Besides being rare, all that would do is 481 * result in an extra Access-bit fault, which would then turn on the 482 * ACCESSED bit in the low-level fault handler (iaccess_bit or 483 * daccess_bit in ivt.S). 484 */ 485 #ifdef CONFIG_SMP 486 # define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __safely_writable) \ 487 ({ \ 488 int __changed = !pte_same(*(__ptep), __entry); \ 489 if (__changed && __safely_writable) { \ 490 set_pte(__ptep, __entry); \ 491 flush_tlb_page(__vma, __addr); \ 492 } \ 493 __changed; \ 494 }) 495 #else 496 # define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __safely_writable) \ 497 ({ \ 498 int __changed = !pte_same(*(__ptep), __entry); \ 499 if (__changed) { \ 500 set_pte_at((__vma)->vm_mm, (__addr), __ptep, __entry); \ 501 flush_tlb_page(__vma, __addr); \ 502 } \ 503 __changed; \ 504 }) 505 #endif 506 # endif /* !__ASSEMBLY__ */ 507 508 /* 509 * Identity-mapped regions use a large page size. We'll call such large pages 510 * "granules". If you can think of a better name that's unambiguous, let me 511 * know... 512 */ 513 #if defined(CONFIG_IA64_GRANULE_64MB) 514 # define IA64_GRANULE_SHIFT _PAGE_SIZE_64M 515 #elif defined(CONFIG_IA64_GRANULE_16MB) 516 # define IA64_GRANULE_SHIFT _PAGE_SIZE_16M 517 #endif 518 #define IA64_GRANULE_SIZE (1 << IA64_GRANULE_SHIFT) 519 /* 520 * log2() of the page size we use to map the kernel image (IA64_TR_KERNEL): 521 */ 522 #define KERNEL_TR_PAGE_SHIFT _PAGE_SIZE_64M 523 #define KERNEL_TR_PAGE_SIZE (1 << KERNEL_TR_PAGE_SHIFT) 524 525 /* These tell get_user_pages() that the first gate page is accessible from user-level. */ 526 #define FIXADDR_USER_START GATE_ADDR 527 #ifdef HAVE_BUGGY_SEGREL 528 # define FIXADDR_USER_END (GATE_ADDR + 2*PAGE_SIZE) 529 #else 530 # define FIXADDR_USER_END (GATE_ADDR + 2*PERCPU_PAGE_SIZE) 531 #endif 532 533 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 534 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 535 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 536 #define __HAVE_ARCH_PTE_SAME 537 #define __HAVE_ARCH_PGD_OFFSET_GATE 538 539 540 #if CONFIG_PGTABLE_LEVELS == 3 541 #include <asm-generic/pgtable-nopud.h> 542 #endif 543 #include <asm-generic/pgtable-nop4d.h> 544 545 #endif /* _ASM_IA64_PGTABLE_H */ 546