1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_IA64_KREGS_H 3 #define _ASM_IA64_KREGS_H 4 5 /* 6 * Copyright (C) 2001-2002 Hewlett-Packard Co 7 * David Mosberger-Tang <davidm@hpl.hp.com> 8 */ 9 /* 10 * This file defines the kernel register usage convention used by Linux/ia64. 11 */ 12 13 /* 14 * Kernel registers: 15 */ 16 #define IA64_KR_IO_BASE 0 /* ar.k0: legacy I/O base address */ 17 #define IA64_KR_TSSD 1 /* ar.k1: IVE uses this as the TSSD */ 18 #define IA64_KR_PER_CPU_DATA 3 /* ar.k3: physical per-CPU base */ 19 #define IA64_KR_CURRENT_STACK 4 /* ar.k4: what's mapped in IA64_TR_CURRENT_STACK */ 20 #define IA64_KR_FPU_OWNER 5 /* ar.k5: fpu-owner (UP only, at the moment) */ 21 #define IA64_KR_CURRENT 6 /* ar.k6: "current" task pointer */ 22 #define IA64_KR_PT_BASE 7 /* ar.k7: page table base address (physical) */ 23 24 #define _IA64_KR_PASTE(x,y) x##y 25 #define _IA64_KR_PREFIX(n) _IA64_KR_PASTE(ar.k, n) 26 #define IA64_KR(n) _IA64_KR_PREFIX(IA64_KR_##n) 27 28 /* 29 * Translation registers: 30 */ 31 #define IA64_TR_KERNEL 0 /* itr0, dtr0: maps kernel image (code & data) */ 32 #define IA64_TR_PALCODE 1 /* itr1: maps PALcode as required by EFI */ 33 #define IA64_TR_CURRENT_STACK 1 /* dtr1: maps kernel's memory- & register-stacks */ 34 35 #define IA64_TR_ALLOC_BASE 2 /* itr&dtr: Base of dynamic TR resource*/ 36 #define IA64_TR_ALLOC_MAX 64 /* Max number for dynamic use*/ 37 38 /* Processor status register bits: */ 39 #define IA64_PSR_BE_BIT 1 40 #define IA64_PSR_UP_BIT 2 41 #define IA64_PSR_AC_BIT 3 42 #define IA64_PSR_MFL_BIT 4 43 #define IA64_PSR_MFH_BIT 5 44 #define IA64_PSR_IC_BIT 13 45 #define IA64_PSR_I_BIT 14 46 #define IA64_PSR_PK_BIT 15 47 #define IA64_PSR_DT_BIT 17 48 #define IA64_PSR_DFL_BIT 18 49 #define IA64_PSR_DFH_BIT 19 50 #define IA64_PSR_SP_BIT 20 51 #define IA64_PSR_PP_BIT 21 52 #define IA64_PSR_DI_BIT 22 53 #define IA64_PSR_SI_BIT 23 54 #define IA64_PSR_DB_BIT 24 55 #define IA64_PSR_LP_BIT 25 56 #define IA64_PSR_TB_BIT 26 57 #define IA64_PSR_RT_BIT 27 58 /* The following are not affected by save_flags()/restore_flags(): */ 59 #define IA64_PSR_CPL0_BIT 32 60 #define IA64_PSR_CPL1_BIT 33 61 #define IA64_PSR_IS_BIT 34 62 #define IA64_PSR_MC_BIT 35 63 #define IA64_PSR_IT_BIT 36 64 #define IA64_PSR_ID_BIT 37 65 #define IA64_PSR_DA_BIT 38 66 #define IA64_PSR_DD_BIT 39 67 #define IA64_PSR_SS_BIT 40 68 #define IA64_PSR_RI_BIT 41 69 #define IA64_PSR_ED_BIT 43 70 #define IA64_PSR_BN_BIT 44 71 #define IA64_PSR_IA_BIT 45 72 73 /* A mask of PSR bits that we generally don't want to inherit across a clone2() or an 74 execve(). Only list flags here that need to be cleared/set for BOTH clone2() and 75 execve(). */ 76 #define IA64_PSR_BITS_TO_CLEAR (IA64_PSR_MFL | IA64_PSR_MFH | IA64_PSR_DB | IA64_PSR_LP | \ 77 IA64_PSR_TB | IA64_PSR_ID | IA64_PSR_DA | IA64_PSR_DD | \ 78 IA64_PSR_SS | IA64_PSR_ED | IA64_PSR_IA) 79 #define IA64_PSR_BITS_TO_SET (IA64_PSR_DFH | IA64_PSR_SP) 80 81 #define IA64_PSR_BE (__IA64_UL(1) << IA64_PSR_BE_BIT) 82 #define IA64_PSR_UP (__IA64_UL(1) << IA64_PSR_UP_BIT) 83 #define IA64_PSR_AC (__IA64_UL(1) << IA64_PSR_AC_BIT) 84 #define IA64_PSR_MFL (__IA64_UL(1) << IA64_PSR_MFL_BIT) 85 #define IA64_PSR_MFH (__IA64_UL(1) << IA64_PSR_MFH_BIT) 86 #define IA64_PSR_IC (__IA64_UL(1) << IA64_PSR_IC_BIT) 87 #define IA64_PSR_I (__IA64_UL(1) << IA64_PSR_I_BIT) 88 #define IA64_PSR_PK (__IA64_UL(1) << IA64_PSR_PK_BIT) 89 #define IA64_PSR_DT (__IA64_UL(1) << IA64_PSR_DT_BIT) 90 #define IA64_PSR_DFL (__IA64_UL(1) << IA64_PSR_DFL_BIT) 91 #define IA64_PSR_DFH (__IA64_UL(1) << IA64_PSR_DFH_BIT) 92 #define IA64_PSR_SP (__IA64_UL(1) << IA64_PSR_SP_BIT) 93 #define IA64_PSR_PP (__IA64_UL(1) << IA64_PSR_PP_BIT) 94 #define IA64_PSR_DI (__IA64_UL(1) << IA64_PSR_DI_BIT) 95 #define IA64_PSR_SI (__IA64_UL(1) << IA64_PSR_SI_BIT) 96 #define IA64_PSR_DB (__IA64_UL(1) << IA64_PSR_DB_BIT) 97 #define IA64_PSR_LP (__IA64_UL(1) << IA64_PSR_LP_BIT) 98 #define IA64_PSR_TB (__IA64_UL(1) << IA64_PSR_TB_BIT) 99 #define IA64_PSR_RT (__IA64_UL(1) << IA64_PSR_RT_BIT) 100 /* The following are not affected by save_flags()/restore_flags(): */ 101 #define IA64_PSR_CPL (__IA64_UL(3) << IA64_PSR_CPL0_BIT) 102 #define IA64_PSR_IS (__IA64_UL(1) << IA64_PSR_IS_BIT) 103 #define IA64_PSR_MC (__IA64_UL(1) << IA64_PSR_MC_BIT) 104 #define IA64_PSR_IT (__IA64_UL(1) << IA64_PSR_IT_BIT) 105 #define IA64_PSR_ID (__IA64_UL(1) << IA64_PSR_ID_BIT) 106 #define IA64_PSR_DA (__IA64_UL(1) << IA64_PSR_DA_BIT) 107 #define IA64_PSR_DD (__IA64_UL(1) << IA64_PSR_DD_BIT) 108 #define IA64_PSR_SS (__IA64_UL(1) << IA64_PSR_SS_BIT) 109 #define IA64_PSR_RI (__IA64_UL(3) << IA64_PSR_RI_BIT) 110 #define IA64_PSR_ED (__IA64_UL(1) << IA64_PSR_ED_BIT) 111 #define IA64_PSR_BN (__IA64_UL(1) << IA64_PSR_BN_BIT) 112 #define IA64_PSR_IA (__IA64_UL(1) << IA64_PSR_IA_BIT) 113 114 /* User mask bits: */ 115 #define IA64_PSR_UM (IA64_PSR_BE | IA64_PSR_UP | IA64_PSR_AC | IA64_PSR_MFL | IA64_PSR_MFH) 116 117 /* Default Control Register */ 118 #define IA64_DCR_PP_BIT 0 /* privileged performance monitor default */ 119 #define IA64_DCR_BE_BIT 1 /* big-endian default */ 120 #define IA64_DCR_LC_BIT 2 /* ia32 lock-check enable */ 121 #define IA64_DCR_DM_BIT 8 /* defer TLB miss faults */ 122 #define IA64_DCR_DP_BIT 9 /* defer page-not-present faults */ 123 #define IA64_DCR_DK_BIT 10 /* defer key miss faults */ 124 #define IA64_DCR_DX_BIT 11 /* defer key permission faults */ 125 #define IA64_DCR_DR_BIT 12 /* defer access right faults */ 126 #define IA64_DCR_DA_BIT 13 /* defer access bit faults */ 127 #define IA64_DCR_DD_BIT 14 /* defer debug faults */ 128 129 #define IA64_DCR_PP (__IA64_UL(1) << IA64_DCR_PP_BIT) 130 #define IA64_DCR_BE (__IA64_UL(1) << IA64_DCR_BE_BIT) 131 #define IA64_DCR_LC (__IA64_UL(1) << IA64_DCR_LC_BIT) 132 #define IA64_DCR_DM (__IA64_UL(1) << IA64_DCR_DM_BIT) 133 #define IA64_DCR_DP (__IA64_UL(1) << IA64_DCR_DP_BIT) 134 #define IA64_DCR_DK (__IA64_UL(1) << IA64_DCR_DK_BIT) 135 #define IA64_DCR_DX (__IA64_UL(1) << IA64_DCR_DX_BIT) 136 #define IA64_DCR_DR (__IA64_UL(1) << IA64_DCR_DR_BIT) 137 #define IA64_DCR_DA (__IA64_UL(1) << IA64_DCR_DA_BIT) 138 #define IA64_DCR_DD (__IA64_UL(1) << IA64_DCR_DD_BIT) 139 140 /* Interrupt Status Register */ 141 #define IA64_ISR_X_BIT 32 /* execute access */ 142 #define IA64_ISR_W_BIT 33 /* write access */ 143 #define IA64_ISR_R_BIT 34 /* read access */ 144 #define IA64_ISR_NA_BIT 35 /* non-access */ 145 #define IA64_ISR_SP_BIT 36 /* speculative load exception */ 146 #define IA64_ISR_RS_BIT 37 /* mandatory register-stack exception */ 147 #define IA64_ISR_IR_BIT 38 /* invalid register frame exception */ 148 #define IA64_ISR_CODE_MASK 0xf 149 150 #define IA64_ISR_X (__IA64_UL(1) << IA64_ISR_X_BIT) 151 #define IA64_ISR_W (__IA64_UL(1) << IA64_ISR_W_BIT) 152 #define IA64_ISR_R (__IA64_UL(1) << IA64_ISR_R_BIT) 153 #define IA64_ISR_NA (__IA64_UL(1) << IA64_ISR_NA_BIT) 154 #define IA64_ISR_SP (__IA64_UL(1) << IA64_ISR_SP_BIT) 155 #define IA64_ISR_RS (__IA64_UL(1) << IA64_ISR_RS_BIT) 156 #define IA64_ISR_IR (__IA64_UL(1) << IA64_ISR_IR_BIT) 157 158 /* ISR code field for non-access instructions */ 159 #define IA64_ISR_CODE_TPA 0 160 #define IA64_ISR_CODE_FC 1 161 #define IA64_ISR_CODE_PROBE 2 162 #define IA64_ISR_CODE_TAK 3 163 #define IA64_ISR_CODE_LFETCH 4 164 #define IA64_ISR_CODE_PROBEF 5 165 166 #endif /* _ASM_IA64_kREGS_H */ 167