1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __ASM_IA64_IOSAPIC_H 3 #define __ASM_IA64_IOSAPIC_H 4 5 #define IOSAPIC_REG_SELECT 0x0 6 #define IOSAPIC_WINDOW 0x10 7 #define IOSAPIC_EOI 0x40 8 9 #define IOSAPIC_VERSION 0x1 10 11 /* 12 * Redirection table entry 13 */ 14 #define IOSAPIC_RTE_LOW(i) (0x10+i*2) 15 #define IOSAPIC_RTE_HIGH(i) (0x11+i*2) 16 17 #define IOSAPIC_DEST_SHIFT 16 18 19 /* 20 * Delivery mode 21 */ 22 #define IOSAPIC_DELIVERY_SHIFT 8 23 #define IOSAPIC_FIXED 0x0 24 #define IOSAPIC_LOWEST_PRIORITY 0x1 25 #define IOSAPIC_PMI 0x2 26 #define IOSAPIC_NMI 0x4 27 #define IOSAPIC_INIT 0x5 28 #define IOSAPIC_EXTINT 0x7 29 30 /* 31 * Interrupt polarity 32 */ 33 #define IOSAPIC_POLARITY_SHIFT 13 34 #define IOSAPIC_POL_HIGH 0 35 #define IOSAPIC_POL_LOW 1 36 37 /* 38 * Trigger mode 39 */ 40 #define IOSAPIC_TRIGGER_SHIFT 15 41 #define IOSAPIC_EDGE 0 42 #define IOSAPIC_LEVEL 1 43 44 /* 45 * Mask bit 46 */ 47 48 #define IOSAPIC_MASK_SHIFT 16 49 #define IOSAPIC_MASK (1<<IOSAPIC_MASK_SHIFT) 50 51 #define IOSAPIC_VECTOR_MASK 0xffffff00 52 53 #ifndef __ASSEMBLY__ 54 55 #ifdef CONFIG_IOSAPIC 56 57 #define NR_IOSAPICS 256 58 59 #define iosapic_pcat_compat_init ia64_native_iosapic_pcat_compat_init 60 #define __iosapic_read __ia64_native_iosapic_read 61 #define __iosapic_write __ia64_native_iosapic_write 62 #define iosapic_get_irq_chip ia64_native_iosapic_get_irq_chip 63 64 extern void __init ia64_native_iosapic_pcat_compat_init(void); 65 extern struct irq_chip *ia64_native_iosapic_get_irq_chip(unsigned long trigger); 66 67 static inline unsigned int 68 __ia64_native_iosapic_read(char __iomem *iosapic, unsigned int reg) 69 { 70 writel(reg, iosapic + IOSAPIC_REG_SELECT); 71 return readl(iosapic + IOSAPIC_WINDOW); 72 } 73 74 static inline void 75 __ia64_native_iosapic_write(char __iomem *iosapic, unsigned int reg, u32 val) 76 { 77 writel(reg, iosapic + IOSAPIC_REG_SELECT); 78 writel(val, iosapic + IOSAPIC_WINDOW); 79 } 80 81 static inline void iosapic_eoi(char __iomem *iosapic, u32 vector) 82 { 83 writel(vector, iosapic + IOSAPIC_EOI); 84 } 85 86 extern void __init iosapic_system_init (int pcat_compat); 87 extern int iosapic_init (unsigned long address, unsigned int gsi_base); 88 extern int iosapic_remove (unsigned int gsi_base); 89 extern int gsi_to_irq (unsigned int gsi); 90 extern int iosapic_register_intr (unsigned int gsi, unsigned long polarity, 91 unsigned long trigger); 92 extern void iosapic_unregister_intr (unsigned int irq); 93 extern void iosapic_override_isa_irq (unsigned int isa_irq, unsigned int gsi, 94 unsigned long polarity, 95 unsigned long trigger); 96 extern int __init iosapic_register_platform_intr (u32 int_type, 97 unsigned int gsi, 98 int pmi_vector, 99 u16 eid, u16 id, 100 unsigned long polarity, 101 unsigned long trigger); 102 103 #ifdef CONFIG_NUMA 104 extern void map_iosapic_to_node (unsigned int, int); 105 #endif 106 #else 107 #define iosapic_system_init(pcat_compat) do { } while (0) 108 #define iosapic_init(address,gsi_base) (-EINVAL) 109 #define iosapic_remove(gsi_base) (-ENODEV) 110 #define iosapic_register_intr(gsi,polarity,trigger) (gsi) 111 #define iosapic_unregister_intr(irq) do { } while (0) 112 #define iosapic_override_isa_irq(isa_irq,gsi,polarity,trigger) do { } while (0) 113 #define iosapic_register_platform_intr(type,gsi,pmi,eid,id, \ 114 polarity,trigger) (gsi) 115 #endif 116 117 # endif /* !__ASSEMBLY__ */ 118 #endif /* __ASM_IA64_IOSAPIC_H */ 119