1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_IA64_IO_H 3 #define _ASM_IA64_IO_H 4 5 /* 6 * This file contains the definitions for the emulated IO instructions 7 * inb/inw/inl/outb/outw/outl and the "string versions" of the same 8 * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing" 9 * versions of the single-IO instructions (inb_p/inw_p/..). 10 * 11 * This file is not meant to be obfuscating: it's just complicated to 12 * (a) handle it all in a way that makes gcc able to optimize it as 13 * well as possible and (b) trying to avoid writing the same thing 14 * over and over again with slight variations and possibly making a 15 * mistake somewhere. 16 * 17 * Copyright (C) 1998-2003 Hewlett-Packard Co 18 * David Mosberger-Tang <davidm@hpl.hp.com> 19 * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com> 20 * Copyright (C) 1999 Don Dugger <don.dugger@intel.com> 21 */ 22 23 #include <asm/unaligned.h> 24 #include <asm/early_ioremap.h> 25 26 /* We don't use IO slowdowns on the ia64, but.. */ 27 #define __SLOW_DOWN_IO do { } while (0) 28 #define SLOW_DOWN_IO do { } while (0) 29 30 #define __IA64_UNCACHED_OFFSET RGN_BASE(RGN_UNCACHED) 31 32 /* 33 * The legacy I/O space defined by the ia64 architecture supports only 65536 ports, but 34 * large machines may have multiple other I/O spaces so we can't place any a priori limit 35 * on IO_SPACE_LIMIT. These additional spaces are described in ACPI. 36 */ 37 #define IO_SPACE_LIMIT 0xffffffffffffffffUL 38 39 #define MAX_IO_SPACES_BITS 8 40 #define MAX_IO_SPACES (1UL << MAX_IO_SPACES_BITS) 41 #define IO_SPACE_BITS 24 42 #define IO_SPACE_SIZE (1UL << IO_SPACE_BITS) 43 44 #define IO_SPACE_NR(port) ((port) >> IO_SPACE_BITS) 45 #define IO_SPACE_BASE(space) ((space) << IO_SPACE_BITS) 46 #define IO_SPACE_PORT(port) ((port) & (IO_SPACE_SIZE - 1)) 47 48 #define IO_SPACE_SPARSE_ENCODING(p) ((((p) >> 2) << 12) | ((p) & 0xfff)) 49 50 struct io_space { 51 unsigned long mmio_base; /* base in MMIO space */ 52 int sparse; 53 }; 54 55 extern struct io_space io_space[]; 56 extern unsigned int num_io_spaces; 57 58 # ifdef __KERNEL__ 59 60 /* 61 * All MMIO iomem cookies are in region 6; anything less is a PIO cookie: 62 * 0xCxxxxxxxxxxxxxxx MMIO cookie (return from ioremap) 63 * 0x000000001SPPPPPP PIO cookie (S=space number, P..P=port) 64 * 65 * ioread/writeX() uses the leading 1 in PIO cookies (PIO_OFFSET) to catch 66 * code that uses bare port numbers without the prerequisite pci_iomap(). 67 */ 68 #define PIO_OFFSET (1UL << (MAX_IO_SPACES_BITS + IO_SPACE_BITS)) 69 #define PIO_MASK (PIO_OFFSET - 1) 70 #define PIO_RESERVED __IA64_UNCACHED_OFFSET 71 #define HAVE_ARCH_PIO_SIZE 72 73 #include <asm/intrinsics.h> 74 #include <asm/machvec.h> 75 #include <asm/page.h> 76 #include <asm-generic/iomap.h> 77 78 /* 79 * Change virtual addresses to physical addresses and vv. 80 */ 81 static inline unsigned long 82 virt_to_phys (volatile void *address) 83 { 84 return (unsigned long) address - PAGE_OFFSET; 85 } 86 #define virt_to_phys virt_to_phys 87 88 static inline void* 89 phys_to_virt (unsigned long address) 90 { 91 return (void *) (address + PAGE_OFFSET); 92 } 93 #define phys_to_virt phys_to_virt 94 95 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE 96 extern u64 kern_mem_attribute (unsigned long phys_addr, unsigned long size); 97 extern int valid_phys_addr_range (phys_addr_t addr, size_t count); /* efi.c */ 98 extern int valid_mmap_phys_addr_range (unsigned long pfn, size_t count); 99 100 /* 101 * The following two macros are deprecated and scheduled for removal. 102 * Please use the PCI-DMA interface defined in <asm/pci.h> instead. 103 */ 104 #define bus_to_virt phys_to_virt 105 #define virt_to_bus virt_to_phys 106 #define page_to_bus page_to_phys 107 108 # endif /* KERNEL */ 109 110 /* 111 * Memory fence w/accept. This should never be used in code that is 112 * not IA-64 specific. 113 */ 114 #define __ia64_mf_a() ia64_mfa() 115 116 static inline void* 117 __ia64_mk_io_addr (unsigned long port) 118 { 119 struct io_space *space; 120 unsigned long offset; 121 122 space = &io_space[IO_SPACE_NR(port)]; 123 port = IO_SPACE_PORT(port); 124 if (space->sparse) 125 offset = IO_SPACE_SPARSE_ENCODING(port); 126 else 127 offset = port; 128 129 return (void *) (space->mmio_base | offset); 130 } 131 132 #define __ia64_inb ___ia64_inb 133 #define __ia64_inw ___ia64_inw 134 #define __ia64_inl ___ia64_inl 135 #define __ia64_outb ___ia64_outb 136 #define __ia64_outw ___ia64_outw 137 #define __ia64_outl ___ia64_outl 138 #define __ia64_readb ___ia64_readb 139 #define __ia64_readw ___ia64_readw 140 #define __ia64_readl ___ia64_readl 141 #define __ia64_readq ___ia64_readq 142 #define __ia64_readb_relaxed ___ia64_readb 143 #define __ia64_readw_relaxed ___ia64_readw 144 #define __ia64_readl_relaxed ___ia64_readl 145 #define __ia64_readq_relaxed ___ia64_readq 146 #define __ia64_writeb ___ia64_writeb 147 #define __ia64_writew ___ia64_writew 148 #define __ia64_writel ___ia64_writel 149 #define __ia64_writeq ___ia64_writeq 150 151 /* 152 * For the in/out routines, we need to do "mf.a" _after_ doing the I/O access to ensure 153 * that the access has completed before executing other I/O accesses. Since we're doing 154 * the accesses through an uncachable (UC) translation, the CPU will execute them in 155 * program order. However, we still need to tell the compiler not to shuffle them around 156 * during optimization, which is why we use "volatile" pointers. 157 */ 158 159 static inline unsigned int 160 ___ia64_inb (unsigned long port) 161 { 162 volatile unsigned char *addr = __ia64_mk_io_addr(port); 163 unsigned char ret; 164 165 ret = *addr; 166 __ia64_mf_a(); 167 return ret; 168 } 169 170 static inline unsigned int 171 ___ia64_inw (unsigned long port) 172 { 173 volatile unsigned short *addr = __ia64_mk_io_addr(port); 174 unsigned short ret; 175 176 ret = *addr; 177 __ia64_mf_a(); 178 return ret; 179 } 180 181 static inline unsigned int 182 ___ia64_inl (unsigned long port) 183 { 184 volatile unsigned int *addr = __ia64_mk_io_addr(port); 185 unsigned int ret; 186 187 ret = *addr; 188 __ia64_mf_a(); 189 return ret; 190 } 191 192 static inline void 193 ___ia64_outb (unsigned char val, unsigned long port) 194 { 195 volatile unsigned char *addr = __ia64_mk_io_addr(port); 196 197 *addr = val; 198 __ia64_mf_a(); 199 } 200 201 static inline void 202 ___ia64_outw (unsigned short val, unsigned long port) 203 { 204 volatile unsigned short *addr = __ia64_mk_io_addr(port); 205 206 *addr = val; 207 __ia64_mf_a(); 208 } 209 210 static inline void 211 ___ia64_outl (unsigned int val, unsigned long port) 212 { 213 volatile unsigned int *addr = __ia64_mk_io_addr(port); 214 215 *addr = val; 216 __ia64_mf_a(); 217 } 218 219 static inline void 220 __insb (unsigned long port, void *dst, unsigned long count) 221 { 222 unsigned char *dp = dst; 223 224 while (count--) 225 *dp++ = platform_inb(port); 226 } 227 228 static inline void 229 __insw (unsigned long port, void *dst, unsigned long count) 230 { 231 unsigned short *dp = dst; 232 233 while (count--) 234 put_unaligned(platform_inw(port), dp++); 235 } 236 237 static inline void 238 __insl (unsigned long port, void *dst, unsigned long count) 239 { 240 unsigned int *dp = dst; 241 242 while (count--) 243 put_unaligned(platform_inl(port), dp++); 244 } 245 246 static inline void 247 __outsb (unsigned long port, const void *src, unsigned long count) 248 { 249 const unsigned char *sp = src; 250 251 while (count--) 252 platform_outb(*sp++, port); 253 } 254 255 static inline void 256 __outsw (unsigned long port, const void *src, unsigned long count) 257 { 258 const unsigned short *sp = src; 259 260 while (count--) 261 platform_outw(get_unaligned(sp++), port); 262 } 263 264 static inline void 265 __outsl (unsigned long port, const void *src, unsigned long count) 266 { 267 const unsigned int *sp = src; 268 269 while (count--) 270 platform_outl(get_unaligned(sp++), port); 271 } 272 273 /* 274 * Unfortunately, some platforms are broken and do not follow the IA-64 architecture 275 * specification regarding legacy I/O support. Thus, we have to make these operations 276 * platform dependent... 277 */ 278 #define __inb platform_inb 279 #define __inw platform_inw 280 #define __inl platform_inl 281 #define __outb platform_outb 282 #define __outw platform_outw 283 #define __outl platform_outl 284 285 #define inb(p) __inb(p) 286 #define inw(p) __inw(p) 287 #define inl(p) __inl(p) 288 #define insb(p,d,c) __insb(p,d,c) 289 #define insw(p,d,c) __insw(p,d,c) 290 #define insl(p,d,c) __insl(p,d,c) 291 #define outb(v,p) __outb(v,p) 292 #define outw(v,p) __outw(v,p) 293 #define outl(v,p) __outl(v,p) 294 #define outsb(p,s,c) __outsb(p,s,c) 295 #define outsw(p,s,c) __outsw(p,s,c) 296 #define outsl(p,s,c) __outsl(p,s,c) 297 298 /* 299 * The address passed to these functions are ioremap()ped already. 300 * 301 * We need these to be machine vectors since some platforms don't provide 302 * DMA coherence via PIO reads (PCI drivers and the spec imply that this is 303 * a good idea). Writes are ok though for all existing ia64 platforms (and 304 * hopefully it'll stay that way). 305 */ 306 static inline unsigned char 307 ___ia64_readb (const volatile void __iomem *addr) 308 { 309 return *(volatile unsigned char __force *)addr; 310 } 311 312 static inline unsigned short 313 ___ia64_readw (const volatile void __iomem *addr) 314 { 315 return *(volatile unsigned short __force *)addr; 316 } 317 318 static inline unsigned int 319 ___ia64_readl (const volatile void __iomem *addr) 320 { 321 return *(volatile unsigned int __force *) addr; 322 } 323 324 static inline unsigned long 325 ___ia64_readq (const volatile void __iomem *addr) 326 { 327 return *(volatile unsigned long __force *) addr; 328 } 329 330 static inline void 331 __writeb (unsigned char val, volatile void __iomem *addr) 332 { 333 *(volatile unsigned char __force *) addr = val; 334 } 335 336 static inline void 337 __writew (unsigned short val, volatile void __iomem *addr) 338 { 339 *(volatile unsigned short __force *) addr = val; 340 } 341 342 static inline void 343 __writel (unsigned int val, volatile void __iomem *addr) 344 { 345 *(volatile unsigned int __force *) addr = val; 346 } 347 348 static inline void 349 __writeq (unsigned long val, volatile void __iomem *addr) 350 { 351 *(volatile unsigned long __force *) addr = val; 352 } 353 354 #define __readb platform_readb 355 #define __readw platform_readw 356 #define __readl platform_readl 357 #define __readq platform_readq 358 #define __readb_relaxed platform_readb_relaxed 359 #define __readw_relaxed platform_readw_relaxed 360 #define __readl_relaxed platform_readl_relaxed 361 #define __readq_relaxed platform_readq_relaxed 362 363 #define readb(a) __readb((a)) 364 #define readw(a) __readw((a)) 365 #define readl(a) __readl((a)) 366 #define readq(a) __readq((a)) 367 #define readb_relaxed(a) __readb_relaxed((a)) 368 #define readw_relaxed(a) __readw_relaxed((a)) 369 #define readl_relaxed(a) __readl_relaxed((a)) 370 #define readq_relaxed(a) __readq_relaxed((a)) 371 #define __raw_readb readb 372 #define __raw_readw readw 373 #define __raw_readl readl 374 #define __raw_readq readq 375 #define __raw_readb_relaxed readb_relaxed 376 #define __raw_readw_relaxed readw_relaxed 377 #define __raw_readl_relaxed readl_relaxed 378 #define __raw_readq_relaxed readq_relaxed 379 #define writeb(v,a) __writeb((v), (a)) 380 #define writew(v,a) __writew((v), (a)) 381 #define writel(v,a) __writel((v), (a)) 382 #define writeq(v,a) __writeq((v), (a)) 383 #define writeb_relaxed(v,a) __writeb((v), (a)) 384 #define writew_relaxed(v,a) __writew((v), (a)) 385 #define writel_relaxed(v,a) __writel((v), (a)) 386 #define writeq_relaxed(v,a) __writeq((v), (a)) 387 #define __raw_writeb writeb 388 #define __raw_writew writew 389 #define __raw_writel writel 390 #define __raw_writeq writeq 391 392 #ifndef inb_p 393 # define inb_p inb 394 #endif 395 #ifndef inw_p 396 # define inw_p inw 397 #endif 398 #ifndef inl_p 399 # define inl_p inl 400 #endif 401 402 #ifndef outb_p 403 # define outb_p outb 404 #endif 405 #ifndef outw_p 406 # define outw_p outw 407 #endif 408 #ifndef outl_p 409 # define outl_p outl 410 #endif 411 412 # ifdef __KERNEL__ 413 414 extern void __iomem * ioremap(unsigned long offset, unsigned long size); 415 extern void __iomem * ioremap_nocache (unsigned long offset, unsigned long size); 416 extern void iounmap (volatile void __iomem *addr); 417 static inline void __iomem * ioremap_cache (unsigned long phys_addr, unsigned long size) 418 { 419 return ioremap(phys_addr, size); 420 } 421 #define ioremap ioremap 422 #define ioremap_nocache ioremap_nocache 423 #define ioremap_cache ioremap_cache 424 #define ioremap_uc ioremap_nocache 425 #define iounmap iounmap 426 427 /* 428 * String version of IO memory access ops: 429 */ 430 extern void memcpy_fromio(void *dst, const volatile void __iomem *src, long n); 431 extern void memcpy_toio(volatile void __iomem *dst, const void *src, long n); 432 extern void memset_io(volatile void __iomem *s, int c, long n); 433 434 #define memcpy_fromio memcpy_fromio 435 #define memcpy_toio memcpy_toio 436 #define memset_io memset_io 437 #define xlate_dev_kmem_ptr xlate_dev_kmem_ptr 438 #define xlate_dev_mem_ptr xlate_dev_mem_ptr 439 #include <asm-generic/io.h> 440 #undef PCI_IOBASE 441 442 # endif /* __KERNEL__ */ 443 444 #endif /* _ASM_IA64_IO_H */ 445