1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_IA64_HW_IRQ_H 3 #define _ASM_IA64_HW_IRQ_H 4 5 /* 6 * Copyright (C) 2001-2003 Hewlett-Packard Co 7 * David Mosberger-Tang <davidm@hpl.hp.com> 8 */ 9 10 #include <linux/interrupt.h> 11 #include <linux/sched.h> 12 #include <linux/types.h> 13 #include <linux/profile.h> 14 15 #include <asm/machvec.h> 16 #include <asm/ptrace.h> 17 #include <asm/smp.h> 18 19 typedef u8 ia64_vector; 20 21 /* 22 * 0 special 23 * 24 * 1,3-14 are reserved from firmware 25 * 26 * 16-255 (vectored external interrupts) are available 27 * 28 * 15 spurious interrupt (see IVR) 29 * 30 * 16 lowest priority, 255 highest priority 31 * 32 * 15 classes of 16 interrupts each. 33 */ 34 #define IA64_MIN_VECTORED_IRQ 16 35 #define IA64_MAX_VECTORED_IRQ 255 36 #define IA64_NUM_VECTORS 256 37 38 #define AUTO_ASSIGN -1 39 40 #define IA64_SPURIOUS_INT_VECTOR 0x0f 41 42 /* 43 * Vectors 0x10-0x1f are used for low priority interrupts, e.g. CMCI. 44 */ 45 #define IA64_CPEP_VECTOR 0x1c /* corrected platform error polling vector */ 46 #define IA64_CMCP_VECTOR 0x1d /* corrected machine-check polling vector */ 47 #define IA64_CPE_VECTOR 0x1e /* corrected platform error interrupt vector */ 48 #define IA64_CMC_VECTOR 0x1f /* corrected machine-check interrupt vector */ 49 /* 50 * Vectors 0x20-0x2f are reserved for legacy ISA IRQs. 51 * Use vectors 0x30-0xe7 as the default device vector range for ia64. 52 * Platforms may choose to reduce this range in platform_irq_setup, but the 53 * platform range must fall within 54 * [IA64_DEF_FIRST_DEVICE_VECTOR..IA64_DEF_LAST_DEVICE_VECTOR] 55 */ 56 extern int ia64_first_device_vector; 57 extern int ia64_last_device_vector; 58 59 #if defined(CONFIG_SMP) && (defined(CONFIG_IA64_GENERIC) || defined (CONFIG_IA64_DIG)) 60 /* Reserve the lower priority vector than device vectors for "move IRQ" IPI */ 61 #define IA64_IRQ_MOVE_VECTOR 0x30 /* "move IRQ" IPI */ 62 #define IA64_DEF_FIRST_DEVICE_VECTOR 0x31 63 #else 64 #define IA64_DEF_FIRST_DEVICE_VECTOR 0x30 65 #endif 66 #define IA64_DEF_LAST_DEVICE_VECTOR 0xe7 67 #define IA64_FIRST_DEVICE_VECTOR ia64_first_device_vector 68 #define IA64_LAST_DEVICE_VECTOR ia64_last_device_vector 69 #define IA64_MAX_DEVICE_VECTORS (IA64_DEF_LAST_DEVICE_VECTOR - IA64_DEF_FIRST_DEVICE_VECTOR + 1) 70 #define IA64_NUM_DEVICE_VECTORS (IA64_LAST_DEVICE_VECTOR - IA64_FIRST_DEVICE_VECTOR + 1) 71 72 #define IA64_MCA_RENDEZ_VECTOR 0xe8 /* MCA rendez interrupt */ 73 #define IA64_PERFMON_VECTOR 0xee /* performance monitor interrupt vector */ 74 #define IA64_TIMER_VECTOR 0xef /* use highest-prio group 15 interrupt for timer */ 75 #define IA64_MCA_WAKEUP_VECTOR 0xf0 /* MCA wakeup (must be >MCA_RENDEZ_VECTOR) */ 76 #define IA64_IPI_LOCAL_TLB_FLUSH 0xfc /* SMP flush local TLB */ 77 #define IA64_IPI_RESCHEDULE 0xfd /* SMP reschedule */ 78 #define IA64_IPI_VECTOR 0xfe /* inter-processor interrupt vector */ 79 80 /* Used for encoding redirected irqs */ 81 82 #define IA64_IRQ_REDIRECTED (1 << 31) 83 84 /* IA64 inter-cpu interrupt related definitions */ 85 86 #define IA64_IPI_DEFAULT_BASE_ADDR 0xfee00000 87 88 /* Delivery modes for inter-cpu interrupts */ 89 enum { 90 IA64_IPI_DM_INT = 0x0, /* pend an external interrupt */ 91 IA64_IPI_DM_PMI = 0x2, /* pend a PMI */ 92 IA64_IPI_DM_NMI = 0x4, /* pend an NMI (vector 2) */ 93 IA64_IPI_DM_INIT = 0x5, /* pend an INIT interrupt */ 94 IA64_IPI_DM_EXTINT = 0x7, /* pend an 8259-compatible interrupt. */ 95 }; 96 97 extern __u8 isa_irq_to_vector_map[16]; 98 #define isa_irq_to_vector(x) isa_irq_to_vector_map[(x)] 99 100 struct irq_cfg { 101 ia64_vector vector; 102 cpumask_t domain; 103 cpumask_t old_domain; 104 unsigned move_cleanup_count; 105 u8 move_in_progress : 1; 106 }; 107 extern spinlock_t vector_lock; 108 extern struct irq_cfg irq_cfg[NR_IRQS]; 109 #define irq_to_domain(x) irq_cfg[(x)].domain 110 DECLARE_PER_CPU(int[IA64_NUM_VECTORS], vector_irq); 111 112 extern struct irq_chip irq_type_ia64_lsapic; /* CPU-internal interrupt controller */ 113 114 #define ia64_register_ipi ia64_native_register_ipi 115 #define assign_irq_vector ia64_native_assign_irq_vector 116 #define free_irq_vector ia64_native_free_irq_vector 117 #define register_percpu_irq ia64_native_register_percpu_irq 118 #define ia64_resend_irq ia64_native_resend_irq 119 120 extern void ia64_native_register_ipi(void); 121 extern int bind_irq_vector(int irq, int vector, cpumask_t domain); 122 extern int ia64_native_assign_irq_vector (int irq); /* allocate a free vector */ 123 extern void ia64_native_free_irq_vector (int vector); 124 extern int reserve_irq_vector (int vector); 125 extern void __setup_vector_irq(int cpu); 126 extern void ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect); 127 extern void ia64_native_register_percpu_irq (ia64_vector vec, struct irqaction *action); 128 extern void destroy_and_reserve_irq (unsigned int irq); 129 130 #if defined(CONFIG_SMP) && (defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_DIG)) 131 extern int irq_prepare_move(int irq, int cpu); 132 extern void irq_complete_move(unsigned int irq); 133 #else 134 static inline int irq_prepare_move(int irq, int cpu) { return 0; } 135 static inline void irq_complete_move(unsigned int irq) {} 136 #endif 137 138 static inline void ia64_native_resend_irq(unsigned int vector) 139 { 140 platform_send_ipi(smp_processor_id(), vector, IA64_IPI_DM_INT, 0); 141 } 142 143 /* 144 * Default implementations for the irq-descriptor API: 145 */ 146 #ifndef CONFIG_IA64_GENERIC 147 static inline ia64_vector __ia64_irq_to_vector(int irq) 148 { 149 return irq_cfg[irq].vector; 150 } 151 152 static inline unsigned int 153 __ia64_local_vector_to_irq (ia64_vector vec) 154 { 155 return __this_cpu_read(vector_irq[vec]); 156 } 157 #endif 158 159 /* 160 * Next follows the irq descriptor interface. On IA-64, each CPU supports 256 interrupt 161 * vectors. On smaller systems, there is a one-to-one correspondence between interrupt 162 * vectors and the Linux irq numbers. However, larger systems may have multiple interrupt 163 * domains meaning that the translation from vector number to irq number depends on the 164 * interrupt domain that a CPU belongs to. This API abstracts such platform-dependent 165 * differences and provides a uniform means to translate between vector and irq numbers 166 * and to obtain the irq descriptor for a given irq number. 167 */ 168 169 /* Extract the IA-64 vector that corresponds to IRQ. */ 170 static inline ia64_vector 171 irq_to_vector (int irq) 172 { 173 return platform_irq_to_vector(irq); 174 } 175 176 /* 177 * Convert the local IA-64 vector to the corresponding irq number. This translation is 178 * done in the context of the interrupt domain that the currently executing CPU belongs 179 * to. 180 */ 181 static inline unsigned int 182 local_vector_to_irq (ia64_vector vec) 183 { 184 return platform_local_vector_to_irq(vec); 185 } 186 187 #endif /* _ASM_IA64_HW_IRQ_H */ 188