1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Page table support for the Hexagon architecture 4 * 5 * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved. 6 */ 7 8 #ifndef _ASM_PGTABLE_H 9 #define _ASM_PGTABLE_H 10 11 /* 12 * Page table definitions for Qualcomm Hexagon processor. 13 */ 14 #include <asm/page.h> 15 #include <asm-generic/pgtable-nopmd.h> 16 17 /* A handy thing to have if one has the RAM. Declared in head.S */ 18 extern unsigned long empty_zero_page; 19 20 /* 21 * The PTE model described here is that of the Hexagon Virtual Machine, 22 * which autonomously walks 2-level page tables. At a lower level, we 23 * also describe the RISCish software-loaded TLB entry structure of 24 * the underlying Hexagon processor. A kernel built to run on the 25 * virtual machine has no need to know about the underlying hardware. 26 */ 27 #include <asm/vm_mmu.h> 28 29 /* 30 * To maximize the comfort level for the PTE manipulation macros, 31 * define the "well known" architecture-specific bits. 32 */ 33 #define _PAGE_READ __HVM_PTE_R 34 #define _PAGE_WRITE __HVM_PTE_W 35 #define _PAGE_EXECUTE __HVM_PTE_X 36 #define _PAGE_USER __HVM_PTE_U 37 38 /* 39 * We have a total of 4 "soft" bits available in the abstract PTE. 40 * The two mandatory software bits are Dirty and Accessed. 41 * To make nonlinear swap work according to the more recent 42 * model, we want a low order "Present" bit to indicate whether 43 * the PTE describes MMU programming or swap space. 44 */ 45 #define _PAGE_PRESENT (1<<0) 46 #define _PAGE_DIRTY (1<<1) 47 #define _PAGE_ACCESSED (1<<2) 48 49 /* 50 * For now, let's say that Valid and Present are the same thing. 51 * Alternatively, we could say that it's the "or" of R, W, and X 52 * permissions. 53 */ 54 #define _PAGE_VALID _PAGE_PRESENT 55 56 /* 57 * We're not defining _PAGE_GLOBAL here, since there's no concept 58 * of global pages or ASIDs exposed to the Hexagon Virtual Machine, 59 * and we want to use the same page table structures and macros in 60 * the native kernel as we do in the virtual machine kernel. 61 * So we'll put up with a bit of inefficiency for now... 62 */ 63 64 /* 65 * Top "FOURTH" level (pgd), which for the Hexagon VM is really 66 * only the second from the bottom, pgd and pud both being collapsed. 67 * Each entry represents 4MB of virtual address space, 4K of table 68 * thus maps the full 4GB. 69 */ 70 #define PGDIR_SHIFT 22 71 #define PTRS_PER_PGD 1024 72 73 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 74 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 75 76 #ifdef CONFIG_PAGE_SIZE_4KB 77 #define PTRS_PER_PTE 1024 78 #endif 79 80 #ifdef CONFIG_PAGE_SIZE_16KB 81 #define PTRS_PER_PTE 256 82 #endif 83 84 #ifdef CONFIG_PAGE_SIZE_64KB 85 #define PTRS_PER_PTE 64 86 #endif 87 88 #ifdef CONFIG_PAGE_SIZE_256KB 89 #define PTRS_PER_PTE 16 90 #endif 91 92 #ifdef CONFIG_PAGE_SIZE_1MB 93 #define PTRS_PER_PTE 4 94 #endif 95 96 /* Any bigger and the PTE disappears. */ 97 #define pgd_ERROR(e) \ 98 printk(KERN_ERR "%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__,\ 99 pgd_val(e)) 100 101 /* 102 * Page Protection Constants. Includes (in this variant) cache attributes. 103 */ 104 extern unsigned long _dflt_cache_att; 105 106 #define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_USER | \ 107 _dflt_cache_att) 108 #define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | \ 109 _PAGE_READ | _PAGE_EXECUTE | _dflt_cache_att) 110 #define PAGE_COPY PAGE_READONLY 111 #define PAGE_EXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | \ 112 _PAGE_READ | _PAGE_EXECUTE | _dflt_cache_att) 113 #define PAGE_COPY_EXEC PAGE_EXEC 114 #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | \ 115 _PAGE_EXECUTE | _PAGE_WRITE | _dflt_cache_att) 116 #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_READ | \ 117 _PAGE_WRITE | _PAGE_EXECUTE | _dflt_cache_att) 118 119 120 /* 121 * Aliases for mapping mmap() protection bits to page protections. 122 * These get used for static initialization, so using the _dflt_cache_att 123 * variable for the default cache attribute isn't workable. If the 124 * default gets changed at boot time, the boot option code has to 125 * update data structures like the protaction_map[] array. 126 */ 127 #define CACHEDEF (CACHE_DEFAULT << 6) 128 129 extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; /* located in head.S */ 130 131 /* HUGETLB not working currently */ 132 #ifdef CONFIG_HUGETLB_PAGE 133 #define pte_mkhuge(pte) __pte((pte_val(pte) & ~0x3) | HVM_HUGEPAGE_SIZE) 134 #endif 135 136 /* 137 * For now, assume that higher-level code will do TLB/MMU invalidations 138 * and don't insert that overhead into this low-level function. 139 */ 140 extern void sync_icache_dcache(pte_t pte); 141 142 #define pte_present_exec_user(pte) \ 143 ((pte_val(pte) & (_PAGE_EXECUTE | _PAGE_USER)) == \ 144 (_PAGE_EXECUTE | _PAGE_USER)) 145 146 static inline void set_pte(pte_t *ptep, pte_t pteval) 147 { 148 /* should really be using pte_exec, if it weren't declared later. */ 149 if (pte_present_exec_user(pteval)) 150 sync_icache_dcache(pteval); 151 152 *ptep = pteval; 153 } 154 155 /* 156 * For the Hexagon Virtual Machine MMU (or its emulation), a null/invalid 157 * L1 PTE (PMD/PGD) has 7 in the least significant bits. For the L2 PTE 158 * (Linux PTE), the key is to have bits 11..9 all zero. We'd use 0x7 159 * as a universal null entry, but some of those least significant bits 160 * are interpreted by software. 161 */ 162 #define _NULL_PMD 0x7 163 #define _NULL_PTE 0x0 164 165 static inline void pmd_clear(pmd_t *pmd_entry_ptr) 166 { 167 pmd_val(*pmd_entry_ptr) = _NULL_PMD; 168 } 169 170 /* 171 * Conveniently, a null PTE value is invalid. 172 */ 173 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, 174 pte_t *ptep) 175 { 176 pte_val(*ptep) = _NULL_PTE; 177 } 178 179 /** 180 * pmd_none - check if pmd_entry is mapped 181 * @pmd_entry: pmd entry 182 * 183 * MIPS checks it against that "invalid pte table" thing. 184 */ 185 static inline int pmd_none(pmd_t pmd) 186 { 187 return pmd_val(pmd) == _NULL_PMD; 188 } 189 190 /** 191 * pmd_present - is there a page table behind this? 192 * Essentially the inverse of pmd_none. We maybe 193 * save an inline instruction by defining it this 194 * way, instead of simply "!pmd_none". 195 */ 196 static inline int pmd_present(pmd_t pmd) 197 { 198 return pmd_val(pmd) != (unsigned long)_NULL_PMD; 199 } 200 201 /** 202 * pmd_bad - check if a PMD entry is "bad". That might mean swapped out. 203 * As we have no known cause of badness, it's null, as it is for many 204 * architectures. 205 */ 206 static inline int pmd_bad(pmd_t pmd) 207 { 208 return 0; 209 } 210 211 /* 212 * pmd_pfn - converts a PMD entry to a page frame number 213 */ 214 #define pmd_pfn(pmd) (pmd_val(pmd) >> PAGE_SHIFT) 215 216 /* 217 * pmd_page - converts a PMD entry to a page pointer 218 */ 219 #define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)) 220 221 /** 222 * pte_none - check if pte is mapped 223 * @pte: pte_t entry 224 */ 225 static inline int pte_none(pte_t pte) 226 { 227 return pte_val(pte) == _NULL_PTE; 228 }; 229 230 /* 231 * pte_present - check if page is present 232 */ 233 static inline int pte_present(pte_t pte) 234 { 235 return pte_val(pte) & _PAGE_PRESENT; 236 } 237 238 /* mk_pte - make a PTE out of a page pointer and protection bits */ 239 #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) 240 241 /* pte_page - returns a page (frame pointer/descriptor?) based on a PTE */ 242 #define pte_page(x) pfn_to_page(pte_pfn(x)) 243 244 /* pte_mkold - mark PTE as not recently accessed */ 245 static inline pte_t pte_mkold(pte_t pte) 246 { 247 pte_val(pte) &= ~_PAGE_ACCESSED; 248 return pte; 249 } 250 251 /* pte_mkyoung - mark PTE as recently accessed */ 252 static inline pte_t pte_mkyoung(pte_t pte) 253 { 254 pte_val(pte) |= _PAGE_ACCESSED; 255 return pte; 256 } 257 258 /* pte_mkclean - mark page as in sync with backing store */ 259 static inline pte_t pte_mkclean(pte_t pte) 260 { 261 pte_val(pte) &= ~_PAGE_DIRTY; 262 return pte; 263 } 264 265 /* pte_mkdirty - mark page as modified */ 266 static inline pte_t pte_mkdirty(pte_t pte) 267 { 268 pte_val(pte) |= _PAGE_DIRTY; 269 return pte; 270 } 271 272 /* pte_young - "is PTE marked as accessed"? */ 273 static inline int pte_young(pte_t pte) 274 { 275 return pte_val(pte) & _PAGE_ACCESSED; 276 } 277 278 /* pte_dirty - "is PTE dirty?" */ 279 static inline int pte_dirty(pte_t pte) 280 { 281 return pte_val(pte) & _PAGE_DIRTY; 282 } 283 284 /* pte_modify - set protection bits on PTE */ 285 static inline pte_t pte_modify(pte_t pte, pgprot_t prot) 286 { 287 pte_val(pte) &= PAGE_MASK; 288 pte_val(pte) |= pgprot_val(prot); 289 return pte; 290 } 291 292 /* pte_wrprotect - mark page as not writable */ 293 static inline pte_t pte_wrprotect(pte_t pte) 294 { 295 pte_val(pte) &= ~_PAGE_WRITE; 296 return pte; 297 } 298 299 /* pte_mkwrite - mark page as writable */ 300 static inline pte_t pte_mkwrite(pte_t pte) 301 { 302 pte_val(pte) |= _PAGE_WRITE; 303 return pte; 304 } 305 306 /* pte_mkexec - mark PTE as executable */ 307 static inline pte_t pte_mkexec(pte_t pte) 308 { 309 pte_val(pte) |= _PAGE_EXECUTE; 310 return pte; 311 } 312 313 /* pte_read - "is PTE marked as readable?" */ 314 static inline int pte_read(pte_t pte) 315 { 316 return pte_val(pte) & _PAGE_READ; 317 } 318 319 /* pte_write - "is PTE marked as writable?" */ 320 static inline int pte_write(pte_t pte) 321 { 322 return pte_val(pte) & _PAGE_WRITE; 323 } 324 325 326 /* pte_exec - "is PTE marked as executable?" */ 327 static inline int pte_exec(pte_t pte) 328 { 329 return pte_val(pte) & _PAGE_EXECUTE; 330 } 331 332 /* __pte_to_swp_entry - extract swap entry from PTE */ 333 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 334 335 /* __swp_entry_to_pte - extract PTE from swap entry */ 336 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 337 338 /* pfn_pte - convert page number and protection value to page table entry */ 339 #define pfn_pte(pfn, pgprot) __pte((pfn << PAGE_SHIFT) | pgprot_val(pgprot)) 340 341 /* pte_pfn - convert pte to page frame number */ 342 #define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT) 343 #define set_pmd(pmdptr, pmdval) (*(pmdptr) = (pmdval)) 344 345 /* 346 * set_pte_at - update page table and do whatever magic may be 347 * necessary to make the underlying hardware/firmware take note. 348 * 349 * VM may require a virtual instruction to alert the MMU. 350 */ 351 #define set_pte_at(mm, addr, ptep, pte) set_pte(ptep, pte) 352 353 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 354 { 355 return (unsigned long)__va(pmd_val(pmd) & PAGE_MASK); 356 } 357 358 /* ZERO_PAGE - returns the globally shared zero page */ 359 #define ZERO_PAGE(vaddr) (virt_to_page(&empty_zero_page)) 360 361 /* 362 * Swap/file PTE definitions. If _PAGE_PRESENT is zero, the rest of the PTE is 363 * interpreted as swap information. The remaining free bits are interpreted as 364 * swap type/offset tuple. Rather than have the TLB fill handler test 365 * _PAGE_PRESENT, we're going to reserve the permissions bits and set them to 366 * all zeros for swap entries, which speeds up the miss handler at the cost of 367 * 3 bits of offset. That trade-off can be revisited if necessary, but Hexagon 368 * processor architecture and target applications suggest a lot of TLB misses 369 * and not much swap space. 370 * 371 * Format of swap PTE: 372 * bit 0: Present (zero) 373 * bits 1-5: swap type (arch independent layer uses 5 bits max) 374 * bits 6-9: bits 3:0 of offset 375 * bits 10-12: effectively _PAGE_PROTNONE (all zero) 376 * bits 13-31: bits 22:4 of swap offset 377 * 378 * The split offset makes some of the following macros a little gnarly, 379 * but there's plenty of precedent for this sort of thing. 380 */ 381 382 /* Used for swap PTEs */ 383 #define __swp_type(swp_pte) (((swp_pte).val >> 1) & 0x1f) 384 385 #define __swp_offset(swp_pte) \ 386 ((((swp_pte).val >> 6) & 0xf) | (((swp_pte).val >> 9) & 0x7ffff0)) 387 388 #define __swp_entry(type, offset) \ 389 ((swp_entry_t) { \ 390 ((type << 1) | \ 391 ((offset & 0x7ffff0) << 9) | ((offset & 0xf) << 6)) }) 392 393 #endif 394