xref: /openbmc/linux/arch/hexagon/include/asm/io.h (revision d58f75de)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * IO definitions for the Hexagon architecture
4  *
5  * Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
6  */
7 
8 #ifndef _ASM_IO_H
9 #define _ASM_IO_H
10 
11 #ifdef __KERNEL__
12 
13 #include <linux/types.h>
14 #include <asm/iomap.h>
15 #include <asm/page.h>
16 #include <asm/cacheflush.h>
17 
18 /*
19  * We don't have PCI yet.
20  * _IO_BASE is pointing at what should be unused virtual space.
21  */
22 #define IO_SPACE_LIMIT 0xffff
23 #define _IO_BASE ((void __iomem *)0xfe000000)
24 
25 #define IOMEM(x)        ((void __force __iomem *)(x))
26 
27 extern int remap_area_pages(unsigned long start, unsigned long phys_addr,
28 				unsigned long end, unsigned long flags);
29 
30 extern void iounmap(const volatile void __iomem *addr);
31 
32 /* Defined in lib/io.c, needed for smc91x driver. */
33 extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen);
34 extern void __raw_writesw(void __iomem *addr, const void *data, int wordlen);
35 
36 extern void __raw_readsl(const void __iomem *addr, void *data, int wordlen);
37 extern void __raw_writesl(void __iomem *addr, const void *data, int wordlen);
38 
39 #define readsw(p, d, l)	__raw_readsw(p, d, l)
40 #define writesw(p, d, l) __raw_writesw(p, d, l)
41 
42 #define readsl(p, d, l)   __raw_readsl(p, d, l)
43 #define writesl(p, d, l)  __raw_writesl(p, d, l)
44 
45 /*
46  * virt_to_phys - map virtual address to physical
47  * @address:  address to map
48  */
49 static inline unsigned long virt_to_phys(volatile void *address)
50 {
51 	return __pa(address);
52 }
53 
54 /*
55  * phys_to_virt - map physical address to virtual
56  * @address: address to map
57  */
58 static inline void *phys_to_virt(unsigned long address)
59 {
60 	return __va(address);
61 }
62 
63 /*
64  * convert a physical pointer to a virtual kernel pointer for
65  * /dev/mem access.
66  */
67 #define xlate_dev_mem_ptr(p)    __va(p)
68 
69 /*
70  * IO port access primitives.  Hexagon doesn't have special IO access
71  * instructions; all I/O is memory mapped.
72  *
73  * in/out are used for "ports", but we don't have "port instructions",
74  * so these are really just memory mapped too.
75  */
76 
77 /*
78  * readb - read byte from memory mapped device
79  * @addr:  pointer to memory
80  *
81  * Operates on "I/O bus memory space"
82  */
83 static inline u8 readb(const volatile void __iomem *addr)
84 {
85 	u8 val;
86 	asm volatile(
87 		"%0 = memb(%1);"
88 		: "=&r" (val)
89 		: "r" (addr)
90 	);
91 	return val;
92 }
93 
94 static inline u16 readw(const volatile void __iomem *addr)
95 {
96 	u16 val;
97 	asm volatile(
98 		"%0 = memh(%1);"
99 		: "=&r" (val)
100 		: "r" (addr)
101 	);
102 	return val;
103 }
104 
105 static inline u32 readl(const volatile void __iomem *addr)
106 {
107 	u32 val;
108 	asm volatile(
109 		"%0 = memw(%1);"
110 		: "=&r" (val)
111 		: "r" (addr)
112 	);
113 	return val;
114 }
115 
116 /*
117  * writeb - write a byte to a memory location
118  * @data: data to write to
119  * @addr:  pointer to memory
120  *
121  */
122 static inline void writeb(u8 data, volatile void __iomem *addr)
123 {
124 	asm volatile(
125 		"memb(%0) = %1;"
126 		:
127 		: "r" (addr), "r" (data)
128 		: "memory"
129 	);
130 }
131 
132 static inline void writew(u16 data, volatile void __iomem *addr)
133 {
134 	asm volatile(
135 		"memh(%0) = %1;"
136 		:
137 		: "r" (addr), "r" (data)
138 		: "memory"
139 	);
140 
141 }
142 
143 static inline void writel(u32 data, volatile void __iomem *addr)
144 {
145 	asm volatile(
146 		"memw(%0) = %1;"
147 		:
148 		: "r" (addr), "r" (data)
149 		: "memory"
150 	);
151 }
152 
153 #define __raw_writeb writeb
154 #define __raw_writew writew
155 #define __raw_writel writel
156 
157 #define __raw_readb readb
158 #define __raw_readw readw
159 #define __raw_readl readl
160 
161 /*
162  * http://comments.gmane.org/gmane.linux.ports.arm.kernel/117626
163  */
164 
165 #define readb_relaxed __raw_readb
166 #define readw_relaxed __raw_readw
167 #define readl_relaxed __raw_readl
168 
169 #define writeb_relaxed __raw_writeb
170 #define writew_relaxed __raw_writew
171 #define writel_relaxed __raw_writel
172 
173 void __iomem *ioremap(unsigned long phys_addr, unsigned long size);
174 #define ioremap_uc(X, Y) ioremap((X), (Y))
175 
176 
177 #define __raw_writel writel
178 
179 static inline void memcpy_fromio(void *dst, const volatile void __iomem *src,
180 	int count)
181 {
182 	memcpy(dst, (void *) src, count);
183 }
184 
185 static inline void memcpy_toio(volatile void __iomem *dst, const void *src,
186 	int count)
187 {
188 	memcpy((void *) dst, src, count);
189 }
190 
191 static inline void memset_io(volatile void __iomem *addr, int value,
192 			     size_t size)
193 {
194 	memset((void __force *)addr, value, size);
195 }
196 
197 #define PCI_IO_ADDR	(volatile void __iomem *)
198 
199 /*
200  * inb - read byte from I/O port or something
201  * @port:  address in I/O space
202  *
203  * Operates on "I/O bus I/O space"
204  */
205 static inline u8 inb(unsigned long port)
206 {
207 	return readb(_IO_BASE + (port & IO_SPACE_LIMIT));
208 }
209 
210 static inline u16 inw(unsigned long port)
211 {
212 	return readw(_IO_BASE + (port & IO_SPACE_LIMIT));
213 }
214 
215 static inline u32 inl(unsigned long port)
216 {
217 	return readl(_IO_BASE + (port & IO_SPACE_LIMIT));
218 }
219 
220 /*
221  * outb - write a byte to a memory location
222  * @data: data to write to
223  * @addr:  address in I/O space
224  */
225 static inline void outb(u8 data, unsigned long port)
226 {
227 	writeb(data, _IO_BASE + (port & IO_SPACE_LIMIT));
228 }
229 
230 static inline void outw(u16 data, unsigned long port)
231 {
232 	writew(data, _IO_BASE + (port & IO_SPACE_LIMIT));
233 }
234 
235 static inline void outl(u32 data, unsigned long port)
236 {
237 	writel(data, _IO_BASE + (port & IO_SPACE_LIMIT));
238 }
239 
240 #define outb_p outb
241 #define outw_p outw
242 #define outl_p outl
243 
244 #define inb_p inb
245 #define inw_p inw
246 #define inl_p inl
247 
248 static inline void insb(unsigned long port, void *buffer, int count)
249 {
250 	if (count) {
251 		u8 *buf = buffer;
252 		do {
253 			u8 x = inb(port);
254 			*buf++ = x;
255 		} while (--count);
256 	}
257 }
258 
259 static inline void insw(unsigned long port, void *buffer, int count)
260 {
261 	if (count) {
262 		u16 *buf = buffer;
263 		do {
264 			u16 x = inw(port);
265 			*buf++ = x;
266 		} while (--count);
267 	}
268 }
269 
270 static inline void insl(unsigned long port, void *buffer, int count)
271 {
272 	if (count) {
273 		u32 *buf = buffer;
274 		do {
275 			u32 x = inw(port);
276 			*buf++ = x;
277 		} while (--count);
278 	}
279 }
280 
281 static inline void outsb(unsigned long port, const void *buffer, int count)
282 {
283 	if (count) {
284 		const u8 *buf = buffer;
285 		do {
286 			outb(*buf++, port);
287 		} while (--count);
288 	}
289 }
290 
291 static inline void outsw(unsigned long port, const void *buffer, int count)
292 {
293 	if (count) {
294 		const u16 *buf = buffer;
295 		do {
296 			outw(*buf++, port);
297 		} while (--count);
298 	}
299 }
300 
301 static inline void outsl(unsigned long port, const void *buffer, int count)
302 {
303 	if (count) {
304 		const u32 *buf = buffer;
305 		do {
306 			outl(*buf++, port);
307 		} while (--count);
308 	}
309 }
310 
311 #endif /* __KERNEL__ */
312 
313 #endif
314