xref: /openbmc/linux/arch/hexagon/include/asm/io.h (revision 5a158981)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * IO definitions for the Hexagon architecture
4  *
5  * Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
6  */
7 
8 #ifndef _ASM_IO_H
9 #define _ASM_IO_H
10 
11 #ifdef __KERNEL__
12 
13 #include <linux/types.h>
14 #include <asm/iomap.h>
15 #include <asm/page.h>
16 #include <asm/cacheflush.h>
17 
18 /*
19  * We don't have PCI yet.
20  * _IO_BASE is pointing at what should be unused virtual space.
21  */
22 #define IO_SPACE_LIMIT 0xffff
23 #define _IO_BASE ((void __iomem *)0xfe000000)
24 
25 #define IOMEM(x)        ((void __force __iomem *)(x))
26 
27 extern int remap_area_pages(unsigned long start, unsigned long phys_addr,
28 				unsigned long end, unsigned long flags);
29 
30 extern void iounmap(const volatile void __iomem *addr);
31 
32 /* Defined in lib/io.c, needed for smc91x driver. */
33 extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen);
34 extern void __raw_writesw(void __iomem *addr, const void *data, int wordlen);
35 
36 extern void __raw_readsl(const void __iomem *addr, void *data, int wordlen);
37 extern void __raw_writesl(void __iomem *addr, const void *data, int wordlen);
38 
39 #define readsw(p, d, l)	__raw_readsw(p, d, l)
40 #define writesw(p, d, l) __raw_writesw(p, d, l)
41 
42 #define readsl(p, d, l)   __raw_readsl(p, d, l)
43 #define writesl(p, d, l)  __raw_writesl(p, d, l)
44 
45 /*
46  * virt_to_phys - map virtual address to physical
47  * @address:  address to map
48  */
49 static inline unsigned long virt_to_phys(volatile void *address)
50 {
51 	return __pa(address);
52 }
53 
54 /*
55  * phys_to_virt - map physical address to virtual
56  * @address: address to map
57  */
58 static inline void *phys_to_virt(unsigned long address)
59 {
60 	return __va(address);
61 }
62 
63 /*
64  * convert a physical pointer to a virtual kernel pointer for
65  * /dev/mem access.
66  */
67 #define xlate_dev_kmem_ptr(p)    __va(p)
68 #define xlate_dev_mem_ptr(p)    __va(p)
69 
70 /*
71  * IO port access primitives.  Hexagon doesn't have special IO access
72  * instructions; all I/O is memory mapped.
73  *
74  * in/out are used for "ports", but we don't have "port instructions",
75  * so these are really just memory mapped too.
76  */
77 
78 /*
79  * readb - read byte from memory mapped device
80  * @addr:  pointer to memory
81  *
82  * Operates on "I/O bus memory space"
83  */
84 static inline u8 readb(const volatile void __iomem *addr)
85 {
86 	u8 val;
87 	asm volatile(
88 		"%0 = memb(%1);"
89 		: "=&r" (val)
90 		: "r" (addr)
91 	);
92 	return val;
93 }
94 
95 static inline u16 readw(const volatile void __iomem *addr)
96 {
97 	u16 val;
98 	asm volatile(
99 		"%0 = memh(%1);"
100 		: "=&r" (val)
101 		: "r" (addr)
102 	);
103 	return val;
104 }
105 
106 static inline u32 readl(const volatile void __iomem *addr)
107 {
108 	u32 val;
109 	asm volatile(
110 		"%0 = memw(%1);"
111 		: "=&r" (val)
112 		: "r" (addr)
113 	);
114 	return val;
115 }
116 
117 /*
118  * writeb - write a byte to a memory location
119  * @data: data to write to
120  * @addr:  pointer to memory
121  *
122  */
123 static inline void writeb(u8 data, volatile void __iomem *addr)
124 {
125 	asm volatile(
126 		"memb(%0) = %1;"
127 		:
128 		: "r" (addr), "r" (data)
129 		: "memory"
130 	);
131 }
132 
133 static inline void writew(u16 data, volatile void __iomem *addr)
134 {
135 	asm volatile(
136 		"memh(%0) = %1;"
137 		:
138 		: "r" (addr), "r" (data)
139 		: "memory"
140 	);
141 
142 }
143 
144 static inline void writel(u32 data, volatile void __iomem *addr)
145 {
146 	asm volatile(
147 		"memw(%0) = %1;"
148 		:
149 		: "r" (addr), "r" (data)
150 		: "memory"
151 	);
152 }
153 
154 #define __raw_writeb writeb
155 #define __raw_writew writew
156 #define __raw_writel writel
157 
158 #define __raw_readb readb
159 #define __raw_readw readw
160 #define __raw_readl readl
161 
162 /*
163  * http://comments.gmane.org/gmane.linux.ports.arm.kernel/117626
164  */
165 
166 #define readb_relaxed __raw_readb
167 #define readw_relaxed __raw_readw
168 #define readl_relaxed __raw_readl
169 
170 #define writeb_relaxed __raw_writeb
171 #define writew_relaxed __raw_writew
172 #define writel_relaxed __raw_writel
173 
174 void __iomem *ioremap(unsigned long phys_addr, unsigned long size);
175 #define ioremap_nocache ioremap
176 #define ioremap_uc(X, Y) ioremap((X), (Y))
177 
178 
179 #define __raw_writel writel
180 
181 static inline void memcpy_fromio(void *dst, const volatile void __iomem *src,
182 	int count)
183 {
184 	memcpy(dst, (void *) src, count);
185 }
186 
187 static inline void memcpy_toio(volatile void __iomem *dst, const void *src,
188 	int count)
189 {
190 	memcpy((void *) dst, src, count);
191 }
192 
193 static inline void memset_io(volatile void __iomem *addr, int value,
194 			     size_t size)
195 {
196 	memset((void __force *)addr, value, size);
197 }
198 
199 #define PCI_IO_ADDR	(volatile void __iomem *)
200 
201 /*
202  * inb - read byte from I/O port or something
203  * @port:  address in I/O space
204  *
205  * Operates on "I/O bus I/O space"
206  */
207 static inline u8 inb(unsigned long port)
208 {
209 	return readb(_IO_BASE + (port & IO_SPACE_LIMIT));
210 }
211 
212 static inline u16 inw(unsigned long port)
213 {
214 	return readw(_IO_BASE + (port & IO_SPACE_LIMIT));
215 }
216 
217 static inline u32 inl(unsigned long port)
218 {
219 	return readl(_IO_BASE + (port & IO_SPACE_LIMIT));
220 }
221 
222 /*
223  * outb - write a byte to a memory location
224  * @data: data to write to
225  * @addr:  address in I/O space
226  */
227 static inline void outb(u8 data, unsigned long port)
228 {
229 	writeb(data, _IO_BASE + (port & IO_SPACE_LIMIT));
230 }
231 
232 static inline void outw(u16 data, unsigned long port)
233 {
234 	writew(data, _IO_BASE + (port & IO_SPACE_LIMIT));
235 }
236 
237 static inline void outl(u32 data, unsigned long port)
238 {
239 	writel(data, _IO_BASE + (port & IO_SPACE_LIMIT));
240 }
241 
242 #define outb_p outb
243 #define outw_p outw
244 #define outl_p outl
245 
246 #define inb_p inb
247 #define inw_p inw
248 #define inl_p inl
249 
250 static inline void insb(unsigned long port, void *buffer, int count)
251 {
252 	if (count) {
253 		u8 *buf = buffer;
254 		do {
255 			u8 x = inb(port);
256 			*buf++ = x;
257 		} while (--count);
258 	}
259 }
260 
261 static inline void insw(unsigned long port, void *buffer, int count)
262 {
263 	if (count) {
264 		u16 *buf = buffer;
265 		do {
266 			u16 x = inw(port);
267 			*buf++ = x;
268 		} while (--count);
269 	}
270 }
271 
272 static inline void insl(unsigned long port, void *buffer, int count)
273 {
274 	if (count) {
275 		u32 *buf = buffer;
276 		do {
277 			u32 x = inw(port);
278 			*buf++ = x;
279 		} while (--count);
280 	}
281 }
282 
283 static inline void outsb(unsigned long port, const void *buffer, int count)
284 {
285 	if (count) {
286 		const u8 *buf = buffer;
287 		do {
288 			outb(*buf++, port);
289 		} while (--count);
290 	}
291 }
292 
293 static inline void outsw(unsigned long port, const void *buffer, int count)
294 {
295 	if (count) {
296 		const u16 *buf = buffer;
297 		do {
298 			outw(*buf++, port);
299 		} while (--count);
300 	}
301 }
302 
303 static inline void outsl(unsigned long port, const void *buffer, int count)
304 {
305 	if (count) {
306 		const u32 *buf = buffer;
307 		do {
308 			outl(*buf++, port);
309 		} while (--count);
310 	}
311 }
312 
313 #endif /* __KERNEL__ */
314 
315 #endif
316