1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * IO definitions for the Hexagon architecture 4 * 5 * Copyright (c) 2010-2013, The Linux Foundation. All rights reserved. 6 */ 7 8 #ifndef _ASM_IO_H 9 #define _ASM_IO_H 10 11 #ifdef __KERNEL__ 12 13 #include <linux/types.h> 14 #include <asm/iomap.h> 15 #include <asm/page.h> 16 #include <asm/cacheflush.h> 17 18 /* 19 * We don't have PCI yet. 20 * _IO_BASE is pointing at what should be unused virtual space. 21 */ 22 #define IO_SPACE_LIMIT 0xffff 23 #define _IO_BASE ((void __iomem *)0xfe000000) 24 25 #define IOMEM(x) ((void __force __iomem *)(x)) 26 27 extern int remap_area_pages(unsigned long start, unsigned long phys_addr, 28 unsigned long end, unsigned long flags); 29 30 extern void iounmap(const volatile void __iomem *addr); 31 32 /* Defined in lib/io.c, needed for smc91x driver. */ 33 extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen); 34 extern void __raw_writesw(void __iomem *addr, const void *data, int wordlen); 35 36 extern void __raw_readsl(const void __iomem *addr, void *data, int wordlen); 37 extern void __raw_writesl(void __iomem *addr, const void *data, int wordlen); 38 39 #define readsw(p, d, l) __raw_readsw(p, d, l) 40 #define writesw(p, d, l) __raw_writesw(p, d, l) 41 42 #define readsl(p, d, l) __raw_readsl(p, d, l) 43 #define writesl(p, d, l) __raw_writesl(p, d, l) 44 45 /* 46 * virt_to_phys - map virtual address to physical 47 * @address: address to map 48 */ 49 static inline unsigned long virt_to_phys(volatile void *address) 50 { 51 return __pa(address); 52 } 53 54 /* 55 * phys_to_virt - map physical address to virtual 56 * @address: address to map 57 */ 58 static inline void *phys_to_virt(unsigned long address) 59 { 60 return __va(address); 61 } 62 63 /* 64 * convert a physical pointer to a virtual kernel pointer for 65 * /dev/mem access. 66 */ 67 #define xlate_dev_kmem_ptr(p) __va(p) 68 #define xlate_dev_mem_ptr(p) __va(p) 69 70 /* 71 * IO port access primitives. Hexagon doesn't have special IO access 72 * instructions; all I/O is memory mapped. 73 * 74 * in/out are used for "ports", but we don't have "port instructions", 75 * so these are really just memory mapped too. 76 */ 77 78 /* 79 * readb - read byte from memory mapped device 80 * @addr: pointer to memory 81 * 82 * Operates on "I/O bus memory space" 83 */ 84 static inline u8 readb(const volatile void __iomem *addr) 85 { 86 u8 val; 87 asm volatile( 88 "%0 = memb(%1);" 89 : "=&r" (val) 90 : "r" (addr) 91 ); 92 return val; 93 } 94 95 static inline u16 readw(const volatile void __iomem *addr) 96 { 97 u16 val; 98 asm volatile( 99 "%0 = memh(%1);" 100 : "=&r" (val) 101 : "r" (addr) 102 ); 103 return val; 104 } 105 106 static inline u32 readl(const volatile void __iomem *addr) 107 { 108 u32 val; 109 asm volatile( 110 "%0 = memw(%1);" 111 : "=&r" (val) 112 : "r" (addr) 113 ); 114 return val; 115 } 116 117 /* 118 * writeb - write a byte to a memory location 119 * @data: data to write to 120 * @addr: pointer to memory 121 * 122 */ 123 static inline void writeb(u8 data, volatile void __iomem *addr) 124 { 125 asm volatile( 126 "memb(%0) = %1;" 127 : 128 : "r" (addr), "r" (data) 129 : "memory" 130 ); 131 } 132 133 static inline void writew(u16 data, volatile void __iomem *addr) 134 { 135 asm volatile( 136 "memh(%0) = %1;" 137 : 138 : "r" (addr), "r" (data) 139 : "memory" 140 ); 141 142 } 143 144 static inline void writel(u32 data, volatile void __iomem *addr) 145 { 146 asm volatile( 147 "memw(%0) = %1;" 148 : 149 : "r" (addr), "r" (data) 150 : "memory" 151 ); 152 } 153 154 #define __raw_writeb writeb 155 #define __raw_writew writew 156 #define __raw_writel writel 157 158 #define __raw_readb readb 159 #define __raw_readw readw 160 #define __raw_readl readl 161 162 /* 163 * http://comments.gmane.org/gmane.linux.ports.arm.kernel/117626 164 */ 165 166 #define readb_relaxed __raw_readb 167 #define readw_relaxed __raw_readw 168 #define readl_relaxed __raw_readl 169 170 #define writeb_relaxed __raw_writeb 171 #define writew_relaxed __raw_writew 172 #define writel_relaxed __raw_writel 173 174 void __iomem *ioremap(unsigned long phys_addr, unsigned long size); 175 #define ioremap_uc(X, Y) ioremap((X), (Y)) 176 177 178 #define __raw_writel writel 179 180 static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, 181 int count) 182 { 183 memcpy(dst, (void *) src, count); 184 } 185 186 static inline void memcpy_toio(volatile void __iomem *dst, const void *src, 187 int count) 188 { 189 memcpy((void *) dst, src, count); 190 } 191 192 static inline void memset_io(volatile void __iomem *addr, int value, 193 size_t size) 194 { 195 memset((void __force *)addr, value, size); 196 } 197 198 #define PCI_IO_ADDR (volatile void __iomem *) 199 200 /* 201 * inb - read byte from I/O port or something 202 * @port: address in I/O space 203 * 204 * Operates on "I/O bus I/O space" 205 */ 206 static inline u8 inb(unsigned long port) 207 { 208 return readb(_IO_BASE + (port & IO_SPACE_LIMIT)); 209 } 210 211 static inline u16 inw(unsigned long port) 212 { 213 return readw(_IO_BASE + (port & IO_SPACE_LIMIT)); 214 } 215 216 static inline u32 inl(unsigned long port) 217 { 218 return readl(_IO_BASE + (port & IO_SPACE_LIMIT)); 219 } 220 221 /* 222 * outb - write a byte to a memory location 223 * @data: data to write to 224 * @addr: address in I/O space 225 */ 226 static inline void outb(u8 data, unsigned long port) 227 { 228 writeb(data, _IO_BASE + (port & IO_SPACE_LIMIT)); 229 } 230 231 static inline void outw(u16 data, unsigned long port) 232 { 233 writew(data, _IO_BASE + (port & IO_SPACE_LIMIT)); 234 } 235 236 static inline void outl(u32 data, unsigned long port) 237 { 238 writel(data, _IO_BASE + (port & IO_SPACE_LIMIT)); 239 } 240 241 #define outb_p outb 242 #define outw_p outw 243 #define outl_p outl 244 245 #define inb_p inb 246 #define inw_p inw 247 #define inl_p inl 248 249 static inline void insb(unsigned long port, void *buffer, int count) 250 { 251 if (count) { 252 u8 *buf = buffer; 253 do { 254 u8 x = inb(port); 255 *buf++ = x; 256 } while (--count); 257 } 258 } 259 260 static inline void insw(unsigned long port, void *buffer, int count) 261 { 262 if (count) { 263 u16 *buf = buffer; 264 do { 265 u16 x = inw(port); 266 *buf++ = x; 267 } while (--count); 268 } 269 } 270 271 static inline void insl(unsigned long port, void *buffer, int count) 272 { 273 if (count) { 274 u32 *buf = buffer; 275 do { 276 u32 x = inw(port); 277 *buf++ = x; 278 } while (--count); 279 } 280 } 281 282 static inline void outsb(unsigned long port, const void *buffer, int count) 283 { 284 if (count) { 285 const u8 *buf = buffer; 286 do { 287 outb(*buf++, port); 288 } while (--count); 289 } 290 } 291 292 static inline void outsw(unsigned long port, const void *buffer, int count) 293 { 294 if (count) { 295 const u16 *buf = buffer; 296 do { 297 outw(*buf++, port); 298 } while (--count); 299 } 300 } 301 302 static inline void outsl(unsigned long port, const void *buffer, int count) 303 { 304 if (count) { 305 const u32 *buf = buffer; 306 do { 307 outl(*buf++, port); 308 } while (--count); 309 } 310 } 311 312 #endif /* __KERNEL__ */ 313 314 #endif 315