1 /* 2 * Cache flush operations for the Hexagon architecture 3 * 4 * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 and 8 * only version 2 as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 18 * 02110-1301, USA. 19 */ 20 21 #ifndef _ASM_CACHEFLUSH_H 22 #define _ASM_CACHEFLUSH_H 23 24 #include <linux/cache.h> 25 #include <linux/mm.h> 26 #include <asm/string.h> 27 #include <asm-generic/cacheflush.h> 28 29 /* Cache flushing: 30 * 31 * - flush_cache_all() flushes entire cache 32 * - flush_cache_mm(mm) flushes the specified mm context's cache lines 33 * - flush_cache_page(mm, vmaddr, pfn) flushes a single page 34 * - flush_cache_range(vma, start, end) flushes a range of pages 35 * - flush_icache_range(start, end) flush a range of instructions 36 * - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache 37 * - flush_icache_page(vma, pg) flushes(invalidates) a page for icache 38 * 39 * Need to doublecheck which one is really needed for ptrace stuff to work. 40 */ 41 #define LINESIZE 32 42 #define LINEBITS 5 43 44 /* 45 * Flush Dcache range through current map. 46 */ 47 extern void flush_dcache_range(unsigned long start, unsigned long end); 48 49 /* 50 * Flush Icache range through current map. 51 */ 52 #undef flush_icache_range 53 extern void flush_icache_range(unsigned long start, unsigned long end); 54 55 /* 56 * Memory-management related flushes are there to ensure in non-physically 57 * indexed cache schemes that stale lines belonging to a given ASID aren't 58 * in the cache to confuse things. The prototype Hexagon Virtual Machine 59 * only uses a single ASID for all user-mode maps, which should 60 * mean that they aren't necessary. A brute-force, flush-everything 61 * implementation, with the name xxxxx_hexagon() is present in 62 * arch/hexagon/mm/cache.c, but let's not wire it up until we know 63 * it is needed. 64 */ 65 extern void flush_cache_all_hexagon(void); 66 67 /* 68 * This may or may not ever have to be non-null, depending on the 69 * virtual machine MMU. For a native kernel, it's definitiely a no-op 70 * 71 * This is also the place where deferred cache coherency stuff seems 72 * to happen, classically... but instead we do it like ia64 and 73 * clean the cache when the PTE is set. 74 * 75 */ 76 static inline void update_mmu_cache(struct vm_area_struct *vma, 77 unsigned long address, pte_t *ptep) 78 { 79 /* generic_ptrace_pokedata doesn't wind up here, does it? */ 80 } 81 82 #undef copy_to_user_page 83 static inline void copy_to_user_page(struct vm_area_struct *vma, 84 struct page *page, 85 unsigned long vaddr, 86 void *dst, void *src, int len) 87 { 88 memcpy(dst, src, len); 89 if (vma->vm_flags & VM_EXEC) { 90 flush_icache_range((unsigned long) dst, 91 (unsigned long) dst + len); 92 } 93 } 94 95 96 extern void hexagon_inv_dcache_range(unsigned long start, unsigned long end); 97 extern void hexagon_clean_dcache_range(unsigned long start, unsigned long end); 98 99 #endif 100