xref: /openbmc/linux/arch/hexagon/include/asm/atomic.h (revision d2999e1b)
1 /*
2  * Atomic operations for the Hexagon architecture
3  *
4  * Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
5  *
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 and
9  * only version 2 as published by the Free Software Foundation.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
19  * 02110-1301, USA.
20  */
21 
22 #ifndef _ASM_ATOMIC_H
23 #define _ASM_ATOMIC_H
24 
25 #include <linux/types.h>
26 #include <asm/cmpxchg.h>
27 #include <asm/barrier.h>
28 
29 #define ATOMIC_INIT(i)		{ (i) }
30 
31 /*  Normal writes in our arch don't clear lock reservations  */
32 
33 static inline void atomic_set(atomic_t *v, int new)
34 {
35 	asm volatile(
36 		"1:	r6 = memw_locked(%0);\n"
37 		"	memw_locked(%0,p0) = %1;\n"
38 		"	if (!P0) jump 1b;\n"
39 		:
40 		: "r" (&v->counter), "r" (new)
41 		: "memory", "p0", "r6"
42 	);
43 }
44 
45 /**
46  * atomic_read - reads a word, atomically
47  * @v: pointer to atomic value
48  *
49  * Assumes all word reads on our architecture are atomic.
50  */
51 #define atomic_read(v)		((v)->counter)
52 
53 /**
54  * atomic_xchg - atomic
55  * @v: pointer to memory to change
56  * @new: new value (technically passed in a register -- see xchg)
57  */
58 #define atomic_xchg(v, new)	(xchg(&((v)->counter), (new)))
59 
60 
61 /**
62  * atomic_cmpxchg - atomic compare-and-exchange values
63  * @v: pointer to value to change
64  * @old:  desired old value to match
65  * @new:  new value to put in
66  *
67  * Parameters are then pointer, value-in-register, value-in-register,
68  * and the output is the old value.
69  *
70  * Apparently this is complicated for archs that don't support
71  * the memw_locked like we do (or it's broken or whatever).
72  *
73  * Kind of the lynchpin of the rest of the generically defined routines.
74  * Remember V2 had that bug with dotnew predicate set by memw_locked.
75  *
76  * "old" is "expected" old val, __oldval is actual old value
77  */
78 static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
79 {
80 	int __oldval;
81 
82 	asm volatile(
83 		"1:	%0 = memw_locked(%1);\n"
84 		"	{ P0 = cmp.eq(%0,%2);\n"
85 		"	  if (!P0.new) jump:nt 2f; }\n"
86 		"	memw_locked(%1,P0) = %3;\n"
87 		"	if (!P0) jump 1b;\n"
88 		"2:\n"
89 		: "=&r" (__oldval)
90 		: "r" (&v->counter), "r" (old), "r" (new)
91 		: "memory", "p0"
92 	);
93 
94 	return __oldval;
95 }
96 
97 static inline int atomic_add_return(int i, atomic_t *v)
98 {
99 	int output;
100 
101 	__asm__ __volatile__ (
102 		"1:	%0 = memw_locked(%1);\n"
103 		"	%0 = add(%0,%2);\n"
104 		"	memw_locked(%1,P3)=%0;\n"
105 		"	if !P3 jump 1b;\n"
106 		: "=&r" (output)
107 		: "r" (&v->counter), "r" (i)
108 		: "memory", "p3"
109 	);
110 	return output;
111 
112 }
113 
114 #define atomic_add(i, v) atomic_add_return(i, (v))
115 
116 static inline int atomic_sub_return(int i, atomic_t *v)
117 {
118 	int output;
119 	__asm__ __volatile__ (
120 		"1:	%0 = memw_locked(%1);\n"
121 		"	%0 = sub(%0,%2);\n"
122 		"	memw_locked(%1,P3)=%0\n"
123 		"	if !P3 jump 1b;\n"
124 		: "=&r" (output)
125 		: "r" (&v->counter), "r" (i)
126 		: "memory", "p3"
127 	);
128 	return output;
129 }
130 
131 #define atomic_sub(i, v) atomic_sub_return(i, (v))
132 
133 /**
134  * __atomic_add_unless - add unless the number is a given value
135  * @v: pointer to value
136  * @a: amount to add
137  * @u: unless value is equal to u
138  *
139  * Returns old value.
140  *
141  */
142 
143 static inline int __atomic_add_unless(atomic_t *v, int a, int u)
144 {
145 	int __oldval;
146 	register int tmp;
147 
148 	asm volatile(
149 		"1:	%0 = memw_locked(%2);"
150 		"	{"
151 		"		p3 = cmp.eq(%0, %4);"
152 		"		if (p3.new) jump:nt 2f;"
153 		"		%1 = add(%0, %3);"
154 		"	}"
155 		"	memw_locked(%2, p3) = %1;"
156 		"	{"
157 		"		if !p3 jump 1b;"
158 		"	}"
159 		"2:"
160 		: "=&r" (__oldval), "=&r" (tmp)
161 		: "r" (v), "r" (a), "r" (u)
162 		: "memory", "p3"
163 	);
164 	return __oldval;
165 }
166 
167 #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
168 
169 #define atomic_inc(v) atomic_add(1, (v))
170 #define atomic_dec(v) atomic_sub(1, (v))
171 
172 #define atomic_inc_and_test(v) (atomic_add_return(1, (v)) == 0)
173 #define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
174 #define atomic_sub_and_test(i, v) (atomic_sub_return(i, (v)) == 0)
175 #define atomic_add_negative(i, v) (atomic_add_return(i, (v)) < 0)
176 
177 #define atomic_inc_return(v) (atomic_add_return(1, v))
178 #define atomic_dec_return(v) (atomic_sub_return(1, v))
179 
180 #endif
181