1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. 3 4 #include <linux/spinlock.h> 5 #include <linux/smp.h> 6 #include <linux/mm.h> 7 #include <asm/cache.h> 8 #include <asm/barrier.h> 9 10 #define INS_CACHE (1 << 0) 11 #define CACHE_INV (1 << 4) 12 13 void local_icache_inv_all(void *priv) 14 { 15 mtcr("cr17", INS_CACHE|CACHE_INV); 16 sync_is(); 17 } 18 19 void icache_inv_all(void) 20 { 21 on_each_cpu(local_icache_inv_all, NULL, 1); 22 } 23 24 #ifdef CONFIG_CPU_HAS_ICACHE_INS 25 void icache_inv_range(unsigned long start, unsigned long end) 26 { 27 unsigned long i = start & ~(L1_CACHE_BYTES - 1); 28 29 for (; i < end; i += L1_CACHE_BYTES) 30 asm volatile("icache.iva %0\n"::"r"(i):"memory"); 31 sync_is(); 32 } 33 #else 34 void icache_inv_range(unsigned long start, unsigned long end) 35 { 36 icache_inv_all(); 37 } 38 #endif 39 40 inline void dcache_wb_line(unsigned long start) 41 { 42 asm volatile("dcache.cval1 %0\n"::"r"(start):"memory"); 43 sync_is(); 44 } 45 46 void dcache_wb_range(unsigned long start, unsigned long end) 47 { 48 unsigned long i = start & ~(L1_CACHE_BYTES - 1); 49 50 for (; i < end; i += L1_CACHE_BYTES) 51 asm volatile("dcache.cval1 %0\n"::"r"(i):"memory"); 52 sync_is(); 53 } 54 55 void cache_wbinv_range(unsigned long start, unsigned long end) 56 { 57 dcache_wb_range(start, end); 58 icache_inv_range(start, end); 59 } 60 EXPORT_SYMBOL(cache_wbinv_range); 61 62 void dma_wbinv_range(unsigned long start, unsigned long end) 63 { 64 unsigned long i = start & ~(L1_CACHE_BYTES - 1); 65 66 for (; i < end; i += L1_CACHE_BYTES) 67 asm volatile("dcache.civa %0\n"::"r"(i):"memory"); 68 sync_is(); 69 } 70 71 void dma_inv_range(unsigned long start, unsigned long end) 72 { 73 unsigned long i = start & ~(L1_CACHE_BYTES - 1); 74 75 for (; i < end; i += L1_CACHE_BYTES) 76 asm volatile("dcache.iva %0\n"::"r"(i):"memory"); 77 sync_is(); 78 } 79 80 void dma_wb_range(unsigned long start, unsigned long end) 81 { 82 unsigned long i = start & ~(L1_CACHE_BYTES - 1); 83 84 for (; i < end; i += L1_CACHE_BYTES) 85 asm volatile("dcache.cva %0\n"::"r"(i):"memory"); 86 sync_is(); 87 } 88