1 /* SPDX-License-Identifier: GPL-2.0 */ 2 // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. 3 4 #ifndef __ASM_CSKY_MMU_CONTEXT_H 5 #define __ASM_CSKY_MMU_CONTEXT_H 6 7 #include <asm-generic/mm_hooks.h> 8 #include <asm/setup.h> 9 #include <asm/page.h> 10 #include <asm/cacheflush.h> 11 #include <asm/tlbflush.h> 12 13 #include <linux/errno.h> 14 #include <linux/sched.h> 15 #include <abi/ckmmu.h> 16 17 #define TLBMISS_HANDLER_SETUP_PGD(pgd) \ 18 setup_pgd(__pa(pgd), false) 19 20 #define TLBMISS_HANDLER_SETUP_PGD_KERNEL(pgd) \ 21 setup_pgd(__pa(pgd), true) 22 23 #define ASID_MASK ((1 << CONFIG_CPU_ASID_BITS) - 1) 24 #define cpu_asid(mm) (atomic64_read(&mm->context.asid) & ASID_MASK) 25 26 #define init_new_context(tsk,mm) ({ atomic64_set(&(mm)->context.asid, 0); 0; }) 27 28 void check_and_switch_context(struct mm_struct *mm, unsigned int cpu); 29 30 static inline void 31 switch_mm(struct mm_struct *prev, struct mm_struct *next, 32 struct task_struct *tsk) 33 { 34 unsigned int cpu = smp_processor_id(); 35 36 if (prev != next) 37 check_and_switch_context(next, cpu); 38 39 TLBMISS_HANDLER_SETUP_PGD(next->pgd); 40 write_mmu_entryhi(next->context.asid.counter); 41 42 flush_icache_deferred(next); 43 } 44 45 #include <asm-generic/mmu_context.h> 46 47 #endif /* __ASM_CSKY_MMU_CONTEXT_H */ 48