1 /* SPDX-License-Identifier: GPL-2.0 */ 2 // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. 3 4 #ifndef __ASM_CSKY_IO_H 5 #define __ASM_CSKY_IO_H 6 7 #include <abi/pgtable-bits.h> 8 #include <linux/types.h> 9 #include <linux/version.h> 10 11 extern void __iomem *ioremap(phys_addr_t offset, size_t size); 12 13 extern void iounmap(void *addr); 14 15 extern int remap_area_pages(unsigned long address, phys_addr_t phys_addr, 16 size_t size, unsigned long flags); 17 18 /* 19 * I/O memory access primitives. Reads are ordered relative to any 20 * following Normal memory access. Writes are ordered relative to any prior 21 * Normal memory access. 22 * 23 * For CACHEV1 (807, 810), store instruction could fast retire, so we need 24 * another mb() to prevent st fast retire. 25 * 26 * For CACHEV2 (860), store instruction with PAGE_ATTR_NO_BUFFERABLE won't 27 * fast retire. 28 */ 29 #define readb(c) ({ u8 __v = readb_relaxed(c); rmb(); __v; }) 30 #define readw(c) ({ u16 __v = readw_relaxed(c); rmb(); __v; }) 31 #define readl(c) ({ u32 __v = readl_relaxed(c); rmb(); __v; }) 32 33 #ifdef CONFIG_CPU_HAS_CACHEV2 34 #define writeb(v,c) ({ wmb(); writeb_relaxed((v),(c)); }) 35 #define writew(v,c) ({ wmb(); writew_relaxed((v),(c)); }) 36 #define writel(v,c) ({ wmb(); writel_relaxed((v),(c)); }) 37 #else 38 #define writeb(v,c) ({ wmb(); writeb_relaxed((v),(c)); mb(); }) 39 #define writew(v,c) ({ wmb(); writew_relaxed((v),(c)); mb(); }) 40 #define writel(v,c) ({ wmb(); writel_relaxed((v),(c)); mb(); }) 41 #endif 42 43 #define ioremap_nocache(phy, sz) ioremap(phy, sz) 44 #define ioremap_wc ioremap_nocache 45 #define ioremap_wt ioremap_nocache 46 47 #include <asm-generic/io.h> 48 49 #endif /* __ASM_CSKY_IO_H */ 50