1 /* SPDX-License-Identifier: GPL-2.0 */ 2 // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. 3 4 #ifndef __ASM_CSKY_BARRIER_H 5 #define __ASM_CSKY_BARRIER_H 6 7 #ifndef __ASSEMBLY__ 8 9 #define nop() asm volatile ("nop\n":::"memory") 10 11 /* 12 * sync: completion barrier, all sync.xx instructions 13 * guarantee the last response recieved by bus transaction 14 * made by ld/st instructions before sync.s 15 * sync.s: inherit from sync, but also shareable to other cores 16 * sync.i: inherit from sync, but also flush cpu pipeline 17 * sync.is: the same with sync.i + sync.s 18 * 19 * bar.brwarw: ordering barrier for all load/store instructions before it 20 * bar.brwarws: ordering barrier for all load/store instructions before it 21 * and shareable to other cores 22 * bar.brar: ordering barrier for all load instructions before it 23 * bar.brars: ordering barrier for all load instructions before it 24 * and shareable to other cores 25 * bar.bwaw: ordering barrier for all store instructions before it 26 * bar.bwaws: ordering barrier for all store instructions before it 27 * and shareable to other cores 28 */ 29 30 #ifdef CONFIG_CPU_HAS_CACHEV2 31 #define mb() asm volatile ("sync.s\n":::"memory") 32 33 #ifdef CONFIG_SMP 34 #define __smp_mb() asm volatile ("bar.brwarws\n":::"memory") 35 #define __smp_rmb() asm volatile ("bar.brars\n":::"memory") 36 #define __smp_wmb() asm volatile ("bar.bwaws\n":::"memory") 37 #endif /* CONFIG_SMP */ 38 39 #define sync_is() asm volatile ("sync.is\n":::"memory") 40 41 #else /* !CONFIG_CPU_HAS_CACHEV2 */ 42 #define mb() asm volatile ("sync\n":::"memory") 43 #endif 44 45 #include <asm-generic/barrier.h> 46 47 #endif /* __ASSEMBLY__ */ 48 #endif /* __ASM_CSKY_BARRIER_H */ 49