1 /* SPDX-License-Identifier: GPL-2.0 */ 2 // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. 3 4 #ifndef __ASM_CSKY_PGTABLE_BITS_H 5 #define __ASM_CSKY_PGTABLE_BITS_H 6 7 /* implemented in software */ 8 #define _PAGE_ACCESSED (1<<7) 9 #define _PAGE_READ (1<<8) 10 #define _PAGE_WRITE (1<<9) 11 #define _PAGE_PRESENT (1<<10) 12 #define _PAGE_MODIFIED (1<<11) 13 14 /* implemented in hardware */ 15 #define _PAGE_GLOBAL (1<<0) 16 #define _PAGE_VALID (1<<1) 17 #define _PAGE_DIRTY (1<<2) 18 19 #define _PAGE_SO (1<<5) 20 #define _PAGE_BUF (1<<6) 21 #define _PAGE_CACHE (1<<3) 22 #define _CACHE_MASK _PAGE_CACHE 23 24 #define _CACHE_CACHED (_PAGE_CACHE | _PAGE_BUF) 25 #define _CACHE_UNCACHED (0) 26 27 #define _PAGE_PROT_NONE _PAGE_WRITE 28 29 /* 30 * Encode and decode a swap entry 31 * 32 * Format of swap PTE: 33 * bit 0: _PAGE_GLOBAL (zero) 34 * bit 1: _PAGE_VALID (zero) 35 * bit 2 - 6: swap type 36 * bit 7 - 8: swap offset[0 - 1] 37 * bit 9: _PAGE_WRITE (zero) 38 * bit 10: _PAGE_PRESENT (zero) 39 * bit 11 - 31: swap offset[2 - 22] 40 */ 41 #define __swp_type(x) (((x).val >> 2) & 0x1f) 42 #define __swp_offset(x) ((((x).val >> 7) & 0x3) | \ 43 (((x).val >> 9) & 0x7ffffc)) 44 #define __swp_entry(type, offset) ((swp_entry_t) { \ 45 ((type & 0x1f) << 2) | \ 46 ((offset & 0x3) << 7) | \ 47 ((offset & 0x7ffffc) << 9)}) 48 49 #endif /* __ASM_CSKY_PGTABLE_BITS_H */ 50