1 /* SPDX-License-Identifier: GPL-2.0 */ 2 // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. 3 4 #ifndef __ASM_CSKY_ENTRY_H 5 #define __ASM_CSKY_ENTRY_H 6 7 #include <asm/setup.h> 8 #include <abi/regdef.h> 9 10 #define LSAVE_PC 8 11 #define LSAVE_PSR 12 12 #define LSAVE_A0 24 13 #define LSAVE_A1 28 14 #define LSAVE_A2 32 15 #define LSAVE_A3 36 16 #define LSAVE_A4 40 17 #define LSAVE_A5 44 18 19 #define KSPTOUSP 20 #define USPTOKSP 21 22 #define usp cr<14, 1> 23 24 .macro SAVE_ALL epc_inc 25 subi sp, 152 26 stw tls, (sp, 0) 27 stw lr, (sp, 4) 28 29 mfcr lr, epc 30 movi tls, \epc_inc 31 add lr, tls 32 stw lr, (sp, 8) 33 34 mfcr lr, epsr 35 stw lr, (sp, 12) 36 btsti lr, 31 37 bf 1f 38 addi lr, sp, 152 39 br 2f 40 1: 41 mfcr lr, usp 42 2: 43 stw lr, (sp, 16) 44 45 stw a0, (sp, 20) 46 stw a0, (sp, 24) 47 stw a1, (sp, 28) 48 stw a2, (sp, 32) 49 stw a3, (sp, 36) 50 51 addi sp, 40 52 stm r4-r13, (sp) 53 54 addi sp, 40 55 stm r16-r30, (sp) 56 #ifdef CONFIG_CPU_HAS_HILO 57 mfhi lr 58 stw lr, (sp, 60) 59 mflo lr 60 stw lr, (sp, 64) 61 mfcr lr, cr14 62 stw lr, (sp, 68) 63 #endif 64 subi sp, 80 65 .endm 66 67 .macro RESTORE_ALL 68 ldw tls, (sp, 0) 69 ldw lr, (sp, 4) 70 ldw a0, (sp, 8) 71 mtcr a0, epc 72 ldw a0, (sp, 12) 73 mtcr a0, epsr 74 btsti a0, 31 75 ldw a0, (sp, 16) 76 mtcr a0, usp 77 mtcr a0, ss0 78 79 #ifdef CONFIG_CPU_HAS_HILO 80 ldw a0, (sp, 140) 81 mthi a0 82 ldw a0, (sp, 144) 83 mtlo a0 84 ldw a0, (sp, 148) 85 mtcr a0, cr14 86 #endif 87 88 ldw a0, (sp, 24) 89 ldw a1, (sp, 28) 90 ldw a2, (sp, 32) 91 ldw a3, (sp, 36) 92 93 addi sp, 40 94 ldm r4-r13, (sp) 95 addi sp, 40 96 ldm r16-r30, (sp) 97 addi sp, 72 98 bf 1f 99 mfcr sp, ss0 100 1: 101 rte 102 .endm 103 104 .macro SAVE_REGS_FTRACE 105 subi sp, 152 106 stw tls, (sp, 0) 107 stw lr, (sp, 4) 108 109 mfcr lr, psr 110 stw lr, (sp, 12) 111 112 addi lr, sp, 152 113 stw lr, (sp, 16) 114 115 stw a0, (sp, 20) 116 stw a0, (sp, 24) 117 stw a1, (sp, 28) 118 stw a2, (sp, 32) 119 stw a3, (sp, 36) 120 121 addi sp, 40 122 stm r4-r13, (sp) 123 124 addi sp, 40 125 stm r16-r30, (sp) 126 #ifdef CONFIG_CPU_HAS_HILO 127 mfhi lr 128 stw lr, (sp, 60) 129 mflo lr 130 stw lr, (sp, 64) 131 mfcr lr, cr14 132 stw lr, (sp, 68) 133 #endif 134 subi sp, 80 135 .endm 136 137 .macro RESTORE_REGS_FTRACE 138 ldw tls, (sp, 0) 139 ldw a0, (sp, 16) 140 mtcr a0, ss0 141 142 #ifdef CONFIG_CPU_HAS_HILO 143 ldw a0, (sp, 140) 144 mthi a0 145 ldw a0, (sp, 144) 146 mtlo a0 147 ldw a0, (sp, 148) 148 mtcr a0, cr14 149 #endif 150 151 ldw a0, (sp, 24) 152 ldw a1, (sp, 28) 153 ldw a2, (sp, 32) 154 ldw a3, (sp, 36) 155 156 addi sp, 40 157 ldm r4-r13, (sp) 158 addi sp, 40 159 ldm r16-r30, (sp) 160 addi sp, 72 161 mfcr sp, ss0 162 .endm 163 164 .macro SAVE_SWITCH_STACK 165 subi sp, 64 166 stm r4-r11, (sp) 167 stw lr, (sp, 32) 168 stw r16, (sp, 36) 169 stw r17, (sp, 40) 170 stw r26, (sp, 44) 171 stw r27, (sp, 48) 172 stw r28, (sp, 52) 173 stw r29, (sp, 56) 174 stw r30, (sp, 60) 175 #ifdef CONFIG_CPU_HAS_HILO 176 subi sp, 16 177 mfhi lr 178 stw lr, (sp, 0) 179 mflo lr 180 stw lr, (sp, 4) 181 mfcr lr, cr14 182 stw lr, (sp, 8) 183 #endif 184 .endm 185 186 .macro RESTORE_SWITCH_STACK 187 #ifdef CONFIG_CPU_HAS_HILO 188 ldw lr, (sp, 0) 189 mthi lr 190 ldw lr, (sp, 4) 191 mtlo lr 192 ldw lr, (sp, 8) 193 mtcr lr, cr14 194 addi sp, 16 195 #endif 196 ldm r4-r11, (sp) 197 ldw lr, (sp, 32) 198 ldw r16, (sp, 36) 199 ldw r17, (sp, 40) 200 ldw r26, (sp, 44) 201 ldw r27, (sp, 48) 202 ldw r28, (sp, 52) 203 ldw r29, (sp, 56) 204 ldw r30, (sp, 60) 205 addi sp, 64 206 .endm 207 208 /* MMU registers operators. */ 209 .macro RD_MIR rx 210 mfcr \rx, cr<0, 15> 211 .endm 212 213 .macro RD_MEH rx 214 mfcr \rx, cr<4, 15> 215 .endm 216 217 .macro RD_MCIR rx 218 mfcr \rx, cr<8, 15> 219 .endm 220 221 .macro RD_PGDR rx 222 mfcr \rx, cr<29, 15> 223 .endm 224 225 .macro RD_PGDR_K rx 226 mfcr \rx, cr<28, 15> 227 .endm 228 229 .macro WR_MEH rx 230 mtcr \rx, cr<4, 15> 231 .endm 232 233 .macro WR_MCIR rx 234 mtcr \rx, cr<8, 15> 235 .endm 236 237 .macro SETUP_MMU 238 /* Init psr and enable ee */ 239 lrw r6, DEFAULT_PSR_VALUE 240 mtcr r6, psr 241 psrset ee 242 243 /* Invalid I/Dcache BTB BHT */ 244 movi r6, 7 245 lsli r6, 16 246 addi r6, (1<<4) | 3 247 mtcr r6, cr17 248 249 /* Invalid all TLB */ 250 bgeni r6, 26 251 mtcr r6, cr<8, 15> /* Set MCIR */ 252 253 /* Check MMU on/off */ 254 mfcr r6, cr18 255 btsti r6, 0 256 bt 1f 257 258 /* MMU off: setup mapping tlb entry */ 259 movi r6, 0 260 mtcr r6, cr<6, 15> /* Set MPR with 4K page size */ 261 262 grs r6, 1f /* Get current pa by PC */ 263 bmaski r7, (PAGE_SHIFT + 1) /* r7 = 0x1fff */ 264 andn r6, r7 265 mtcr r6, cr<4, 15> /* Set MEH */ 266 267 mov r8, r6 268 movi r7, 0x00000006 269 or r8, r7 270 mtcr r8, cr<2, 15> /* Set MEL0 */ 271 movi r7, 0x00001006 272 or r8, r7 273 mtcr r8, cr<3, 15> /* Set MEL1 */ 274 275 bgeni r8, 28 276 mtcr r8, cr<8, 15> /* Set MCIR to write TLB */ 277 278 br 2f 279 1: 280 /* 281 * MMU on: use origin MSA value from bootloader 282 * 283 * cr<30/31, 15> MSA register format: 284 * 31 - 29 | 28 - 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 285 * BA Reserved SH WA B SO SEC C D V 286 */ 287 mfcr r6, cr<30, 15> /* Get MSA0 */ 288 2: 289 lsri r6, 29 290 lsli r6, 29 291 addi r6, 0x1ce 292 mtcr r6, cr<30, 15> /* Set MSA0 */ 293 294 movi r6, 0 295 mtcr r6, cr<31, 15> /* Clr MSA1 */ 296 297 /* enable MMU */ 298 mfcr r6, cr18 299 bseti r6, 0 300 mtcr r6, cr18 301 302 jmpi 3f /* jump to va */ 303 3: 304 .endm 305 #endif /* __ASM_CSKY_ENTRY_H */ 306