1 /* SPDX-License-Identifier: GPL-2.0 */ 2 // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. 3 4 #ifndef __ASM_CSKY_ENTRY_H 5 #define __ASM_CSKY_ENTRY_H 6 7 #include <asm/setup.h> 8 #include <abi/regdef.h> 9 10 #define LSAVE_PC 8 11 #define LSAVE_PSR 12 12 #define LSAVE_A0 24 13 #define LSAVE_A1 28 14 #define LSAVE_A2 32 15 #define LSAVE_A3 36 16 17 #define EPC_INCREASE 4 18 #define EPC_KEEP 0 19 20 #define KSPTOUSP 21 #define USPTOKSP 22 23 #define usp cr<14, 1> 24 25 .macro INCTRAP rx 26 addi \rx, EPC_INCREASE 27 .endm 28 29 .macro SAVE_ALL epc_inc 30 subi sp, 152 31 stw tls, (sp, 0) 32 stw lr, (sp, 4) 33 34 mfcr lr, epc 35 movi tls, \epc_inc 36 add lr, tls 37 stw lr, (sp, 8) 38 39 mfcr lr, epsr 40 stw lr, (sp, 12) 41 mfcr lr, usp 42 stw lr, (sp, 16) 43 44 stw a0, (sp, 20) 45 stw a0, (sp, 24) 46 stw a1, (sp, 28) 47 stw a2, (sp, 32) 48 stw a3, (sp, 36) 49 50 addi sp, 40 51 stm r4-r13, (sp) 52 53 addi sp, 40 54 stm r16-r30, (sp) 55 #ifdef CONFIG_CPU_HAS_HILO 56 mfhi lr 57 stw lr, (sp, 60) 58 mflo lr 59 stw lr, (sp, 64) 60 #endif 61 subi sp, 80 62 .endm 63 64 .macro RESTORE_ALL 65 psrclr ie 66 ldw tls, (sp, 0) 67 ldw lr, (sp, 4) 68 ldw a0, (sp, 8) 69 mtcr a0, epc 70 ldw a0, (sp, 12) 71 mtcr a0, epsr 72 ldw a0, (sp, 16) 73 mtcr a0, usp 74 75 #ifdef CONFIG_CPU_HAS_HILO 76 ldw a0, (sp, 140) 77 mthi a0 78 ldw a0, (sp, 144) 79 mtlo a0 80 #endif 81 82 ldw a0, (sp, 24) 83 ldw a1, (sp, 28) 84 ldw a2, (sp, 32) 85 ldw a3, (sp, 36) 86 87 addi sp, 40 88 ldm r4-r13, (sp) 89 addi sp, 40 90 ldm r16-r30, (sp) 91 addi sp, 72 92 rte 93 .endm 94 95 .macro SAVE_SWITCH_STACK 96 subi sp, 64 97 stm r4-r11, (sp) 98 stw r15, (sp, 32) 99 stw r16, (sp, 36) 100 stw r17, (sp, 40) 101 stw r26, (sp, 44) 102 stw r27, (sp, 48) 103 stw r28, (sp, 52) 104 stw r29, (sp, 56) 105 stw r30, (sp, 60) 106 .endm 107 108 .macro RESTORE_SWITCH_STACK 109 ldm r4-r11, (sp) 110 ldw r15, (sp, 32) 111 ldw r16, (sp, 36) 112 ldw r17, (sp, 40) 113 ldw r26, (sp, 44) 114 ldw r27, (sp, 48) 115 ldw r28, (sp, 52) 116 ldw r29, (sp, 56) 117 ldw r30, (sp, 60) 118 addi sp, 64 119 .endm 120 121 /* MMU registers operators. */ 122 .macro RD_MIR rx 123 mfcr \rx, cr<0, 15> 124 .endm 125 126 .macro RD_MEH rx 127 mfcr \rx, cr<4, 15> 128 .endm 129 130 .macro RD_MCIR rx 131 mfcr \rx, cr<8, 15> 132 .endm 133 134 .macro RD_PGDR rx 135 mfcr \rx, cr<29, 15> 136 .endm 137 138 .macro RD_PGDR_K rx 139 mfcr \rx, cr<28, 15> 140 .endm 141 142 .macro WR_MEH rx 143 mtcr \rx, cr<4, 15> 144 .endm 145 146 .macro WR_MCIR rx 147 mtcr \rx, cr<8, 15> 148 .endm 149 150 .macro SETUP_MMU rx 151 lrw \rx, PHYS_OFFSET | 0xe 152 mtcr \rx, cr<30, 15> 153 lrw \rx, (PHYS_OFFSET + 0x20000000) | 0xe 154 mtcr \rx, cr<31, 15> 155 .endm 156 #endif /* __ASM_CSKY_ENTRY_H */ 157