1081860b9SGuo Ren /* SPDX-License-Identifier: GPL-2.0 */ 2081860b9SGuo Ren // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. 3081860b9SGuo Ren 4081860b9SGuo Ren #ifndef __ASM_CSKY_ENTRY_H 5081860b9SGuo Ren #define __ASM_CSKY_ENTRY_H 6081860b9SGuo Ren 7081860b9SGuo Ren #include <asm/setup.h> 8081860b9SGuo Ren #include <abi/regdef.h> 9081860b9SGuo Ren 10081860b9SGuo Ren #define LSAVE_PC 8 11081860b9SGuo Ren #define LSAVE_PSR 12 12081860b9SGuo Ren #define LSAVE_A0 24 13081860b9SGuo Ren #define LSAVE_A1 28 14081860b9SGuo Ren #define LSAVE_A2 32 15081860b9SGuo Ren #define LSAVE_A3 36 16081860b9SGuo Ren 17081860b9SGuo Ren #define KSPTOUSP 18081860b9SGuo Ren #define USPTOKSP 19081860b9SGuo Ren 20081860b9SGuo Ren #define usp cr<14, 1> 21081860b9SGuo Ren 22081860b9SGuo Ren .macro SAVE_ALL epc_inc 23081860b9SGuo Ren subi sp, 152 24081860b9SGuo Ren stw tls, (sp, 0) 25081860b9SGuo Ren stw lr, (sp, 4) 26081860b9SGuo Ren 27081860b9SGuo Ren mfcr lr, epc 28081860b9SGuo Ren movi tls, \epc_inc 29081860b9SGuo Ren add lr, tls 30081860b9SGuo Ren stw lr, (sp, 8) 31081860b9SGuo Ren 32081860b9SGuo Ren mfcr lr, epsr 33081860b9SGuo Ren stw lr, (sp, 12) 34081860b9SGuo Ren mfcr lr, usp 35081860b9SGuo Ren stw lr, (sp, 16) 36081860b9SGuo Ren 37081860b9SGuo Ren stw a0, (sp, 20) 38081860b9SGuo Ren stw a0, (sp, 24) 39081860b9SGuo Ren stw a1, (sp, 28) 40081860b9SGuo Ren stw a2, (sp, 32) 41081860b9SGuo Ren stw a3, (sp, 36) 42081860b9SGuo Ren 43081860b9SGuo Ren addi sp, 40 44081860b9SGuo Ren stm r4-r13, (sp) 45081860b9SGuo Ren 46081860b9SGuo Ren addi sp, 40 47081860b9SGuo Ren stm r16-r30, (sp) 48081860b9SGuo Ren #ifdef CONFIG_CPU_HAS_HILO 49081860b9SGuo Ren mfhi lr 50081860b9SGuo Ren stw lr, (sp, 60) 51081860b9SGuo Ren mflo lr 52081860b9SGuo Ren stw lr, (sp, 64) 53789154c2SGuo Ren mfcr lr, cr14 54789154c2SGuo Ren stw lr, (sp, 68) 55081860b9SGuo Ren #endif 56081860b9SGuo Ren subi sp, 80 57081860b9SGuo Ren .endm 58081860b9SGuo Ren 59081860b9SGuo Ren .macro RESTORE_ALL 60081860b9SGuo Ren psrclr ie 61081860b9SGuo Ren ldw tls, (sp, 0) 62081860b9SGuo Ren ldw lr, (sp, 4) 63081860b9SGuo Ren ldw a0, (sp, 8) 64081860b9SGuo Ren mtcr a0, epc 65081860b9SGuo Ren ldw a0, (sp, 12) 66081860b9SGuo Ren mtcr a0, epsr 67081860b9SGuo Ren ldw a0, (sp, 16) 68081860b9SGuo Ren mtcr a0, usp 69081860b9SGuo Ren 70081860b9SGuo Ren #ifdef CONFIG_CPU_HAS_HILO 71081860b9SGuo Ren ldw a0, (sp, 140) 72081860b9SGuo Ren mthi a0 73081860b9SGuo Ren ldw a0, (sp, 144) 74081860b9SGuo Ren mtlo a0 75789154c2SGuo Ren ldw a0, (sp, 148) 76789154c2SGuo Ren mtcr a0, cr14 77081860b9SGuo Ren #endif 78081860b9SGuo Ren 79081860b9SGuo Ren ldw a0, (sp, 24) 80081860b9SGuo Ren ldw a1, (sp, 28) 81081860b9SGuo Ren ldw a2, (sp, 32) 82081860b9SGuo Ren ldw a3, (sp, 36) 83081860b9SGuo Ren 84081860b9SGuo Ren addi sp, 40 85081860b9SGuo Ren ldm r4-r13, (sp) 86081860b9SGuo Ren addi sp, 40 87081860b9SGuo Ren ldm r16-r30, (sp) 88081860b9SGuo Ren addi sp, 72 89081860b9SGuo Ren rte 90081860b9SGuo Ren .endm 91081860b9SGuo Ren 92081860b9SGuo Ren .macro SAVE_SWITCH_STACK 93081860b9SGuo Ren subi sp, 64 94081860b9SGuo Ren stm r4-r11, (sp) 95789154c2SGuo Ren stw lr, (sp, 32) 96081860b9SGuo Ren stw r16, (sp, 36) 97081860b9SGuo Ren stw r17, (sp, 40) 98081860b9SGuo Ren stw r26, (sp, 44) 99081860b9SGuo Ren stw r27, (sp, 48) 100081860b9SGuo Ren stw r28, (sp, 52) 101081860b9SGuo Ren stw r29, (sp, 56) 102081860b9SGuo Ren stw r30, (sp, 60) 103789154c2SGuo Ren #ifdef CONFIG_CPU_HAS_HILO 104789154c2SGuo Ren subi sp, 16 105789154c2SGuo Ren mfhi lr 106789154c2SGuo Ren stw lr, (sp, 0) 107789154c2SGuo Ren mflo lr 108789154c2SGuo Ren stw lr, (sp, 4) 109789154c2SGuo Ren mfcr lr, cr14 110789154c2SGuo Ren stw lr, (sp, 8) 111789154c2SGuo Ren #endif 112081860b9SGuo Ren .endm 113081860b9SGuo Ren 114081860b9SGuo Ren .macro RESTORE_SWITCH_STACK 115789154c2SGuo Ren #ifdef CONFIG_CPU_HAS_HILO 116789154c2SGuo Ren ldw lr, (sp, 0) 117789154c2SGuo Ren mthi lr 118789154c2SGuo Ren ldw lr, (sp, 4) 119789154c2SGuo Ren mtlo lr 120789154c2SGuo Ren ldw lr, (sp, 8) 121789154c2SGuo Ren mtcr lr, cr14 122789154c2SGuo Ren addi sp, 16 123789154c2SGuo Ren #endif 124081860b9SGuo Ren ldm r4-r11, (sp) 125789154c2SGuo Ren ldw lr, (sp, 32) 126081860b9SGuo Ren ldw r16, (sp, 36) 127081860b9SGuo Ren ldw r17, (sp, 40) 128081860b9SGuo Ren ldw r26, (sp, 44) 129081860b9SGuo Ren ldw r27, (sp, 48) 130081860b9SGuo Ren ldw r28, (sp, 52) 131081860b9SGuo Ren ldw r29, (sp, 56) 132081860b9SGuo Ren ldw r30, (sp, 60) 133081860b9SGuo Ren addi sp, 64 134081860b9SGuo Ren .endm 135081860b9SGuo Ren 136081860b9SGuo Ren /* MMU registers operators. */ 137081860b9SGuo Ren .macro RD_MIR rx 138081860b9SGuo Ren mfcr \rx, cr<0, 15> 139081860b9SGuo Ren .endm 140081860b9SGuo Ren 141081860b9SGuo Ren .macro RD_MEH rx 142081860b9SGuo Ren mfcr \rx, cr<4, 15> 143081860b9SGuo Ren .endm 144081860b9SGuo Ren 145081860b9SGuo Ren .macro RD_MCIR rx 146081860b9SGuo Ren mfcr \rx, cr<8, 15> 147081860b9SGuo Ren .endm 148081860b9SGuo Ren 149081860b9SGuo Ren .macro RD_PGDR rx 150081860b9SGuo Ren mfcr \rx, cr<29, 15> 151081860b9SGuo Ren .endm 152081860b9SGuo Ren 153081860b9SGuo Ren .macro RD_PGDR_K rx 154081860b9SGuo Ren mfcr \rx, cr<28, 15> 155081860b9SGuo Ren .endm 156081860b9SGuo Ren 157081860b9SGuo Ren .macro WR_MEH rx 158081860b9SGuo Ren mtcr \rx, cr<4, 15> 159081860b9SGuo Ren .endm 160081860b9SGuo Ren 161081860b9SGuo Ren .macro WR_MCIR rx 162081860b9SGuo Ren mtcr \rx, cr<8, 15> 163081860b9SGuo Ren .endm 164081860b9SGuo Ren 165081860b9SGuo Ren .macro SETUP_MMU rx 166f62e3162SGuo Ren /* Check MMU on | off */ 167f62e3162SGuo Ren mfcr \rx, cr18 168f62e3162SGuo Ren btsti \rx, 0 169f62e3162SGuo Ren bt 1f 170f62e3162SGuo Ren grs \rx, 1f 171f62e3162SGuo Ren br 2f 172f62e3162SGuo Ren 1: 173f62e3162SGuo Ren /* 174f62e3162SGuo Ren * cr<30, 15> format: 175f62e3162SGuo Ren * 31 - 29 | 28 - 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 176f62e3162SGuo Ren * BA Reserved SH WA B SO SEC C D V 177f62e3162SGuo Ren */ 178f62e3162SGuo Ren mfcr \rx, cr<30, 15> 179f62e3162SGuo Ren 2: 180f62e3162SGuo Ren lsri \rx, 28 181f62e3162SGuo Ren lsli \rx, 28 182f62e3162SGuo Ren addi \rx, 0x1ce 183081860b9SGuo Ren mtcr \rx, cr<30, 15> 184f62e3162SGuo Ren 185f62e3162SGuo Ren lsri \rx, 28 186f62e3162SGuo Ren addi \rx, 2 187f62e3162SGuo Ren lsli \rx, 28 188f62e3162SGuo Ren addi \rx, 0x1ce 189081860b9SGuo Ren mtcr \rx, cr<31, 15> 190081860b9SGuo Ren .endm 1912f7932b0SGuo Ren 1922f7932b0SGuo Ren .macro ANDI_R3 rx, imm 1932f7932b0SGuo Ren lsri \rx, 3 1942f7932b0SGuo Ren andi \rx, (\imm >> 3) 1952f7932b0SGuo Ren .endm 196081860b9SGuo Ren #endif /* __ASM_CSKY_ENTRY_H */ 197