1081860b9SGuo Ren /* SPDX-License-Identifier: GPL-2.0 */ 2081860b9SGuo Ren 3081860b9SGuo Ren #ifndef __ASM_CSKY_ENTRY_H 4081860b9SGuo Ren #define __ASM_CSKY_ENTRY_H 5081860b9SGuo Ren 6081860b9SGuo Ren #include <asm/setup.h> 7081860b9SGuo Ren #include <abi/regdef.h> 8081860b9SGuo Ren 9081860b9SGuo Ren #define LSAVE_PC 8 10081860b9SGuo Ren #define LSAVE_PSR 12 11081860b9SGuo Ren #define LSAVE_A0 24 12081860b9SGuo Ren #define LSAVE_A1 28 13081860b9SGuo Ren #define LSAVE_A2 32 14081860b9SGuo Ren #define LSAVE_A3 36 15e0bbb538SGuo Ren #define LSAVE_A4 40 16e0bbb538SGuo Ren #define LSAVE_A5 44 17081860b9SGuo Ren 18081860b9SGuo Ren #define KSPTOUSP 19081860b9SGuo Ren #define USPTOKSP 20081860b9SGuo Ren 21081860b9SGuo Ren #define usp cr<14, 1> 22081860b9SGuo Ren 23081860b9SGuo Ren .macro SAVE_ALL epc_inc 24081860b9SGuo Ren subi sp, 152 25081860b9SGuo Ren stw tls, (sp, 0) 26081860b9SGuo Ren stw lr, (sp, 4) 27081860b9SGuo Ren 28*0c8a32eeSGuo Ren RD_MEH lr 29*0c8a32eeSGuo Ren WR_MEH lr 30*0c8a32eeSGuo Ren 31081860b9SGuo Ren mfcr lr, epc 32081860b9SGuo Ren movi tls, \epc_inc 33081860b9SGuo Ren add lr, tls 34081860b9SGuo Ren stw lr, (sp, 8) 35081860b9SGuo Ren 36081860b9SGuo Ren mfcr lr, epsr 37081860b9SGuo Ren stw lr, (sp, 12) 38f8e17c17SGuo Ren btsti lr, 31 39f8e17c17SGuo Ren bf 1f 40f8e17c17SGuo Ren addi lr, sp, 152 41f8e17c17SGuo Ren br 2f 42f8e17c17SGuo Ren 1: 43081860b9SGuo Ren mfcr lr, usp 44f8e17c17SGuo Ren 2: 45081860b9SGuo Ren stw lr, (sp, 16) 46081860b9SGuo Ren 47081860b9SGuo Ren stw a0, (sp, 20) 48081860b9SGuo Ren stw a0, (sp, 24) 49081860b9SGuo Ren stw a1, (sp, 28) 50081860b9SGuo Ren stw a2, (sp, 32) 51081860b9SGuo Ren stw a3, (sp, 36) 52081860b9SGuo Ren 53081860b9SGuo Ren addi sp, 40 54081860b9SGuo Ren stm r4-r13, (sp) 55081860b9SGuo Ren 56081860b9SGuo Ren addi sp, 40 57081860b9SGuo Ren stm r16-r30, (sp) 58081860b9SGuo Ren #ifdef CONFIG_CPU_HAS_HILO 59081860b9SGuo Ren mfhi lr 60081860b9SGuo Ren stw lr, (sp, 60) 61081860b9SGuo Ren mflo lr 62081860b9SGuo Ren stw lr, (sp, 64) 63789154c2SGuo Ren mfcr lr, cr14 64789154c2SGuo Ren stw lr, (sp, 68) 65081860b9SGuo Ren #endif 66081860b9SGuo Ren subi sp, 80 67081860b9SGuo Ren .endm 68081860b9SGuo Ren 69081860b9SGuo Ren .macro RESTORE_ALL 70081860b9SGuo Ren ldw tls, (sp, 0) 71081860b9SGuo Ren ldw lr, (sp, 4) 72081860b9SGuo Ren ldw a0, (sp, 8) 73081860b9SGuo Ren mtcr a0, epc 74081860b9SGuo Ren ldw a0, (sp, 12) 75081860b9SGuo Ren mtcr a0, epsr 76f8e17c17SGuo Ren btsti a0, 31 77081860b9SGuo Ren ldw a0, (sp, 16) 78081860b9SGuo Ren mtcr a0, usp 79f8e17c17SGuo Ren mtcr a0, ss0 80081860b9SGuo Ren 81081860b9SGuo Ren #ifdef CONFIG_CPU_HAS_HILO 82081860b9SGuo Ren ldw a0, (sp, 140) 83081860b9SGuo Ren mthi a0 84081860b9SGuo Ren ldw a0, (sp, 144) 85081860b9SGuo Ren mtlo a0 86789154c2SGuo Ren ldw a0, (sp, 148) 87789154c2SGuo Ren mtcr a0, cr14 88081860b9SGuo Ren #endif 89081860b9SGuo Ren 90081860b9SGuo Ren ldw a0, (sp, 24) 91081860b9SGuo Ren ldw a1, (sp, 28) 92081860b9SGuo Ren ldw a2, (sp, 32) 93081860b9SGuo Ren ldw a3, (sp, 36) 94081860b9SGuo Ren 95081860b9SGuo Ren addi sp, 40 96081860b9SGuo Ren ldm r4-r13, (sp) 97081860b9SGuo Ren addi sp, 40 98081860b9SGuo Ren ldm r16-r30, (sp) 99081860b9SGuo Ren addi sp, 72 100f8e17c17SGuo Ren bf 1f 101f8e17c17SGuo Ren mfcr sp, ss0 102f8e17c17SGuo Ren 1: 103081860b9SGuo Ren rte 104081860b9SGuo Ren .endm 105081860b9SGuo Ren 10689a3927aSGuo Ren .macro SAVE_REGS_FTRACE 10789a3927aSGuo Ren subi sp, 152 10889a3927aSGuo Ren stw tls, (sp, 0) 10989a3927aSGuo Ren stw lr, (sp, 4) 11089a3927aSGuo Ren 11189a3927aSGuo Ren mfcr lr, psr 11289a3927aSGuo Ren stw lr, (sp, 12) 11389a3927aSGuo Ren 11489a3927aSGuo Ren addi lr, sp, 152 11589a3927aSGuo Ren stw lr, (sp, 16) 11689a3927aSGuo Ren 11789a3927aSGuo Ren stw a0, (sp, 20) 11889a3927aSGuo Ren stw a0, (sp, 24) 11989a3927aSGuo Ren stw a1, (sp, 28) 12089a3927aSGuo Ren stw a2, (sp, 32) 12189a3927aSGuo Ren stw a3, (sp, 36) 12289a3927aSGuo Ren 12389a3927aSGuo Ren addi sp, 40 12489a3927aSGuo Ren stm r4-r13, (sp) 12589a3927aSGuo Ren 12689a3927aSGuo Ren addi sp, 40 12789a3927aSGuo Ren stm r16-r30, (sp) 12889a3927aSGuo Ren #ifdef CONFIG_CPU_HAS_HILO 12989a3927aSGuo Ren mfhi lr 13089a3927aSGuo Ren stw lr, (sp, 60) 13189a3927aSGuo Ren mflo lr 13289a3927aSGuo Ren stw lr, (sp, 64) 13389a3927aSGuo Ren mfcr lr, cr14 13489a3927aSGuo Ren stw lr, (sp, 68) 13589a3927aSGuo Ren #endif 13689a3927aSGuo Ren subi sp, 80 13789a3927aSGuo Ren .endm 13889a3927aSGuo Ren 13989a3927aSGuo Ren .macro RESTORE_REGS_FTRACE 14089a3927aSGuo Ren ldw tls, (sp, 0) 14189a3927aSGuo Ren 14289a3927aSGuo Ren #ifdef CONFIG_CPU_HAS_HILO 14389a3927aSGuo Ren ldw a0, (sp, 140) 14489a3927aSGuo Ren mthi a0 14589a3927aSGuo Ren ldw a0, (sp, 144) 14689a3927aSGuo Ren mtlo a0 14789a3927aSGuo Ren ldw a0, (sp, 148) 14889a3927aSGuo Ren mtcr a0, cr14 14989a3927aSGuo Ren #endif 15089a3927aSGuo Ren 15189a3927aSGuo Ren ldw a0, (sp, 24) 15289a3927aSGuo Ren ldw a1, (sp, 28) 15389a3927aSGuo Ren ldw a2, (sp, 32) 15489a3927aSGuo Ren ldw a3, (sp, 36) 15589a3927aSGuo Ren 15689a3927aSGuo Ren addi sp, 40 15789a3927aSGuo Ren ldm r4-r13, (sp) 15889a3927aSGuo Ren addi sp, 40 15989a3927aSGuo Ren ldm r16-r30, (sp) 16089a3927aSGuo Ren addi sp, 72 16189a3927aSGuo Ren .endm 16289a3927aSGuo Ren 163081860b9SGuo Ren .macro SAVE_SWITCH_STACK 164081860b9SGuo Ren subi sp, 64 165081860b9SGuo Ren stm r4-r11, (sp) 166789154c2SGuo Ren stw lr, (sp, 32) 167081860b9SGuo Ren stw r16, (sp, 36) 168081860b9SGuo Ren stw r17, (sp, 40) 169081860b9SGuo Ren stw r26, (sp, 44) 170081860b9SGuo Ren stw r27, (sp, 48) 171081860b9SGuo Ren stw r28, (sp, 52) 172081860b9SGuo Ren stw r29, (sp, 56) 173081860b9SGuo Ren stw r30, (sp, 60) 174789154c2SGuo Ren #ifdef CONFIG_CPU_HAS_HILO 175789154c2SGuo Ren subi sp, 16 176789154c2SGuo Ren mfhi lr 177789154c2SGuo Ren stw lr, (sp, 0) 178789154c2SGuo Ren mflo lr 179789154c2SGuo Ren stw lr, (sp, 4) 180789154c2SGuo Ren mfcr lr, cr14 181789154c2SGuo Ren stw lr, (sp, 8) 182789154c2SGuo Ren #endif 183081860b9SGuo Ren .endm 184081860b9SGuo Ren 185081860b9SGuo Ren .macro RESTORE_SWITCH_STACK 186789154c2SGuo Ren #ifdef CONFIG_CPU_HAS_HILO 187789154c2SGuo Ren ldw lr, (sp, 0) 188789154c2SGuo Ren mthi lr 189789154c2SGuo Ren ldw lr, (sp, 4) 190789154c2SGuo Ren mtlo lr 191789154c2SGuo Ren ldw lr, (sp, 8) 192789154c2SGuo Ren mtcr lr, cr14 193789154c2SGuo Ren addi sp, 16 194789154c2SGuo Ren #endif 195081860b9SGuo Ren ldm r4-r11, (sp) 196789154c2SGuo Ren ldw lr, (sp, 32) 197081860b9SGuo Ren ldw r16, (sp, 36) 198081860b9SGuo Ren ldw r17, (sp, 40) 199081860b9SGuo Ren ldw r26, (sp, 44) 200081860b9SGuo Ren ldw r27, (sp, 48) 201081860b9SGuo Ren ldw r28, (sp, 52) 202081860b9SGuo Ren ldw r29, (sp, 56) 203081860b9SGuo Ren ldw r30, (sp, 60) 204081860b9SGuo Ren addi sp, 64 205081860b9SGuo Ren .endm 206081860b9SGuo Ren 207081860b9SGuo Ren /* MMU registers operators. */ 208081860b9SGuo Ren .macro RD_MIR rx 209081860b9SGuo Ren mfcr \rx, cr<0, 15> 210081860b9SGuo Ren .endm 211081860b9SGuo Ren 212081860b9SGuo Ren .macro RD_MEH rx 213081860b9SGuo Ren mfcr \rx, cr<4, 15> 214081860b9SGuo Ren .endm 215081860b9SGuo Ren 216081860b9SGuo Ren .macro RD_MCIR rx 217081860b9SGuo Ren mfcr \rx, cr<8, 15> 218081860b9SGuo Ren .endm 219081860b9SGuo Ren 220081860b9SGuo Ren .macro RD_PGDR rx 221081860b9SGuo Ren mfcr \rx, cr<29, 15> 222081860b9SGuo Ren .endm 223081860b9SGuo Ren 224081860b9SGuo Ren .macro RD_PGDR_K rx 225081860b9SGuo Ren mfcr \rx, cr<28, 15> 226081860b9SGuo Ren .endm 227081860b9SGuo Ren 228081860b9SGuo Ren .macro WR_MEH rx 229081860b9SGuo Ren mtcr \rx, cr<4, 15> 230081860b9SGuo Ren .endm 231081860b9SGuo Ren 232081860b9SGuo Ren .macro WR_MCIR rx 233081860b9SGuo Ren mtcr \rx, cr<8, 15> 234081860b9SGuo Ren .endm 235081860b9SGuo Ren 236*0c8a32eeSGuo Ren #ifdef CONFIG_PAGE_OFFSET_80000000 237*0c8a32eeSGuo Ren #define MSA_SET cr<30, 15> 238*0c8a32eeSGuo Ren #define MSA_CLR cr<31, 15> 239*0c8a32eeSGuo Ren #endif 240*0c8a32eeSGuo Ren 241*0c8a32eeSGuo Ren #ifdef CONFIG_PAGE_OFFSET_A0000000 242*0c8a32eeSGuo Ren #define MSA_SET cr<31, 15> 243*0c8a32eeSGuo Ren #define MSA_CLR cr<30, 15> 244*0c8a32eeSGuo Ren #endif 245*0c8a32eeSGuo Ren 246205353faSGuo Ren .macro SETUP_MMU 247205353faSGuo Ren /* Init psr and enable ee */ 248205353faSGuo Ren lrw r6, DEFAULT_PSR_VALUE 249205353faSGuo Ren mtcr r6, psr 250205353faSGuo Ren psrset ee 251205353faSGuo Ren 252205353faSGuo Ren /* Invalid I/Dcache BTB BHT */ 253205353faSGuo Ren movi r6, 7 254205353faSGuo Ren lsli r6, 16 255205353faSGuo Ren addi r6, (1<<4) | 3 256205353faSGuo Ren mtcr r6, cr17 257205353faSGuo Ren 258205353faSGuo Ren /* Invalid all TLB */ 259205353faSGuo Ren bgeni r6, 26 260205353faSGuo Ren mtcr r6, cr<8, 15> /* Set MCIR */ 261205353faSGuo Ren 262205353faSGuo Ren /* Check MMU on/off */ 263205353faSGuo Ren mfcr r6, cr18 264205353faSGuo Ren btsti r6, 0 265f62e3162SGuo Ren bt 1f 266205353faSGuo Ren 267205353faSGuo Ren /* MMU off: setup mapping tlb entry */ 268205353faSGuo Ren movi r6, 0 269205353faSGuo Ren mtcr r6, cr<6, 15> /* Set MPR with 4K page size */ 270205353faSGuo Ren 271205353faSGuo Ren grs r6, 1f /* Get current pa by PC */ 272205353faSGuo Ren bmaski r7, (PAGE_SHIFT + 1) /* r7 = 0x1fff */ 273205353faSGuo Ren andn r6, r7 274205353faSGuo Ren mtcr r6, cr<4, 15> /* Set MEH */ 275205353faSGuo Ren 276205353faSGuo Ren mov r8, r6 277205353faSGuo Ren movi r7, 0x00000006 278205353faSGuo Ren or r8, r7 279205353faSGuo Ren mtcr r8, cr<2, 15> /* Set MEL0 */ 280205353faSGuo Ren movi r7, 0x00001006 281205353faSGuo Ren or r8, r7 282205353faSGuo Ren mtcr r8, cr<3, 15> /* Set MEL1 */ 283205353faSGuo Ren 284205353faSGuo Ren bgeni r8, 28 285205353faSGuo Ren mtcr r8, cr<8, 15> /* Set MCIR to write TLB */ 286205353faSGuo Ren 287f62e3162SGuo Ren br 2f 288f62e3162SGuo Ren 1: 289f62e3162SGuo Ren /* 290205353faSGuo Ren * MMU on: use origin MSA value from bootloader 291205353faSGuo Ren * 292205353faSGuo Ren * cr<30/31, 15> MSA register format: 293f62e3162SGuo Ren * 31 - 29 | 28 - 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 294f62e3162SGuo Ren * BA Reserved SH WA B SO SEC C D V 295f62e3162SGuo Ren */ 296*0c8a32eeSGuo Ren mfcr r6, MSA_SET /* Get MSA */ 297f62e3162SGuo Ren 2: 298165f2d28SLiu Yibin lsri r6, 29 299165f2d28SLiu Yibin lsli r6, 29 300205353faSGuo Ren addi r6, 0x1ce 301*0c8a32eeSGuo Ren mtcr r6, MSA_SET /* Set MSA */ 302f62e3162SGuo Ren 303aefd9461SGuo Ren movi r6, 0 304*0c8a32eeSGuo Ren mtcr r6, MSA_CLR /* Clr MSA */ 305205353faSGuo Ren 306205353faSGuo Ren /* enable MMU */ 307205353faSGuo Ren mfcr r6, cr18 308205353faSGuo Ren bseti r6, 0 309205353faSGuo Ren mtcr r6, cr18 310205353faSGuo Ren 311205353faSGuo Ren jmpi 3f /* jump to va */ 312205353faSGuo Ren 3: 313081860b9SGuo Ren .endm 314081860b9SGuo Ren #endif /* __ASM_CSKY_ENTRY_H */ 315