1 /* SPDX-License-Identifier: GPL-2.0 */ 2 // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. 3 4 #ifndef __ASM_CSKY_CKMMUV2_H 5 #define __ASM_CSKY_CKMMUV2_H 6 7 #include <abi/reg_ops.h> 8 #include <asm/barrier.h> 9 10 static inline int read_mmu_index(void) 11 { 12 return mfcr("cr<0, 15>"); 13 } 14 15 static inline void write_mmu_index(int value) 16 { 17 mtcr("cr<0, 15>", value); 18 } 19 20 static inline int read_mmu_entrylo0(void) 21 { 22 return mfcr("cr<2, 15>"); 23 } 24 25 static inline int read_mmu_entrylo1(void) 26 { 27 return mfcr("cr<3, 15>"); 28 } 29 30 static inline void write_mmu_pagemask(int value) 31 { 32 mtcr("cr<6, 15>", value); 33 } 34 35 static inline int read_mmu_entryhi(void) 36 { 37 return mfcr("cr<4, 15>"); 38 } 39 40 static inline void write_mmu_entryhi(int value) 41 { 42 mtcr("cr<4, 15>", value); 43 } 44 45 /* 46 * TLB operations. 47 */ 48 static inline void tlb_probe(void) 49 { 50 mtcr("cr<8, 15>", 0x80000000); 51 } 52 53 static inline void tlb_read(void) 54 { 55 mtcr("cr<8, 15>", 0x40000000); 56 } 57 58 static inline void tlb_invalid_all(void) 59 { 60 #ifdef CONFIG_CPU_HAS_TLBI 61 asm volatile("tlbi.alls\n":::"memory"); 62 sync_is(); 63 #else 64 mtcr("cr<8, 15>", 0x04000000); 65 #endif 66 } 67 68 static inline void tlb_invalid_indexed(void) 69 { 70 mtcr("cr<8, 15>", 0x02000000); 71 } 72 73 /* setup hardrefil pgd */ 74 static inline unsigned long get_pgd(void) 75 { 76 return mfcr("cr<29, 15>"); 77 } 78 79 static inline void setup_pgd(unsigned long pgd, bool kernel) 80 { 81 if (kernel) 82 mtcr("cr<28, 15>", pgd); 83 else 84 mtcr("cr<29, 15>", pgd); 85 } 86 87 #endif /* __ASM_CSKY_CKMMUV2_H */ 88