100a9730eSGuo Ren // SPDX-License-Identifier: GPL-2.0 200a9730eSGuo Ren // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. 300a9730eSGuo Ren 400a9730eSGuo Ren #include <linux/cache.h> 500a9730eSGuo Ren #include <linux/highmem.h> 600a9730eSGuo Ren #include <linux/mm.h> 700a9730eSGuo Ren #include <asm/cache.h> 800a9730eSGuo Ren 900a9730eSGuo Ren void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, 1000a9730eSGuo Ren pte_t *pte) 1100a9730eSGuo Ren { 12d936a7e7SGuo Ren unsigned long addr; 1300a9730eSGuo Ren struct page *page; 1400a9730eSGuo Ren 15*3e455cf5SGuo Ren if (!pfn_valid(pte_pfn(*pte))) 16*3e455cf5SGuo Ren return; 17*3e455cf5SGuo Ren 18d936a7e7SGuo Ren page = pfn_to_page(pte_pfn(*pte)); 19d936a7e7SGuo Ren if (page == ZERO_PAGE(0)) 2000a9730eSGuo Ren return; 2100a9730eSGuo Ren 22d936a7e7SGuo Ren if (test_and_set_bit(PG_dcache_clean, &page->flags)) 2300a9730eSGuo Ren return; 2400a9730eSGuo Ren 2500a9730eSGuo Ren addr = (unsigned long) kmap_atomic(page); 2600a9730eSGuo Ren 27d936a7e7SGuo Ren dcache_wb_range(addr, addr + PAGE_SIZE); 28d936a7e7SGuo Ren 29d936a7e7SGuo Ren if (vma->vm_flags & VM_EXEC) 30d936a7e7SGuo Ren icache_inv_range(addr, addr + PAGE_SIZE); 3100a9730eSGuo Ren 3200a9730eSGuo Ren kunmap_atomic((void *) addr); 3300a9730eSGuo Ren } 34997153b9SGuo Ren 35997153b9SGuo Ren void flush_icache_deferred(struct mm_struct *mm) 36997153b9SGuo Ren { 37997153b9SGuo Ren unsigned int cpu = smp_processor_id(); 38997153b9SGuo Ren cpumask_t *mask = &mm->context.icache_stale_mask; 39997153b9SGuo Ren 40997153b9SGuo Ren if (cpumask_test_cpu(cpu, mask)) { 41997153b9SGuo Ren cpumask_clear_cpu(cpu, mask); 42997153b9SGuo Ren /* 43997153b9SGuo Ren * Ensure the remote hart's writes are visible to this hart. 44997153b9SGuo Ren * This pairs with a barrier in flush_icache_mm. 45997153b9SGuo Ren */ 46997153b9SGuo Ren smp_mb(); 47997153b9SGuo Ren local_icache_inv_all(NULL); 48997153b9SGuo Ren } 49997153b9SGuo Ren } 50997153b9SGuo Ren 51997153b9SGuo Ren void flush_icache_mm_range(struct mm_struct *mm, 52997153b9SGuo Ren unsigned long start, unsigned long end) 53997153b9SGuo Ren { 54997153b9SGuo Ren unsigned int cpu; 55997153b9SGuo Ren cpumask_t others, *mask; 56997153b9SGuo Ren 57997153b9SGuo Ren preempt_disable(); 58997153b9SGuo Ren 59997153b9SGuo Ren #ifdef CONFIG_CPU_HAS_ICACHE_INS 60997153b9SGuo Ren if (mm == current->mm) { 61997153b9SGuo Ren icache_inv_range(start, end); 62997153b9SGuo Ren preempt_enable(); 63997153b9SGuo Ren return; 64997153b9SGuo Ren } 65997153b9SGuo Ren #endif 66997153b9SGuo Ren 67997153b9SGuo Ren /* Mark every hart's icache as needing a flush for this MM. */ 68997153b9SGuo Ren mask = &mm->context.icache_stale_mask; 69997153b9SGuo Ren cpumask_setall(mask); 70997153b9SGuo Ren 71997153b9SGuo Ren /* Flush this hart's I$ now, and mark it as flushed. */ 72997153b9SGuo Ren cpu = smp_processor_id(); 73997153b9SGuo Ren cpumask_clear_cpu(cpu, mask); 74997153b9SGuo Ren local_icache_inv_all(NULL); 75997153b9SGuo Ren 76997153b9SGuo Ren /* 77997153b9SGuo Ren * Flush the I$ of other harts concurrently executing, and mark them as 78997153b9SGuo Ren * flushed. 79997153b9SGuo Ren */ 80997153b9SGuo Ren cpumask_andnot(&others, mm_cpumask(mm), cpumask_of(cpu)); 81997153b9SGuo Ren 82997153b9SGuo Ren if (mm != current->active_mm || !cpumask_empty(&others)) { 83997153b9SGuo Ren on_each_cpu_mask(&others, local_icache_inv_all, NULL, 1); 84997153b9SGuo Ren cpumask_clear(mask); 85997153b9SGuo Ren } 86997153b9SGuo Ren 87997153b9SGuo Ren preempt_enable(); 88997153b9SGuo Ren } 89