1 /* SPDX-License-Identifier: GPL-2.0 */ 2 // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. 3 4 #ifndef __ASM_CSKY_ENTRY_H 5 #define __ASM_CSKY_ENTRY_H 6 7 #include <asm/setup.h> 8 #include <abi/regdef.h> 9 10 #define LSAVE_PC 8 11 #define LSAVE_PSR 12 12 #define LSAVE_A0 24 13 #define LSAVE_A1 28 14 #define LSAVE_A2 32 15 #define LSAVE_A3 36 16 #define LSAVE_A4 40 17 #define LSAVE_A5 44 18 19 #define EPC_INCREASE 2 20 #define EPC_KEEP 0 21 22 .macro USPTOKSP 23 mtcr sp, ss1 24 mfcr sp, ss0 25 .endm 26 27 .macro KSPTOUSP 28 mtcr sp, ss0 29 mfcr sp, ss1 30 .endm 31 32 .macro INCTRAP rx 33 addi \rx, EPC_INCREASE 34 .endm 35 36 .macro SAVE_ALL epc_inc 37 mtcr r13, ss2 38 mfcr r13, epsr 39 btsti r13, 31 40 bt 1f 41 USPTOKSP 42 1: 43 subi sp, 32 44 subi sp, 32 45 subi sp, 16 46 stw r13, (sp, 12) 47 48 stw lr, (sp, 4) 49 50 mfcr lr, epc 51 movi r13, \epc_inc 52 add lr, r13 53 stw lr, (sp, 8) 54 55 mfcr lr, ss1 56 stw lr, (sp, 16) 57 58 stw a0, (sp, 20) 59 stw a0, (sp, 24) 60 stw a1, (sp, 28) 61 stw a2, (sp, 32) 62 stw a3, (sp, 36) 63 64 addi sp, 32 65 addi sp, 8 66 mfcr r13, ss2 67 stw r6, (sp) 68 stw r7, (sp, 4) 69 stw r8, (sp, 8) 70 stw r9, (sp, 12) 71 stw r10, (sp, 16) 72 stw r11, (sp, 20) 73 stw r12, (sp, 24) 74 stw r13, (sp, 28) 75 stw r14, (sp, 32) 76 stw r1, (sp, 36) 77 subi sp, 32 78 subi sp, 8 79 .endm 80 81 .macro RESTORE_ALL 82 psrclr ie 83 ldw lr, (sp, 4) 84 ldw a0, (sp, 8) 85 mtcr a0, epc 86 ldw a0, (sp, 12) 87 mtcr a0, epsr 88 btsti a0, 31 89 ldw a0, (sp, 16) 90 mtcr a0, ss1 91 92 ldw a0, (sp, 24) 93 ldw a1, (sp, 28) 94 ldw a2, (sp, 32) 95 ldw a3, (sp, 36) 96 97 addi sp, 32 98 addi sp, 8 99 ldw r6, (sp) 100 ldw r7, (sp, 4) 101 ldw r8, (sp, 8) 102 ldw r9, (sp, 12) 103 ldw r10, (sp, 16) 104 ldw r11, (sp, 20) 105 ldw r12, (sp, 24) 106 ldw r13, (sp, 28) 107 ldw r14, (sp, 32) 108 ldw r1, (sp, 36) 109 addi sp, 32 110 addi sp, 8 111 112 bt 1f 113 KSPTOUSP 114 1: 115 rte 116 .endm 117 118 .macro SAVE_SWITCH_STACK 119 subi sp, 32 120 stm r8-r15, (sp) 121 .endm 122 123 .macro RESTORE_SWITCH_STACK 124 ldm r8-r15, (sp) 125 addi sp, 32 126 .endm 127 128 /* MMU registers operators. */ 129 .macro RD_MIR rx 130 cprcr \rx, cpcr0 131 .endm 132 133 .macro RD_MEH rx 134 cprcr \rx, cpcr4 135 .endm 136 137 .macro RD_MCIR rx 138 cprcr \rx, cpcr8 139 .endm 140 141 .macro RD_PGDR rx 142 cprcr \rx, cpcr29 143 .endm 144 145 .macro WR_MEH rx 146 cpwcr \rx, cpcr4 147 .endm 148 149 .macro WR_MCIR rx 150 cpwcr \rx, cpcr8 151 .endm 152 153 .macro SETUP_MMU rx 154 lrw \rx, PHYS_OFFSET | 0xe 155 cpwcr \rx, cpcr30 156 lrw \rx, (PHYS_OFFSET + 0x20000000) | 0xe 157 cpwcr \rx, cpcr31 158 .endm 159 160 #endif /* __ASM_CSKY_ENTRY_H */ 161