1 /* SPDX-License-Identifier: GPL-2.0 */ 2 // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. 3 4 #ifndef __ASM_CSKY_ENTRY_H 5 #define __ASM_CSKY_ENTRY_H 6 7 #include <asm/setup.h> 8 #include <abi/regdef.h> 9 10 #define LSAVE_PC 8 11 #define LSAVE_PSR 12 12 #define LSAVE_A0 24 13 #define LSAVE_A1 28 14 #define LSAVE_A2 32 15 #define LSAVE_A3 36 16 #define LSAVE_A4 40 17 #define LSAVE_A5 44 18 19 .macro USPTOKSP 20 mtcr sp, ss1 21 mfcr sp, ss0 22 .endm 23 24 .macro KSPTOUSP 25 mtcr sp, ss0 26 mfcr sp, ss1 27 .endm 28 29 .macro SAVE_ALL epc_inc 30 mtcr r13, ss2 31 mfcr r13, epsr 32 btsti r13, 31 33 bt 1f 34 USPTOKSP 35 1: 36 subi sp, 32 37 subi sp, 32 38 subi sp, 16 39 stw r13, (sp, 12) 40 41 stw lr, (sp, 4) 42 43 mfcr lr, epc 44 movi r13, \epc_inc 45 add lr, r13 46 stw lr, (sp, 8) 47 48 mfcr lr, ss1 49 stw lr, (sp, 16) 50 51 stw a0, (sp, 20) 52 stw a0, (sp, 24) 53 stw a1, (sp, 28) 54 stw a2, (sp, 32) 55 stw a3, (sp, 36) 56 57 addi sp, 32 58 addi sp, 8 59 mfcr r13, ss2 60 stw r6, (sp) 61 stw r7, (sp, 4) 62 stw r8, (sp, 8) 63 stw r9, (sp, 12) 64 stw r10, (sp, 16) 65 stw r11, (sp, 20) 66 stw r12, (sp, 24) 67 stw r13, (sp, 28) 68 stw r14, (sp, 32) 69 stw r1, (sp, 36) 70 subi sp, 32 71 subi sp, 8 72 .endm 73 74 .macro RESTORE_ALL 75 psrclr ie 76 ldw lr, (sp, 4) 77 ldw a0, (sp, 8) 78 mtcr a0, epc 79 ldw a0, (sp, 12) 80 mtcr a0, epsr 81 btsti a0, 31 82 ldw a0, (sp, 16) 83 mtcr a0, ss1 84 85 ldw a0, (sp, 24) 86 ldw a1, (sp, 28) 87 ldw a2, (sp, 32) 88 ldw a3, (sp, 36) 89 90 addi sp, 32 91 addi sp, 8 92 ldw r6, (sp) 93 ldw r7, (sp, 4) 94 ldw r8, (sp, 8) 95 ldw r9, (sp, 12) 96 ldw r10, (sp, 16) 97 ldw r11, (sp, 20) 98 ldw r12, (sp, 24) 99 ldw r13, (sp, 28) 100 ldw r14, (sp, 32) 101 ldw r1, (sp, 36) 102 addi sp, 32 103 addi sp, 8 104 105 bt 1f 106 KSPTOUSP 107 1: 108 rte 109 .endm 110 111 .macro SAVE_SWITCH_STACK 112 subi sp, 32 113 stm r8-r15, (sp) 114 .endm 115 116 .macro RESTORE_SWITCH_STACK 117 ldm r8-r15, (sp) 118 addi sp, 32 119 .endm 120 121 /* MMU registers operators. */ 122 .macro RD_MIR rx 123 cprcr \rx, cpcr0 124 .endm 125 126 .macro RD_MEH rx 127 cprcr \rx, cpcr4 128 .endm 129 130 .macro RD_MCIR rx 131 cprcr \rx, cpcr8 132 .endm 133 134 .macro RD_PGDR rx 135 cprcr \rx, cpcr29 136 .endm 137 138 .macro WR_MEH rx 139 cpwcr \rx, cpcr4 140 .endm 141 142 .macro WR_MCIR rx 143 cpwcr \rx, cpcr8 144 .endm 145 146 .macro SETUP_MMU 147 /* Init psr and enable ee */ 148 lrw r6, DEFAULT_PSR_VALUE 149 mtcr r6, psr 150 psrset ee 151 152 /* Select MMU as co-processor */ 153 cpseti cp15 154 155 /* 156 * cpcr30 format: 157 * 31 - 29 | 28 - 4 | 3 | 2 | 1 | 0 158 * BA Reserved C D V 159 */ 160 cprcr r6, cpcr30 161 lsri r6, 28 162 lsli r6, 28 163 addi r6, 0xe 164 cpwcr r6, cpcr30 165 166 lsri r6, 28 167 addi r6, 2 168 lsli r6, 28 169 addi r6, 0xe 170 cpwcr r6, cpcr31 171 .endm 172 173 .macro ANDI_R3 rx, imm 174 lsri \rx, 3 175 andi \rx, (\imm >> 3) 176 .endm 177 #endif /* __ASM_CSKY_ENTRY_H */ 178