1# SPDX-License-Identifier: GPL-2.0-only 2config CSKY 3 def_bool y 4 select ARCH_32BIT_OFF_T 5 select ARCH_HAS_DMA_PREP_COHERENT 6 select ARCH_HAS_GCOV_PROFILE_ALL 7 select ARCH_HAS_SYNC_DMA_FOR_CPU 8 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 9 select ARCH_USE_BUILTIN_BSWAP 10 select ARCH_USE_QUEUED_RWLOCKS 11 select ARCH_USE_QUEUED_SPINLOCKS 12 select ARCH_HAS_CURRENT_STACK_POINTER 13 select ARCH_INLINE_READ_LOCK if !PREEMPTION 14 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION 15 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION 16 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION 17 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION 18 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION 19 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION 20 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION 21 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION 22 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION 23 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION 24 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION 25 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION 26 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION 27 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION 28 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION 29 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION 30 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION 31 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION 32 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION 33 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION 34 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION 35 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION 36 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION 37 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION 38 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION 39 select ARCH_WANT_FRAME_POINTERS if !CPU_CK610 && $(cc-option,-mbacktrace) 40 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT 41 select COMMON_CLK 42 select CLKSRC_MMIO 43 select CSKY_MPINTC if CPU_CK860 44 select CSKY_MP_TIMER if CPU_CK860 45 select CSKY_APB_INTC 46 select DMA_DIRECT_REMAP 47 select IRQ_DOMAIN 48 select DW_APB_TIMER_OF 49 select GENERIC_IOREMAP 50 select GENERIC_LIB_ASHLDI3 51 select GENERIC_LIB_ASHRDI3 52 select GENERIC_LIB_LSHRDI3 53 select GENERIC_LIB_MULDI3 54 select GENERIC_LIB_CMPDI2 55 select GENERIC_LIB_UCMPDI2 56 select GENERIC_ALLOCATOR 57 select GENERIC_ATOMIC64 58 select GENERIC_CPU_DEVICES 59 select GENERIC_IRQ_CHIP 60 select GENERIC_IRQ_PROBE 61 select GENERIC_IRQ_SHOW 62 select GENERIC_IRQ_MULTI_HANDLER 63 select GENERIC_SCHED_CLOCK 64 select GENERIC_SMP_IDLE_THREAD 65 select GENERIC_TIME_VSYSCALL 66 select GENERIC_VDSO_32 67 select GENERIC_GETTIMEOFDAY 68 select GX6605S_TIMER if CPU_CK610 69 select HAVE_ARCH_TRACEHOOK 70 select HAVE_ARCH_AUDITSYSCALL 71 select HAVE_ARCH_JUMP_LABEL if !CPU_CK610 72 select HAVE_ARCH_JUMP_LABEL_RELATIVE 73 select HAVE_ARCH_MMAP_RND_BITS 74 select HAVE_ARCH_SECCOMP_FILTER 75 select HAVE_CONTEXT_TRACKING_USER 76 select HAVE_VIRT_CPU_ACCOUNTING_GEN 77 select HAVE_DEBUG_BUGVERBOSE 78 select HAVE_DEBUG_KMEMLEAK 79 select HAVE_DYNAMIC_FTRACE 80 select HAVE_DYNAMIC_FTRACE_WITH_REGS 81 select HAVE_GENERIC_VDSO 82 select HAVE_FUNCTION_TRACER 83 select HAVE_FUNCTION_GRAPH_TRACER 84 select HAVE_FUNCTION_ERROR_INJECTION 85 select HAVE_FTRACE_MCOUNT_RECORD 86 select HAVE_KERNEL_GZIP 87 select HAVE_KERNEL_LZO 88 select HAVE_KERNEL_LZMA 89 select HAVE_KPROBES if !CPU_CK610 90 select HAVE_KPROBES_ON_FTRACE if !CPU_CK610 91 select HAVE_KRETPROBES if !CPU_CK610 92 select HAVE_PERF_EVENTS 93 select HAVE_PERF_REGS 94 select HAVE_PERF_USER_STACK_DUMP 95 select HAVE_DMA_CONTIGUOUS 96 select HAVE_REGS_AND_STACK_ACCESS_API 97 select HAVE_STACKPROTECTOR 98 select HAVE_SYSCALL_TRACEPOINTS 99 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU 100 select LOCK_MM_AND_FIND_VMA 101 select MAY_HAVE_SPARSE_IRQ 102 select MODULES_USE_ELF_RELA if MODULES 103 select OF 104 select OF_EARLY_FLATTREE 105 select PERF_USE_VMALLOC if CPU_CK610 106 select RTC_LIB 107 select TIMER_OF 108 select GENERIC_PCI_IOMAP 109 select HAVE_PCI 110 select PCI_DOMAINS_GENERIC if PCI 111 select PCI_SYSCALL if PCI 112 select PCI_MSI if PCI 113 select TRACE_IRQFLAGS_SUPPORT 114 115config LOCKDEP_SUPPORT 116 def_bool y 117 118config ARCH_SUPPORTS_UPROBES 119 def_bool y if !CPU_CK610 120 121config CPU_HAS_CACHEV2 122 bool 123 124config CPU_HAS_FPUV2 125 bool 126 127config CPU_HAS_HILO 128 bool 129 130config CPU_HAS_TLBI 131 bool 132 133config CPU_HAS_LDSTEX 134 bool 135 help 136 For SMP, CPU needs "ldex&stex" instructions for atomic operations. 137 138config CPU_NEED_TLBSYNC 139 bool 140 141config CPU_NEED_SOFTALIGN 142 bool 143 144config CPU_NO_USER_BKPT 145 bool 146 help 147 For abiv2 we couldn't use "trap 1" as user space bkpt in gdbserver, because 148 abiv2 is 16/32bit instruction set and "trap 1" is 32bit. 149 So we need a 16bit instruction as user space bkpt, and it will cause an illegal 150 instruction exception. 151 In kernel we parse the *regs->pc to determine whether to send SIGTRAP or not. 152 153config GENERIC_CALIBRATE_DELAY 154 def_bool y 155 156config GENERIC_CSUM 157 def_bool y 158 159config GENERIC_HWEIGHT 160 def_bool y 161 162config MMU 163 def_bool y 164 165config STACKTRACE_SUPPORT 166 def_bool y 167 168config TIME_LOW_RES 169 def_bool y 170 171config CPU_ASID_BITS 172 int 173 default "8" if (CPU_CK610 || CPU_CK807 || CPU_CK810) 174 default "12" if (CPU_CK860) 175 176config L1_CACHE_SHIFT 177 int 178 default "4" if (CPU_CK610) 179 default "5" if (CPU_CK807 || CPU_CK810) 180 default "6" if (CPU_CK860) 181 182config ARCH_MMAP_RND_BITS_MIN 183 default 8 184 185# max bits determined by the following formula: 186# VA_BITS - PAGE_SHIFT - 3 187config ARCH_MMAP_RND_BITS_MAX 188 default 17 189 190menu "Processor type and features" 191 192choice 193 prompt "CPU MODEL" 194 default CPU_CK807 195 196config CPU_CK610 197 bool "CSKY CPU ck610" 198 select CPU_NEED_TLBSYNC 199 select CPU_NEED_SOFTALIGN 200 select CPU_NO_USER_BKPT 201 202config CPU_CK810 203 bool "CSKY CPU ck810" 204 select CPU_HAS_HILO 205 select CPU_NEED_TLBSYNC 206 207config CPU_CK807 208 bool "CSKY CPU ck807" 209 select CPU_HAS_HILO 210 211config CPU_CK860 212 bool "CSKY CPU ck860" 213 select CPU_HAS_TLBI 214 select CPU_HAS_CACHEV2 215 select CPU_HAS_LDSTEX 216 select CPU_HAS_FPUV2 217endchoice 218 219choice 220 prompt "PAGE OFFSET" 221 default PAGE_OFFSET_80000000 222 223config PAGE_OFFSET_80000000 224 bool "PAGE OFFSET 2G (user:kernel = 2:2)" 225 226config PAGE_OFFSET_A0000000 227 bool "PAGE OFFSET 2.5G (user:kernel = 2.5:1.5)" 228endchoice 229 230config PAGE_OFFSET 231 hex 232 default 0x80000000 if PAGE_OFFSET_80000000 233 default 0xa0000000 if PAGE_OFFSET_A0000000 234choice 235 236 prompt "C-SKY PMU type" 237 depends on PERF_EVENTS 238 depends on CPU_CK807 || CPU_CK810 || CPU_CK860 239 240config CPU_PMU_NONE 241 bool "None" 242 243config CSKY_PMU_V1 244 bool "Performance Monitoring Unit Ver.1" 245 246endchoice 247 248choice 249 prompt "Power Manager Instruction (wait/doze/stop)" 250 default CPU_PM_NONE 251 252config CPU_PM_NONE 253 bool "None" 254 255config CPU_PM_WAIT 256 bool "wait" 257 258config CPU_PM_DOZE 259 bool "doze" 260 261config CPU_PM_STOP 262 bool "stop" 263endchoice 264 265menuconfig HAVE_TCM 266 bool "Tightly-Coupled/Sram Memory" 267 depends on !COMPILE_TEST 268 help 269 The implementation are not only used by TCM (Tightly-Coupled Memory) 270 but also used by sram on SOC bus. It follow existed linux tcm 271 software interface, so that old tcm application codes could be 272 re-used directly. 273 274if HAVE_TCM 275config ITCM_RAM_BASE 276 hex "ITCM ram base" 277 default 0xffffffff 278 279config ITCM_NR_PAGES 280 int "Page count of ITCM size: NR*4KB" 281 range 1 256 282 default 32 283 284config HAVE_DTCM 285 bool "DTCM Support" 286 287config DTCM_RAM_BASE 288 hex "DTCM ram base" 289 depends on HAVE_DTCM 290 default 0xffffffff 291 292config DTCM_NR_PAGES 293 int "Page count of DTCM size: NR*4KB" 294 depends on HAVE_DTCM 295 range 1 256 296 default 32 297endif 298 299config CPU_HAS_VDSP 300 bool "CPU has VDSP coprocessor" 301 depends on CPU_HAS_FPU && CPU_HAS_FPUV2 302 303config CPU_HAS_FPU 304 bool "CPU has FPU coprocessor" 305 depends on CPU_CK807 || CPU_CK810 || CPU_CK860 306 307config CPU_HAS_ICACHE_INS 308 bool "CPU has Icache invalidate instructions" 309 depends on CPU_HAS_CACHEV2 310 311config CPU_HAS_TEE 312 bool "CPU has Trusted Execution Environment" 313 depends on CPU_CK810 314 315config SMP 316 bool "Symmetric Multi-Processing (SMP) support for C-SKY" 317 depends on CPU_CK860 318 default n 319 320config NR_CPUS 321 int "Maximum number of CPUs (2-32)" 322 range 2 32 323 depends on SMP 324 default "4" 325 326config HIGHMEM 327 bool "High Memory Support" 328 depends on !CPU_CK610 329 select KMAP_LOCAL 330 default y 331 332config DRAM_BASE 333 hex "DRAM start addr (the same with memory-section in dts)" 334 default 0x0 335 336config HOTPLUG_CPU 337 bool "Support for hot-pluggable CPUs" 338 select GENERIC_IRQ_MIGRATION 339 depends on SMP 340 help 341 Say Y here to allow turning CPUs off and on. CPUs can be 342 controlled through /sys/devices/system/cpu/cpu1/hotplug/target. 343 344 Say N if you want to disable CPU hotplug. 345 346config HAVE_EFFICIENT_UNALIGNED_STRING_OPS 347 bool "Enable EFFICIENT_UNALIGNED_STRING_OPS for abiv2" 348 depends on CPU_CK807 || CPU_CK810 || CPU_CK860 349 help 350 Say Y here to enable EFFICIENT_UNALIGNED_STRING_OPS. Some CPU models could 351 deal with unaligned access by hardware. 352 353endmenu 354 355source "arch/csky/Kconfig.platforms" 356 357source "kernel/Kconfig.hz" 358