1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Based on arch/arm/mm/proc.S 4 * 5 * Copyright (C) 2001 Deep Blue Solutions Ltd. 6 * Copyright (C) 2012 ARM Ltd. 7 * Author: Catalin Marinas <catalin.marinas@arm.com> 8 */ 9 10#include <linux/init.h> 11#include <linux/linkage.h> 12#include <linux/pgtable.h> 13#include <linux/cfi_types.h> 14#include <asm/assembler.h> 15#include <asm/asm-offsets.h> 16#include <asm/asm_pointer_auth.h> 17#include <asm/hwcap.h> 18#include <asm/kernel-pgtable.h> 19#include <asm/pgtable-hwdef.h> 20#include <asm/cpufeature.h> 21#include <asm/alternative.h> 22#include <asm/smp.h> 23#include <asm/sysreg.h> 24 25#ifdef CONFIG_ARM64_64K_PAGES 26#define TCR_TG_FLAGS TCR_TG0_64K | TCR_TG1_64K 27#elif defined(CONFIG_ARM64_16K_PAGES) 28#define TCR_TG_FLAGS TCR_TG0_16K | TCR_TG1_16K 29#else /* CONFIG_ARM64_4K_PAGES */ 30#define TCR_TG_FLAGS TCR_TG0_4K | TCR_TG1_4K 31#endif 32 33#ifdef CONFIG_RANDOMIZE_BASE 34#define TCR_KASLR_FLAGS TCR_NFD1 35#else 36#define TCR_KASLR_FLAGS 0 37#endif 38 39#define TCR_SMP_FLAGS TCR_SHARED 40 41/* PTWs cacheable, inner/outer WBWA */ 42#define TCR_CACHE_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA 43 44#ifdef CONFIG_KASAN_SW_TAGS 45#define TCR_KASAN_SW_FLAGS TCR_TBI1 | TCR_TBID1 46#else 47#define TCR_KASAN_SW_FLAGS 0 48#endif 49 50#ifdef CONFIG_KASAN_HW_TAGS 51#define TCR_MTE_FLAGS TCR_TCMA1 | TCR_TBI1 | TCR_TBID1 52#else 53/* 54 * The mte_zero_clear_page_tags() implementation uses DC GZVA, which relies on 55 * TBI being enabled at EL1. 56 */ 57#define TCR_MTE_FLAGS TCR_TBI1 | TCR_TBID1 58#endif 59 60/* 61 * Default MAIR_EL1. MT_NORMAL_TAGGED is initially mapped as Normal memory and 62 * changed during __cpu_setup to Normal Tagged if the system supports MTE. 63 */ 64#define MAIR_EL1_SET \ 65 (MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRnE, MT_DEVICE_nGnRnE) | \ 66 MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRE, MT_DEVICE_nGnRE) | \ 67 MAIR_ATTRIDX(MAIR_ATTR_NORMAL_NC, MT_NORMAL_NC) | \ 68 MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL) | \ 69 MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL_TAGGED)) 70 71#ifdef CONFIG_CPU_PM 72/** 73 * cpu_do_suspend - save CPU registers context 74 * 75 * x0: virtual address of context pointer 76 * 77 * This must be kept in sync with struct cpu_suspend_ctx in <asm/suspend.h>. 78 */ 79SYM_FUNC_START(cpu_do_suspend) 80 mrs x2, tpidr_el0 81 mrs x3, tpidrro_el0 82 mrs x4, contextidr_el1 83 mrs x5, osdlr_el1 84 mrs x6, cpacr_el1 85 mrs x7, tcr_el1 86 mrs x8, vbar_el1 87 mrs x9, mdscr_el1 88 mrs x10, oslsr_el1 89 mrs x11, sctlr_el1 90 get_this_cpu_offset x12 91 mrs x13, sp_el0 92 stp x2, x3, [x0] 93 stp x4, x5, [x0, #16] 94 stp x6, x7, [x0, #32] 95 stp x8, x9, [x0, #48] 96 stp x10, x11, [x0, #64] 97 stp x12, x13, [x0, #80] 98 /* 99 * Save x18 as it may be used as a platform register, e.g. by shadow 100 * call stack. 101 */ 102 str x18, [x0, #96] 103 ret 104SYM_FUNC_END(cpu_do_suspend) 105 106/** 107 * cpu_do_resume - restore CPU register context 108 * 109 * x0: Address of context pointer 110 */ 111 .pushsection ".idmap.text", "awx" 112SYM_FUNC_START(cpu_do_resume) 113 ldp x2, x3, [x0] 114 ldp x4, x5, [x0, #16] 115 ldp x6, x8, [x0, #32] 116 ldp x9, x10, [x0, #48] 117 ldp x11, x12, [x0, #64] 118 ldp x13, x14, [x0, #80] 119 /* 120 * Restore x18, as it may be used as a platform register, and clear 121 * the buffer to minimize the risk of exposure when used for shadow 122 * call stack. 123 */ 124 ldr x18, [x0, #96] 125 str xzr, [x0, #96] 126 msr tpidr_el0, x2 127 msr tpidrro_el0, x3 128 msr contextidr_el1, x4 129 msr cpacr_el1, x6 130 131 /* Don't change t0sz here, mask those bits when restoring */ 132 mrs x7, tcr_el1 133 bfi x8, x7, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH 134 135 msr tcr_el1, x8 136 msr vbar_el1, x9 137 138 /* 139 * __cpu_setup() cleared MDSCR_EL1.MDE and friends, before unmasking 140 * debug exceptions. By restoring MDSCR_EL1 here, we may take a debug 141 * exception. Mask them until local_daif_restore() in cpu_suspend() 142 * resets them. 143 */ 144 disable_daif 145 msr mdscr_el1, x10 146 147 msr sctlr_el1, x12 148 set_this_cpu_offset x13 149 msr sp_el0, x14 150 /* 151 * Restore oslsr_el1 by writing oslar_el1 152 */ 153 msr osdlr_el1, x5 154 ubfx x11, x11, #1, #1 155 msr oslar_el1, x11 156 reset_pmuserenr_el0 x0 // Disable PMU access from EL0 157 reset_amuserenr_el0 x0 // Disable AMU access from EL0 158 159alternative_if ARM64_HAS_RAS_EXTN 160 msr_s SYS_DISR_EL1, xzr 161alternative_else_nop_endif 162 163 ptrauth_keys_install_kernel_nosync x14, x1, x2, x3 164 isb 165 ret 166SYM_FUNC_END(cpu_do_resume) 167 .popsection 168#endif 169 170 .pushsection ".idmap.text", "awx" 171 172.macro __idmap_cpu_set_reserved_ttbr1, tmp1, tmp2 173 adrp \tmp1, reserved_pg_dir 174 phys_to_ttbr \tmp2, \tmp1 175 offset_ttbr1 \tmp2, \tmp1 176 msr ttbr1_el1, \tmp2 177 isb 178 tlbi vmalle1 179 dsb nsh 180 isb 181.endm 182 183/* 184 * void idmap_cpu_replace_ttbr1(phys_addr_t ttbr1) 185 * 186 * This is the low-level counterpart to cpu_replace_ttbr1, and should not be 187 * called by anything else. It can only be executed from a TTBR0 mapping. 188 */ 189SYM_TYPED_FUNC_START(idmap_cpu_replace_ttbr1) 190 save_and_disable_daif flags=x2 191 192 __idmap_cpu_set_reserved_ttbr1 x1, x3 193 194 offset_ttbr1 x0, x3 195 msr ttbr1_el1, x0 196 isb 197 198 restore_daif x2 199 200 ret 201SYM_FUNC_END(idmap_cpu_replace_ttbr1) 202 .popsection 203 204#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 205 206#define KPTI_NG_PTE_FLAGS (PTE_ATTRINDX(MT_NORMAL) | SWAPPER_PTE_FLAGS) 207 208 .pushsection ".idmap.text", "awx" 209 210 .macro kpti_mk_tbl_ng, type, num_entries 211 add end_\type\()p, cur_\type\()p, #\num_entries * 8 212.Ldo_\type: 213 ldr \type, [cur_\type\()p] // Load the entry 214 tbz \type, #0, .Lnext_\type // Skip invalid and 215 tbnz \type, #11, .Lnext_\type // non-global entries 216 orr \type, \type, #PTE_NG // Same bit for blocks and pages 217 str \type, [cur_\type\()p] // Update the entry 218 .ifnc \type, pte 219 tbnz \type, #1, .Lderef_\type 220 .endif 221.Lnext_\type: 222 add cur_\type\()p, cur_\type\()p, #8 223 cmp cur_\type\()p, end_\type\()p 224 b.ne .Ldo_\type 225 .endm 226 227 /* 228 * Dereference the current table entry and map it into the temporary 229 * fixmap slot associated with the current level. 230 */ 231 .macro kpti_map_pgtbl, type, level 232 str xzr, [temp_pte, #8 * (\level + 1)] // break before make 233 dsb nshst 234 add pte, temp_pte, #PAGE_SIZE * (\level + 1) 235 lsr pte, pte, #12 236 tlbi vaae1, pte 237 dsb nsh 238 isb 239 240 phys_to_pte pte, cur_\type\()p 241 add cur_\type\()p, temp_pte, #PAGE_SIZE * (\level + 1) 242 orr pte, pte, pte_flags 243 str pte, [temp_pte, #8 * (\level + 1)] 244 dsb nshst 245 .endm 246 247/* 248 * void __kpti_install_ng_mappings(int cpu, int num_secondaries, phys_addr_t temp_pgd, 249 * unsigned long temp_pte_va) 250 * 251 * Called exactly once from stop_machine context by each CPU found during boot. 252 */ 253 .pushsection ".data", "aw", %progbits 254SYM_DATA(__idmap_kpti_flag, .long 1) 255 .popsection 256 257SYM_TYPED_FUNC_START(idmap_kpti_install_ng_mappings) 258 cpu .req w0 259 temp_pte .req x0 260 num_cpus .req w1 261 pte_flags .req x1 262 temp_pgd_phys .req x2 263 swapper_ttb .req x3 264 flag_ptr .req x4 265 cur_pgdp .req x5 266 end_pgdp .req x6 267 pgd .req x7 268 cur_pudp .req x8 269 end_pudp .req x9 270 cur_pmdp .req x11 271 end_pmdp .req x12 272 cur_ptep .req x14 273 end_ptep .req x15 274 pte .req x16 275 valid .req x17 276 277 mov x5, x3 // preserve temp_pte arg 278 mrs swapper_ttb, ttbr1_el1 279 adr_l flag_ptr, __idmap_kpti_flag 280 281 cbnz cpu, __idmap_kpti_secondary 282 283 /* We're the boot CPU. Wait for the others to catch up */ 284 sevl 2851: wfe 286 ldaxr w17, [flag_ptr] 287 eor w17, w17, num_cpus 288 cbnz w17, 1b 289 290 /* Switch to the temporary page tables on this CPU only */ 291 __idmap_cpu_set_reserved_ttbr1 x8, x9 292 offset_ttbr1 temp_pgd_phys, x8 293 msr ttbr1_el1, temp_pgd_phys 294 isb 295 296 mov temp_pte, x5 297 mov pte_flags, #KPTI_NG_PTE_FLAGS 298 299 /* Everybody is enjoying the idmap, so we can rewrite swapper. */ 300 /* PGD */ 301 adrp cur_pgdp, swapper_pg_dir 302 kpti_map_pgtbl pgd, 0 303 kpti_mk_tbl_ng pgd, PTRS_PER_PGD 304 305 /* Ensure all the updated entries are visible to secondary CPUs */ 306 dsb ishst 307 308 /* We're done: fire up swapper_pg_dir again */ 309 __idmap_cpu_set_reserved_ttbr1 x8, x9 310 msr ttbr1_el1, swapper_ttb 311 isb 312 313 /* Set the flag to zero to indicate that we're all done */ 314 str wzr, [flag_ptr] 315 ret 316 317.Lderef_pgd: 318 /* PUD */ 319 .if CONFIG_PGTABLE_LEVELS > 3 320 pud .req x10 321 pte_to_phys cur_pudp, pgd 322 kpti_map_pgtbl pud, 1 323 kpti_mk_tbl_ng pud, PTRS_PER_PUD 324 b .Lnext_pgd 325 .else /* CONFIG_PGTABLE_LEVELS <= 3 */ 326 pud .req pgd 327 .set .Lnext_pud, .Lnext_pgd 328 .endif 329 330.Lderef_pud: 331 /* PMD */ 332 .if CONFIG_PGTABLE_LEVELS > 2 333 pmd .req x13 334 pte_to_phys cur_pmdp, pud 335 kpti_map_pgtbl pmd, 2 336 kpti_mk_tbl_ng pmd, PTRS_PER_PMD 337 b .Lnext_pud 338 .else /* CONFIG_PGTABLE_LEVELS <= 2 */ 339 pmd .req pgd 340 .set .Lnext_pmd, .Lnext_pgd 341 .endif 342 343.Lderef_pmd: 344 /* PTE */ 345 pte_to_phys cur_ptep, pmd 346 kpti_map_pgtbl pte, 3 347 kpti_mk_tbl_ng pte, PTRS_PER_PTE 348 b .Lnext_pmd 349 350 .unreq cpu 351 .unreq temp_pte 352 .unreq num_cpus 353 .unreq pte_flags 354 .unreq temp_pgd_phys 355 .unreq cur_pgdp 356 .unreq end_pgdp 357 .unreq pgd 358 .unreq cur_pudp 359 .unreq end_pudp 360 .unreq pud 361 .unreq cur_pmdp 362 .unreq end_pmdp 363 .unreq pmd 364 .unreq cur_ptep 365 .unreq end_ptep 366 .unreq pte 367 .unreq valid 368 369 /* Secondary CPUs end up here */ 370__idmap_kpti_secondary: 371 /* Uninstall swapper before surgery begins */ 372 __idmap_cpu_set_reserved_ttbr1 x16, x17 373 374 /* Increment the flag to let the boot CPU we're ready */ 3751: ldxr w16, [flag_ptr] 376 add w16, w16, #1 377 stxr w17, w16, [flag_ptr] 378 cbnz w17, 1b 379 380 /* Wait for the boot CPU to finish messing around with swapper */ 381 sevl 3821: wfe 383 ldxr w16, [flag_ptr] 384 cbnz w16, 1b 385 386 /* All done, act like nothing happened */ 387 msr ttbr1_el1, swapper_ttb 388 isb 389 ret 390 391 .unreq swapper_ttb 392 .unreq flag_ptr 393SYM_FUNC_END(idmap_kpti_install_ng_mappings) 394 .popsection 395#endif 396 397/* 398 * __cpu_setup 399 * 400 * Initialise the processor for turning the MMU on. 401 * 402 * Input: 403 * x0 - actual number of VA bits (ignored unless VA_BITS > 48) 404 * Output: 405 * Return in x0 the value of the SCTLR_EL1 register. 406 */ 407 .pushsection ".idmap.text", "awx" 408SYM_FUNC_START(__cpu_setup) 409 tlbi vmalle1 // Invalidate local TLB 410 dsb nsh 411 412 mov x1, #3 << 20 413 msr cpacr_el1, x1 // Enable FP/ASIMD 414 mov x1, #1 << 12 // Reset mdscr_el1 and disable 415 msr mdscr_el1, x1 // access to the DCC from EL0 416 isb // Unmask debug exceptions now, 417 enable_dbg // since this is per-cpu 418 reset_pmuserenr_el0 x1 // Disable PMU access from EL0 419 reset_amuserenr_el0 x1 // Disable AMU access from EL0 420 421 /* 422 * Default values for VMSA control registers. These will be adjusted 423 * below depending on detected CPU features. 424 */ 425 mair .req x17 426 tcr .req x16 427 mov_q mair, MAIR_EL1_SET 428 mov_q tcr, TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \ 429 TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \ 430 TCR_TBI0 | TCR_A1 | TCR_KASAN_SW_FLAGS 431 432#ifdef CONFIG_ARM64_MTE 433 /* 434 * Update MAIR_EL1, GCR_EL1 and TFSR*_EL1 if MTE is supported 435 * (ID_AA64PFR1_EL1[11:8] > 1). 436 */ 437 mrs x10, ID_AA64PFR1_EL1 438 ubfx x10, x10, #ID_AA64PFR1_MTE_SHIFT, #4 439 cmp x10, #ID_AA64PFR1_MTE 440 b.lt 1f 441 442 /* Normal Tagged memory type at the corresponding MAIR index */ 443 mov x10, #MAIR_ATTR_NORMAL_TAGGED 444 bfi mair, x10, #(8 * MT_NORMAL_TAGGED), #8 445 446 mov x10, #KERNEL_GCR_EL1 447 msr_s SYS_GCR_EL1, x10 448 449 /* 450 * If GCR_EL1.RRND=1 is implemented the same way as RRND=0, then 451 * RGSR_EL1.SEED must be non-zero for IRG to produce 452 * pseudorandom numbers. As RGSR_EL1 is UNKNOWN out of reset, we 453 * must initialize it. 454 */ 455 mrs x10, CNTVCT_EL0 456 ands x10, x10, #SYS_RGSR_EL1_SEED_MASK 457 csinc x10, x10, xzr, ne 458 lsl x10, x10, #SYS_RGSR_EL1_SEED_SHIFT 459 msr_s SYS_RGSR_EL1, x10 460 461 /* clear any pending tag check faults in TFSR*_EL1 */ 462 msr_s SYS_TFSR_EL1, xzr 463 msr_s SYS_TFSRE0_EL1, xzr 464 465 /* set the TCR_EL1 bits */ 466 mov_q x10, TCR_MTE_FLAGS 467 orr tcr, tcr, x10 4681: 469#endif 470 tcr_clear_errata_bits tcr, x9, x5 471 472#ifdef CONFIG_ARM64_VA_BITS_52 473 sub x9, xzr, x0 474 add x9, x9, #64 475 tcr_set_t1sz tcr, x9 476#else 477 idmap_get_t0sz x9 478#endif 479 tcr_set_t0sz tcr, x9 480 481 /* 482 * Set the IPS bits in TCR_EL1. 483 */ 484 tcr_compute_pa_size tcr, #TCR_IPS_SHIFT, x5, x6 485#ifdef CONFIG_ARM64_HW_AFDBM 486 /* 487 * Enable hardware update of the Access Flags bit. 488 * Hardware dirty bit management is enabled later, 489 * via capabilities. 490 */ 491 mrs x9, ID_AA64MMFR1_EL1 492 and x9, x9, #0xf 493 cbz x9, 1f 494 orr tcr, tcr, #TCR_HA // hardware Access flag update 4951: 496#endif /* CONFIG_ARM64_HW_AFDBM */ 497 msr mair_el1, mair 498 msr tcr_el1, tcr 499 /* 500 * Prepare SCTLR 501 */ 502 mov_q x0, INIT_SCTLR_EL1_MMU_ON 503 ret // return to head.S 504 505 .unreq mair 506 .unreq tcr 507SYM_FUNC_END(__cpu_setup) 508