1/* 2 * Based on arch/arm/mm/proc.S 3 * 4 * Copyright (C) 2001 Deep Blue Solutions Ltd. 5 * Copyright (C) 2012 ARM Ltd. 6 * Author: Catalin Marinas <catalin.marinas@arm.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21#include <linux/init.h> 22#include <linux/linkage.h> 23#include <asm/assembler.h> 24#include <asm/asm-offsets.h> 25#include <asm/hwcap.h> 26#include <asm/pgtable.h> 27#include <asm/pgtable-hwdef.h> 28#include <asm/cpufeature.h> 29#include <asm/alternative.h> 30 31#ifdef CONFIG_ARM64_64K_PAGES 32#define TCR_TG_FLAGS TCR_TG0_64K | TCR_TG1_64K 33#elif defined(CONFIG_ARM64_16K_PAGES) 34#define TCR_TG_FLAGS TCR_TG0_16K | TCR_TG1_16K 35#else /* CONFIG_ARM64_4K_PAGES */ 36#define TCR_TG_FLAGS TCR_TG0_4K | TCR_TG1_4K 37#endif 38 39#define TCR_SMP_FLAGS TCR_SHARED 40 41/* PTWs cacheable, inner/outer WBWA */ 42#define TCR_CACHE_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA 43 44#define MAIR(attr, mt) ((attr) << ((mt) * 8)) 45 46/* 47 * cpu_do_idle() 48 * 49 * Idle the processor (wait for interrupt). 50 */ 51ENTRY(cpu_do_idle) 52 dsb sy // WFI may enter a low-power mode 53 wfi 54 ret 55ENDPROC(cpu_do_idle) 56 57#ifdef CONFIG_CPU_PM 58/** 59 * cpu_do_suspend - save CPU registers context 60 * 61 * x0: virtual address of context pointer 62 */ 63ENTRY(cpu_do_suspend) 64 mrs x2, tpidr_el0 65 mrs x3, tpidrro_el0 66 mrs x4, contextidr_el1 67 mrs x5, cpacr_el1 68 mrs x6, tcr_el1 69 mrs x7, vbar_el1 70 mrs x8, mdscr_el1 71 mrs x9, oslsr_el1 72 mrs x10, sctlr_el1 73 stp x2, x3, [x0] 74 stp x4, xzr, [x0, #16] 75 stp x5, x6, [x0, #32] 76 stp x7, x8, [x0, #48] 77 stp x9, x10, [x0, #64] 78 ret 79ENDPROC(cpu_do_suspend) 80 81/** 82 * cpu_do_resume - restore CPU register context 83 * 84 * x0: Address of context pointer 85 */ 86 .pushsection ".idmap.text", "ax" 87ENTRY(cpu_do_resume) 88 ldp x2, x3, [x0] 89 ldp x4, x5, [x0, #16] 90 ldp x6, x8, [x0, #32] 91 ldp x9, x10, [x0, #48] 92 ldp x11, x12, [x0, #64] 93 msr tpidr_el0, x2 94 msr tpidrro_el0, x3 95 msr contextidr_el1, x4 96 msr cpacr_el1, x6 97 98 /* Don't change t0sz here, mask those bits when restoring */ 99 mrs x5, tcr_el1 100 bfi x8, x5, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH 101 102 msr tcr_el1, x8 103 msr vbar_el1, x9 104 105 /* 106 * __cpu_setup() cleared MDSCR_EL1.MDE and friends, before unmasking 107 * debug exceptions. By restoring MDSCR_EL1 here, we may take a debug 108 * exception. Mask them until local_dbg_restore() in cpu_suspend() 109 * resets them. 110 */ 111 disable_dbg 112 msr mdscr_el1, x10 113 114 msr sctlr_el1, x12 115 /* 116 * Restore oslsr_el1 by writing oslar_el1 117 */ 118 ubfx x11, x11, #1, #1 119 msr oslar_el1, x11 120 reset_pmuserenr_el0 x0 // Disable PMU access from EL0 121 isb 122 ret 123ENDPROC(cpu_do_resume) 124 .popsection 125#endif 126 127/* 128 * cpu_do_switch_mm(pgd_phys, tsk) 129 * 130 * Set the translation table base pointer to be pgd_phys. 131 * 132 * - pgd_phys - physical address of new TTB 133 */ 134ENTRY(cpu_do_switch_mm) 135 mmid x1, x1 // get mm->context.id 136 bfi x0, x1, #48, #16 // set the ASID 137 msr ttbr0_el1, x0 // set TTBR0 138 isb 139alternative_if ARM64_WORKAROUND_CAVIUM_27456 140 ic iallu 141 dsb nsh 142 isb 143alternative_else_nop_endif 144 ret 145ENDPROC(cpu_do_switch_mm) 146 147 .pushsection ".idmap.text", "ax" 148/* 149 * void idmap_cpu_replace_ttbr1(phys_addr_t new_pgd) 150 * 151 * This is the low-level counterpart to cpu_replace_ttbr1, and should not be 152 * called by anything else. It can only be executed from a TTBR0 mapping. 153 */ 154ENTRY(idmap_cpu_replace_ttbr1) 155 mrs x2, daif 156 msr daifset, #0xf 157 158 adrp x1, empty_zero_page 159 msr ttbr1_el1, x1 160 isb 161 162 tlbi vmalle1 163 dsb nsh 164 isb 165 166 msr ttbr1_el1, x0 167 isb 168 169 msr daif, x2 170 171 ret 172ENDPROC(idmap_cpu_replace_ttbr1) 173 .popsection 174 175/* 176 * __cpu_setup 177 * 178 * Initialise the processor for turning the MMU on. Return in x0 the 179 * value of the SCTLR_EL1 register. 180 */ 181 .pushsection ".idmap.text", "ax" 182ENTRY(__cpu_setup) 183 tlbi vmalle1 // Invalidate local TLB 184 dsb nsh 185 186 mov x0, #3 << 20 187 msr cpacr_el1, x0 // Enable FP/ASIMD 188 mov x0, #1 << 12 // Reset mdscr_el1 and disable 189 msr mdscr_el1, x0 // access to the DCC from EL0 190 isb // Unmask debug exceptions now, 191 enable_dbg // since this is per-cpu 192 reset_pmuserenr_el0 x0 // Disable PMU access from EL0 193 /* 194 * Memory region attributes for LPAE: 195 * 196 * n = AttrIndx[2:0] 197 * n MAIR 198 * DEVICE_nGnRnE 000 00000000 199 * DEVICE_nGnRE 001 00000100 200 * DEVICE_GRE 010 00001100 201 * NORMAL_NC 011 01000100 202 * NORMAL 100 11111111 203 * NORMAL_WT 101 10111011 204 */ 205 ldr x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \ 206 MAIR(0x04, MT_DEVICE_nGnRE) | \ 207 MAIR(0x0c, MT_DEVICE_GRE) | \ 208 MAIR(0x44, MT_NORMAL_NC) | \ 209 MAIR(0xff, MT_NORMAL) | \ 210 MAIR(0xbb, MT_NORMAL_WT) 211 msr mair_el1, x5 212 /* 213 * Prepare SCTLR 214 */ 215 adr x5, crval 216 ldp w5, w6, [x5] 217 mrs x0, sctlr_el1 218 bic x0, x0, x5 // clear bits 219 orr x0, x0, x6 // set bits 220 /* 221 * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for 222 * both user and kernel. 223 */ 224 ldr x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \ 225 TCR_TG_FLAGS | TCR_ASID16 | TCR_TBI0 226 tcr_set_idmap_t0sz x10, x9 227 228 /* 229 * Read the PARange bits from ID_AA64MMFR0_EL1 and set the IPS bits in 230 * TCR_EL1. 231 */ 232 mrs x9, ID_AA64MMFR0_EL1 233 bfi x10, x9, #32, #3 234#ifdef CONFIG_ARM64_HW_AFDBM 235 /* 236 * Hardware update of the Access and Dirty bits. 237 */ 238 mrs x9, ID_AA64MMFR1_EL1 239 and x9, x9, #0xf 240 cbz x9, 2f 241 cmp x9, #2 242 b.lt 1f 243 orr x10, x10, #TCR_HD // hardware Dirty flag update 2441: orr x10, x10, #TCR_HA // hardware Access flag update 2452: 246#endif /* CONFIG_ARM64_HW_AFDBM */ 247 msr tcr_el1, x10 248 ret // return to head.S 249ENDPROC(__cpu_setup) 250 251 /* 252 * We set the desired value explicitly, including those of the 253 * reserved bits. The values of bits EE & E0E were set early in 254 * el2_setup, which are left untouched below. 255 * 256 * n n T 257 * U E WT T UD US IHBS 258 * CE0 XWHW CZ ME TEEA S 259 * .... .IEE .... NEAI TE.I ..AD DEN0 ACAM 260 * 0011 0... 1101 ..0. ..0. 10.. .0.. .... < hardware reserved 261 * .... .1.. .... 01.1 11.1 ..01 0.01 1101 < software settings 262 */ 263 .type crval, #object 264crval: 265 .word 0xfcffffff // clear 266 .word 0x34d5d91d // set 267 .popsection 268