xref: /openbmc/linux/arch/arm64/mm/proc.S (revision c7eff738) 
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Based on arch/arm/mm/proc.S
4 *
5 * Copyright (C) 2001 Deep Blue Solutions Ltd.
6 * Copyright (C) 2012 ARM Ltd.
7 * Author: Catalin Marinas <catalin.marinas@arm.com>
8 */
9
10#include <linux/init.h>
11#include <linux/linkage.h>
12#include <linux/pgtable.h>
13#include <asm/assembler.h>
14#include <asm/asm-offsets.h>
15#include <asm/asm_pointer_auth.h>
16#include <asm/hwcap.h>
17#include <asm/pgtable-hwdef.h>
18#include <asm/cpufeature.h>
19#include <asm/alternative.h>
20#include <asm/smp.h>
21#include <asm/sysreg.h>
22
23#ifdef CONFIG_ARM64_64K_PAGES
24#define TCR_TG_FLAGS	TCR_TG0_64K | TCR_TG1_64K
25#elif defined(CONFIG_ARM64_16K_PAGES)
26#define TCR_TG_FLAGS	TCR_TG0_16K | TCR_TG1_16K
27#else /* CONFIG_ARM64_4K_PAGES */
28#define TCR_TG_FLAGS	TCR_TG0_4K | TCR_TG1_4K
29#endif
30
31#ifdef CONFIG_RANDOMIZE_BASE
32#define TCR_KASLR_FLAGS	TCR_NFD1
33#else
34#define TCR_KASLR_FLAGS	0
35#endif
36
37#define TCR_SMP_FLAGS	TCR_SHARED
38
39/* PTWs cacheable, inner/outer WBWA */
40#define TCR_CACHE_FLAGS	TCR_IRGN_WBWA | TCR_ORGN_WBWA
41
42#ifdef CONFIG_KASAN_SW_TAGS
43#define TCR_KASAN_SW_FLAGS TCR_TBI1 | TCR_TBID1
44#else
45#define TCR_KASAN_SW_FLAGS 0
46#endif
47
48#ifdef CONFIG_KASAN_HW_TAGS
49#define TCR_MTE_FLAGS TCR_TCMA1 | TCR_TBI1 | TCR_TBID1
50#else
51/*
52 * The mte_zero_clear_page_tags() implementation uses DC GZVA, which relies on
53 * TBI being enabled at EL1.
54 */
55#define TCR_MTE_FLAGS TCR_TBI1 | TCR_TBID1
56#endif
57
58/*
59 * Default MAIR_EL1. MT_NORMAL_TAGGED is initially mapped as Normal memory and
60 * changed during __cpu_setup to Normal Tagged if the system supports MTE.
61 */
62#define MAIR_EL1_SET							\
63	(MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRnE, MT_DEVICE_nGnRnE) |	\
64	 MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRE, MT_DEVICE_nGnRE) |	\
65	 MAIR_ATTRIDX(MAIR_ATTR_NORMAL_NC, MT_NORMAL_NC) |		\
66	 MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL) |			\
67	 MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL_TAGGED))
68
69#ifdef CONFIG_CPU_PM
70/**
71 * cpu_do_suspend - save CPU registers context
72 *
73 * x0: virtual address of context pointer
74 *
75 * This must be kept in sync with struct cpu_suspend_ctx in <asm/suspend.h>.
76 */
77SYM_FUNC_START(cpu_do_suspend)
78	mrs	x2, tpidr_el0
79	mrs	x3, tpidrro_el0
80	mrs	x4, contextidr_el1
81	mrs	x5, osdlr_el1
82	mrs	x6, cpacr_el1
83	mrs	x7, tcr_el1
84	mrs	x8, vbar_el1
85	mrs	x9, mdscr_el1
86	mrs	x10, oslsr_el1
87	mrs	x11, sctlr_el1
88	get_this_cpu_offset x12
89	mrs	x13, sp_el0
90	stp	x2, x3, [x0]
91	stp	x4, x5, [x0, #16]
92	stp	x6, x7, [x0, #32]
93	stp	x8, x9, [x0, #48]
94	stp	x10, x11, [x0, #64]
95	stp	x12, x13, [x0, #80]
96	/*
97	 * Save x18 as it may be used as a platform register, e.g. by shadow
98	 * call stack.
99	 */
100	str	x18, [x0, #96]
101	ret
102SYM_FUNC_END(cpu_do_suspend)
103
104/**
105 * cpu_do_resume - restore CPU register context
106 *
107 * x0: Address of context pointer
108 */
109	.pushsection ".idmap.text", "awx"
110SYM_FUNC_START(cpu_do_resume)
111	ldp	x2, x3, [x0]
112	ldp	x4, x5, [x0, #16]
113	ldp	x6, x8, [x0, #32]
114	ldp	x9, x10, [x0, #48]
115	ldp	x11, x12, [x0, #64]
116	ldp	x13, x14, [x0, #80]
117	/*
118	 * Restore x18, as it may be used as a platform register, and clear
119	 * the buffer to minimize the risk of exposure when used for shadow
120	 * call stack.
121	 */
122	ldr	x18, [x0, #96]
123	str	xzr, [x0, #96]
124	msr	tpidr_el0, x2
125	msr	tpidrro_el0, x3
126	msr	contextidr_el1, x4
127	msr	cpacr_el1, x6
128
129	/* Don't change t0sz here, mask those bits when restoring */
130	mrs	x7, tcr_el1
131	bfi	x8, x7, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH
132
133	msr	tcr_el1, x8
134	msr	vbar_el1, x9
135
136	/*
137	 * __cpu_setup() cleared MDSCR_EL1.MDE and friends, before unmasking
138	 * debug exceptions. By restoring MDSCR_EL1 here, we may take a debug
139	 * exception. Mask them until local_daif_restore() in cpu_suspend()
140	 * resets them.
141	 */
142	disable_daif
143	msr	mdscr_el1, x10
144
145	msr	sctlr_el1, x12
146	set_this_cpu_offset x13
147	msr	sp_el0, x14
148	/*
149	 * Restore oslsr_el1 by writing oslar_el1
150	 */
151	msr	osdlr_el1, x5
152	ubfx	x11, x11, #1, #1
153	msr	oslar_el1, x11
154	reset_pmuserenr_el0 x0			// Disable PMU access from EL0
155	reset_amuserenr_el0 x0			// Disable AMU access from EL0
156
157alternative_if ARM64_HAS_RAS_EXTN
158	msr_s	SYS_DISR_EL1, xzr
159alternative_else_nop_endif
160
161	ptrauth_keys_install_kernel_nosync x14, x1, x2, x3
162	isb
163	ret
164SYM_FUNC_END(cpu_do_resume)
165	.popsection
166#endif
167
168	.pushsection ".idmap.text", "awx"
169
170.macro	__idmap_cpu_set_reserved_ttbr1, tmp1, tmp2
171	adrp	\tmp1, reserved_pg_dir
172	phys_to_ttbr \tmp2, \tmp1
173	offset_ttbr1 \tmp2, \tmp1
174	msr	ttbr1_el1, \tmp2
175	isb
176	tlbi	vmalle1
177	dsb	nsh
178	isb
179.endm
180
181/*
182 * void idmap_cpu_replace_ttbr1(phys_addr_t ttbr1)
183 *
184 * This is the low-level counterpart to cpu_replace_ttbr1, and should not be
185 * called by anything else. It can only be executed from a TTBR0 mapping.
186 */
187SYM_FUNC_START(idmap_cpu_replace_ttbr1)
188	save_and_disable_daif flags=x2
189
190	__idmap_cpu_set_reserved_ttbr1 x1, x3
191
192	offset_ttbr1 x0, x3
193	msr	ttbr1_el1, x0
194	isb
195
196	restore_daif x2
197
198	ret
199SYM_FUNC_END(idmap_cpu_replace_ttbr1)
200	.popsection
201
202#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
203	.pushsection ".idmap.text", "awx"
204
205	.macro	kpti_mk_tbl_ng, type, num_entries
206	add	end_\type\()p, cur_\type\()p, #\num_entries * 8
207.Ldo_\type:
208	dc	cvac, cur_\type\()p		// Ensure any existing dirty
209	dmb	sy				// lines are written back before
210	ldr	\type, [cur_\type\()p]		// loading the entry
211	tbz	\type, #0, .Lnext_\type		// Skip invalid and
212	tbnz	\type, #11, .Lnext_\type	// non-global entries
213	orr	\type, \type, #PTE_NG		// Same bit for blocks and pages
214	str	\type, [cur_\type\()p]		// Update the entry and ensure
215	dmb	sy				// that it is visible to all
216	dc	civac, cur_\()\type\()p		// CPUs.
217	.ifnc	\type, pte
218	tbnz	\type, #1, .Lderef_\type
219	.endif
220.Lnext_\type:
221	add	cur_\type\()p, cur_\type\()p, #8
222	cmp	cur_\type\()p, end_\type\()p
223	b.ne	.Ldo_\type
224	.endm
225
226/*
227 * void __kpti_install_ng_mappings(int cpu, int num_cpus, phys_addr_t swapper)
228 *
229 * Called exactly once from stop_machine context by each CPU found during boot.
230 */
231__idmap_kpti_flag:
232	.long	1
233SYM_FUNC_START(idmap_kpti_install_ng_mappings)
234	cpu		.req	w0
235	num_cpus	.req	w1
236	swapper_pa	.req	x2
237	swapper_ttb	.req	x3
238	flag_ptr	.req	x4
239	cur_pgdp	.req	x5
240	end_pgdp	.req	x6
241	pgd		.req	x7
242	cur_pudp	.req	x8
243	end_pudp	.req	x9
244	cur_pmdp	.req	x11
245	end_pmdp	.req	x12
246	cur_ptep	.req	x14
247	end_ptep	.req	x15
248	pte		.req	x16
249
250	mrs	swapper_ttb, ttbr1_el1
251	restore_ttbr1	swapper_ttb
252	adr	flag_ptr, __idmap_kpti_flag
253
254	cbnz	cpu, __idmap_kpti_secondary
255
256	/* We're the boot CPU. Wait for the others to catch up */
257	sevl
2581:	wfe
259	ldaxr	w17, [flag_ptr]
260	eor	w17, w17, num_cpus
261	cbnz	w17, 1b
262
263	/* We need to walk swapper, so turn off the MMU. */
264	pre_disable_mmu_workaround
265	mrs	x17, sctlr_el1
266	bic	x17, x17, #SCTLR_ELx_M
267	msr	sctlr_el1, x17
268	isb
269
270	/* Everybody is enjoying the idmap, so we can rewrite swapper. */
271	/* PGD */
272	mov		cur_pgdp, swapper_pa
273	kpti_mk_tbl_ng	pgd, PTRS_PER_PGD
274
275	/* Publish the updated tables and nuke all the TLBs */
276	dsb	sy
277	tlbi	vmalle1is
278	dsb	ish
279	isb
280
281	/* We're done: fire up the MMU again */
282	mrs	x17, sctlr_el1
283	orr	x17, x17, #SCTLR_ELx_M
284	set_sctlr_el1	x17
285
286	/* Set the flag to zero to indicate that we're all done */
287	str	wzr, [flag_ptr]
288	ret
289
290.Lderef_pgd:
291	/* PUD */
292	.if		CONFIG_PGTABLE_LEVELS > 3
293	pud		.req	x10
294	pte_to_phys	cur_pudp, pgd
295	kpti_mk_tbl_ng	pud, PTRS_PER_PUD
296	b		.Lnext_pgd
297	.else		/* CONFIG_PGTABLE_LEVELS <= 3 */
298	pud		.req	pgd
299	.set		.Lnext_pud, .Lnext_pgd
300	.endif
301
302.Lderef_pud:
303	/* PMD */
304	.if		CONFIG_PGTABLE_LEVELS > 2
305	pmd		.req	x13
306	pte_to_phys	cur_pmdp, pud
307	kpti_mk_tbl_ng	pmd, PTRS_PER_PMD
308	b		.Lnext_pud
309	.else		/* CONFIG_PGTABLE_LEVELS <= 2 */
310	pmd		.req	pgd
311	.set		.Lnext_pmd, .Lnext_pgd
312	.endif
313
314.Lderef_pmd:
315	/* PTE */
316	pte_to_phys	cur_ptep, pmd
317	kpti_mk_tbl_ng	pte, PTRS_PER_PTE
318	b		.Lnext_pmd
319
320	.unreq	cpu
321	.unreq	num_cpus
322	.unreq	swapper_pa
323	.unreq	cur_pgdp
324	.unreq	end_pgdp
325	.unreq	pgd
326	.unreq	cur_pudp
327	.unreq	end_pudp
328	.unreq	pud
329	.unreq	cur_pmdp
330	.unreq	end_pmdp
331	.unreq	pmd
332	.unreq	cur_ptep
333	.unreq	end_ptep
334	.unreq	pte
335
336	/* Secondary CPUs end up here */
337__idmap_kpti_secondary:
338	/* Uninstall swapper before surgery begins */
339	__idmap_cpu_set_reserved_ttbr1 x16, x17
340
341	/* Increment the flag to let the boot CPU we're ready */
3421:	ldxr	w16, [flag_ptr]
343	add	w16, w16, #1
344	stxr	w17, w16, [flag_ptr]
345	cbnz	w17, 1b
346
347	/* Wait for the boot CPU to finish messing around with swapper */
348	sevl
3491:	wfe
350	ldxr	w16, [flag_ptr]
351	cbnz	w16, 1b
352
353	/* All done, act like nothing happened */
354	offset_ttbr1 swapper_ttb, x16
355	msr	ttbr1_el1, swapper_ttb
356	isb
357	ret
358
359	.unreq	swapper_ttb
360	.unreq	flag_ptr
361SYM_FUNC_END(idmap_kpti_install_ng_mappings)
362	.popsection
363#endif
364
365/*
366 *	__cpu_setup
367 *
368 *	Initialise the processor for turning the MMU on.
369 *
370 * Output:
371 *	Return in x0 the value of the SCTLR_EL1 register.
372 */
373	.pushsection ".idmap.text", "awx"
374SYM_FUNC_START(__cpu_setup)
375	tlbi	vmalle1				// Invalidate local TLB
376	dsb	nsh
377
378	mov	x1, #3 << 20
379	msr	cpacr_el1, x1			// Enable FP/ASIMD
380	mov	x1, #1 << 12			// Reset mdscr_el1 and disable
381	msr	mdscr_el1, x1			// access to the DCC from EL0
382	isb					// Unmask debug exceptions now,
383	enable_dbg				// since this is per-cpu
384	reset_pmuserenr_el0 x1			// Disable PMU access from EL0
385	reset_amuserenr_el0 x1			// Disable AMU access from EL0
386
387	/*
388	 * Default values for VMSA control registers. These will be adjusted
389	 * below depending on detected CPU features.
390	 */
391	mair	.req	x17
392	tcr	.req	x16
393	mov_q	mair, MAIR_EL1_SET
394	mov_q	tcr, TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \
395			TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \
396			TCR_TBI0 | TCR_A1 | TCR_KASAN_SW_FLAGS
397
398#ifdef CONFIG_ARM64_MTE
399	/*
400	 * Update MAIR_EL1, GCR_EL1 and TFSR*_EL1 if MTE is supported
401	 * (ID_AA64PFR1_EL1[11:8] > 1).
402	 */
403	mrs	x10, ID_AA64PFR1_EL1
404	ubfx	x10, x10, #ID_AA64PFR1_MTE_SHIFT, #4
405	cmp	x10, #ID_AA64PFR1_MTE
406	b.lt	1f
407
408	/* Normal Tagged memory type at the corresponding MAIR index */
409	mov	x10, #MAIR_ATTR_NORMAL_TAGGED
410	bfi	mair, x10, #(8 *  MT_NORMAL_TAGGED), #8
411
412	mov	x10, #KERNEL_GCR_EL1
413	msr_s	SYS_GCR_EL1, x10
414
415	/*
416	 * If GCR_EL1.RRND=1 is implemented the same way as RRND=0, then
417	 * RGSR_EL1.SEED must be non-zero for IRG to produce
418	 * pseudorandom numbers. As RGSR_EL1 is UNKNOWN out of reset, we
419	 * must initialize it.
420	 */
421	mrs	x10, CNTVCT_EL0
422	ands	x10, x10, #SYS_RGSR_EL1_SEED_MASK
423	csinc	x10, x10, xzr, ne
424	lsl	x10, x10, #SYS_RGSR_EL1_SEED_SHIFT
425	msr_s	SYS_RGSR_EL1, x10
426
427	/* clear any pending tag check faults in TFSR*_EL1 */
428	msr_s	SYS_TFSR_EL1, xzr
429	msr_s	SYS_TFSRE0_EL1, xzr
430
431	/* set the TCR_EL1 bits */
432	mov_q	x10, TCR_MTE_FLAGS
433	orr	tcr, tcr, x10
4341:
435#endif
436	tcr_clear_errata_bits tcr, x9, x5
437
438#ifdef CONFIG_ARM64_VA_BITS_52
439	ldr_l		x9, vabits_actual
440	sub		x9, xzr, x9
441	add		x9, x9, #64
442	tcr_set_t1sz	tcr, x9
443#else
444	ldr_l		x9, idmap_t0sz
445#endif
446	tcr_set_t0sz	tcr, x9
447
448	/*
449	 * Set the IPS bits in TCR_EL1.
450	 */
451	tcr_compute_pa_size tcr, #TCR_IPS_SHIFT, x5, x6
452#ifdef CONFIG_ARM64_HW_AFDBM
453	/*
454	 * Enable hardware update of the Access Flags bit.
455	 * Hardware dirty bit management is enabled later,
456	 * via capabilities.
457	 */
458	mrs	x9, ID_AA64MMFR1_EL1
459	and	x9, x9, #0xf
460	cbz	x9, 1f
461	orr	tcr, tcr, #TCR_HA		// hardware Access flag update
4621:
463#endif	/* CONFIG_ARM64_HW_AFDBM */
464	msr	mair_el1, mair
465	msr	tcr_el1, tcr
466	/*
467	 * Prepare SCTLR
468	 */
469	mov_q	x0, INIT_SCTLR_EL1_MMU_ON
470	ret					// return to head.S
471
472	.unreq	mair
473	.unreq	tcr
474SYM_FUNC_END(__cpu_setup)
475