1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Based on arch/arm/mm/proc.S 4 * 5 * Copyright (C) 2001 Deep Blue Solutions Ltd. 6 * Copyright (C) 2012 ARM Ltd. 7 * Author: Catalin Marinas <catalin.marinas@arm.com> 8 */ 9 10#include <linux/init.h> 11#include <linux/linkage.h> 12#include <linux/pgtable.h> 13#include <asm/assembler.h> 14#include <asm/asm-offsets.h> 15#include <asm/asm_pointer_auth.h> 16#include <asm/hwcap.h> 17#include <asm/pgtable-hwdef.h> 18#include <asm/cpufeature.h> 19#include <asm/alternative.h> 20#include <asm/smp.h> 21#include <asm/sysreg.h> 22 23#ifdef CONFIG_ARM64_64K_PAGES 24#define TCR_TG_FLAGS TCR_TG0_64K | TCR_TG1_64K 25#elif defined(CONFIG_ARM64_16K_PAGES) 26#define TCR_TG_FLAGS TCR_TG0_16K | TCR_TG1_16K 27#else /* CONFIG_ARM64_4K_PAGES */ 28#define TCR_TG_FLAGS TCR_TG0_4K | TCR_TG1_4K 29#endif 30 31#ifdef CONFIG_RANDOMIZE_BASE 32#define TCR_KASLR_FLAGS TCR_NFD1 33#else 34#define TCR_KASLR_FLAGS 0 35#endif 36 37#define TCR_SMP_FLAGS TCR_SHARED 38 39/* PTWs cacheable, inner/outer WBWA */ 40#define TCR_CACHE_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA 41 42#ifdef CONFIG_KASAN_SW_TAGS 43#define TCR_KASAN_SW_FLAGS TCR_TBI1 | TCR_TBID1 44#else 45#define TCR_KASAN_SW_FLAGS 0 46#endif 47 48#ifdef CONFIG_KASAN_HW_TAGS 49#define TCR_KASAN_HW_FLAGS SYS_TCR_EL1_TCMA1 | TCR_TBI1 | TCR_TBID1 50#else 51#define TCR_KASAN_HW_FLAGS 0 52#endif 53 54/* 55 * Default MAIR_EL1. MT_NORMAL_TAGGED is initially mapped as Normal memory and 56 * changed during __cpu_setup to Normal Tagged if the system supports MTE. 57 */ 58#define MAIR_EL1_SET \ 59 (MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRnE, MT_DEVICE_nGnRnE) | \ 60 MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRE, MT_DEVICE_nGnRE) | \ 61 MAIR_ATTRIDX(MAIR_ATTR_DEVICE_GRE, MT_DEVICE_GRE) | \ 62 MAIR_ATTRIDX(MAIR_ATTR_NORMAL_NC, MT_NORMAL_NC) | \ 63 MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL) | \ 64 MAIR_ATTRIDX(MAIR_ATTR_NORMAL_WT, MT_NORMAL_WT) | \ 65 MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL_TAGGED)) 66 67#ifdef CONFIG_CPU_PM 68/** 69 * cpu_do_suspend - save CPU registers context 70 * 71 * x0: virtual address of context pointer 72 * 73 * This must be kept in sync with struct cpu_suspend_ctx in <asm/suspend.h>. 74 */ 75SYM_FUNC_START(cpu_do_suspend) 76 mrs x2, tpidr_el0 77 mrs x3, tpidrro_el0 78 mrs x4, contextidr_el1 79 mrs x5, osdlr_el1 80 mrs x6, cpacr_el1 81 mrs x7, tcr_el1 82 mrs x8, vbar_el1 83 mrs x9, mdscr_el1 84 mrs x10, oslsr_el1 85 mrs x11, sctlr_el1 86alternative_if_not ARM64_HAS_VIRT_HOST_EXTN 87 mrs x12, tpidr_el1 88alternative_else 89 mrs x12, tpidr_el2 90alternative_endif 91 mrs x13, sp_el0 92 stp x2, x3, [x0] 93 stp x4, x5, [x0, #16] 94 stp x6, x7, [x0, #32] 95 stp x8, x9, [x0, #48] 96 stp x10, x11, [x0, #64] 97 stp x12, x13, [x0, #80] 98 /* 99 * Save x18 as it may be used as a platform register, e.g. by shadow 100 * call stack. 101 */ 102 str x18, [x0, #96] 103 ret 104SYM_FUNC_END(cpu_do_suspend) 105 106/** 107 * cpu_do_resume - restore CPU register context 108 * 109 * x0: Address of context pointer 110 */ 111 .pushsection ".idmap.text", "awx" 112SYM_FUNC_START(cpu_do_resume) 113 ldp x2, x3, [x0] 114 ldp x4, x5, [x0, #16] 115 ldp x6, x8, [x0, #32] 116 ldp x9, x10, [x0, #48] 117 ldp x11, x12, [x0, #64] 118 ldp x13, x14, [x0, #80] 119 /* 120 * Restore x18, as it may be used as a platform register, and clear 121 * the buffer to minimize the risk of exposure when used for shadow 122 * call stack. 123 */ 124 ldr x18, [x0, #96] 125 str xzr, [x0, #96] 126 msr tpidr_el0, x2 127 msr tpidrro_el0, x3 128 msr contextidr_el1, x4 129 msr cpacr_el1, x6 130 131 /* Don't change t0sz here, mask those bits when restoring */ 132 mrs x7, tcr_el1 133 bfi x8, x7, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH 134 135 msr tcr_el1, x8 136 msr vbar_el1, x9 137 138 /* 139 * __cpu_setup() cleared MDSCR_EL1.MDE and friends, before unmasking 140 * debug exceptions. By restoring MDSCR_EL1 here, we may take a debug 141 * exception. Mask them until local_daif_restore() in cpu_suspend() 142 * resets them. 143 */ 144 disable_daif 145 msr mdscr_el1, x10 146 147 msr sctlr_el1, x12 148alternative_if_not ARM64_HAS_VIRT_HOST_EXTN 149 msr tpidr_el1, x13 150alternative_else 151 msr tpidr_el2, x13 152alternative_endif 153 msr sp_el0, x14 154 /* 155 * Restore oslsr_el1 by writing oslar_el1 156 */ 157 msr osdlr_el1, x5 158 ubfx x11, x11, #1, #1 159 msr oslar_el1, x11 160 reset_pmuserenr_el0 x0 // Disable PMU access from EL0 161 reset_amuserenr_el0 x0 // Disable AMU access from EL0 162 163alternative_if ARM64_HAS_RAS_EXTN 164 msr_s SYS_DISR_EL1, xzr 165alternative_else_nop_endif 166 167 ptrauth_keys_install_kernel_nosync x14, x1, x2, x3 168 isb 169 ret 170SYM_FUNC_END(cpu_do_resume) 171 .popsection 172#endif 173 174 .pushsection ".idmap.text", "awx" 175 176.macro __idmap_cpu_set_reserved_ttbr1, tmp1, tmp2 177 adrp \tmp1, reserved_pg_dir 178 phys_to_ttbr \tmp2, \tmp1 179 offset_ttbr1 \tmp2, \tmp1 180 msr ttbr1_el1, \tmp2 181 isb 182 tlbi vmalle1 183 dsb nsh 184 isb 185.endm 186 187/* 188 * void idmap_cpu_replace_ttbr1(phys_addr_t ttbr1) 189 * 190 * This is the low-level counterpart to cpu_replace_ttbr1, and should not be 191 * called by anything else. It can only be executed from a TTBR0 mapping. 192 */ 193SYM_FUNC_START(idmap_cpu_replace_ttbr1) 194 save_and_disable_daif flags=x2 195 196 __idmap_cpu_set_reserved_ttbr1 x1, x3 197 198 offset_ttbr1 x0, x3 199 msr ttbr1_el1, x0 200 isb 201 202 restore_daif x2 203 204 ret 205SYM_FUNC_END(idmap_cpu_replace_ttbr1) 206 .popsection 207 208#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 209 .pushsection ".idmap.text", "awx" 210 211 .macro __idmap_kpti_get_pgtable_ent, type 212 dc cvac, cur_\()\type\()p // Ensure any existing dirty 213 dmb sy // lines are written back before 214 ldr \type, [cur_\()\type\()p] // loading the entry 215 tbz \type, #0, skip_\()\type // Skip invalid and 216 tbnz \type, #11, skip_\()\type // non-global entries 217 .endm 218 219 .macro __idmap_kpti_put_pgtable_ent_ng, type 220 orr \type, \type, #PTE_NG // Same bit for blocks and pages 221 str \type, [cur_\()\type\()p] // Update the entry and ensure 222 dmb sy // that it is visible to all 223 dc civac, cur_\()\type\()p // CPUs. 224 .endm 225 226/* 227 * void __kpti_install_ng_mappings(int cpu, int num_cpus, phys_addr_t swapper) 228 * 229 * Called exactly once from stop_machine context by each CPU found during boot. 230 */ 231__idmap_kpti_flag: 232 .long 1 233SYM_FUNC_START(idmap_kpti_install_ng_mappings) 234 cpu .req w0 235 num_cpus .req w1 236 swapper_pa .req x2 237 swapper_ttb .req x3 238 flag_ptr .req x4 239 cur_pgdp .req x5 240 end_pgdp .req x6 241 pgd .req x7 242 cur_pudp .req x8 243 end_pudp .req x9 244 pud .req x10 245 cur_pmdp .req x11 246 end_pmdp .req x12 247 pmd .req x13 248 cur_ptep .req x14 249 end_ptep .req x15 250 pte .req x16 251 252 mrs swapper_ttb, ttbr1_el1 253 restore_ttbr1 swapper_ttb 254 adr flag_ptr, __idmap_kpti_flag 255 256 cbnz cpu, __idmap_kpti_secondary 257 258 /* We're the boot CPU. Wait for the others to catch up */ 259 sevl 2601: wfe 261 ldaxr w17, [flag_ptr] 262 eor w17, w17, num_cpus 263 cbnz w17, 1b 264 265 /* We need to walk swapper, so turn off the MMU. */ 266 pre_disable_mmu_workaround 267 mrs x17, sctlr_el1 268 bic x17, x17, #SCTLR_ELx_M 269 msr sctlr_el1, x17 270 isb 271 272 /* Everybody is enjoying the idmap, so we can rewrite swapper. */ 273 /* PGD */ 274 mov cur_pgdp, swapper_pa 275 add end_pgdp, cur_pgdp, #(PTRS_PER_PGD * 8) 276do_pgd: __idmap_kpti_get_pgtable_ent pgd 277 tbnz pgd, #1, walk_puds 278next_pgd: 279 __idmap_kpti_put_pgtable_ent_ng pgd 280skip_pgd: 281 add cur_pgdp, cur_pgdp, #8 282 cmp cur_pgdp, end_pgdp 283 b.ne do_pgd 284 285 /* Publish the updated tables and nuke all the TLBs */ 286 dsb sy 287 tlbi vmalle1is 288 dsb ish 289 isb 290 291 /* We're done: fire up the MMU again */ 292 mrs x17, sctlr_el1 293 orr x17, x17, #SCTLR_ELx_M 294 set_sctlr_el1 x17 295 296 /* Set the flag to zero to indicate that we're all done */ 297 str wzr, [flag_ptr] 298 ret 299 300 /* PUD */ 301walk_puds: 302 .if CONFIG_PGTABLE_LEVELS > 3 303 pte_to_phys cur_pudp, pgd 304 add end_pudp, cur_pudp, #(PTRS_PER_PUD * 8) 305do_pud: __idmap_kpti_get_pgtable_ent pud 306 tbnz pud, #1, walk_pmds 307next_pud: 308 __idmap_kpti_put_pgtable_ent_ng pud 309skip_pud: 310 add cur_pudp, cur_pudp, 8 311 cmp cur_pudp, end_pudp 312 b.ne do_pud 313 b next_pgd 314 .else /* CONFIG_PGTABLE_LEVELS <= 3 */ 315 mov pud, pgd 316 b walk_pmds 317next_pud: 318 b next_pgd 319 .endif 320 321 /* PMD */ 322walk_pmds: 323 .if CONFIG_PGTABLE_LEVELS > 2 324 pte_to_phys cur_pmdp, pud 325 add end_pmdp, cur_pmdp, #(PTRS_PER_PMD * 8) 326do_pmd: __idmap_kpti_get_pgtable_ent pmd 327 tbnz pmd, #1, walk_ptes 328next_pmd: 329 __idmap_kpti_put_pgtable_ent_ng pmd 330skip_pmd: 331 add cur_pmdp, cur_pmdp, #8 332 cmp cur_pmdp, end_pmdp 333 b.ne do_pmd 334 b next_pud 335 .else /* CONFIG_PGTABLE_LEVELS <= 2 */ 336 mov pmd, pud 337 b walk_ptes 338next_pmd: 339 b next_pud 340 .endif 341 342 /* PTE */ 343walk_ptes: 344 pte_to_phys cur_ptep, pmd 345 add end_ptep, cur_ptep, #(PTRS_PER_PTE * 8) 346do_pte: __idmap_kpti_get_pgtable_ent pte 347 __idmap_kpti_put_pgtable_ent_ng pte 348skip_pte: 349 add cur_ptep, cur_ptep, #8 350 cmp cur_ptep, end_ptep 351 b.ne do_pte 352 b next_pmd 353 354 .unreq cpu 355 .unreq num_cpus 356 .unreq swapper_pa 357 .unreq cur_pgdp 358 .unreq end_pgdp 359 .unreq pgd 360 .unreq cur_pudp 361 .unreq end_pudp 362 .unreq pud 363 .unreq cur_pmdp 364 .unreq end_pmdp 365 .unreq pmd 366 .unreq cur_ptep 367 .unreq end_ptep 368 .unreq pte 369 370 /* Secondary CPUs end up here */ 371__idmap_kpti_secondary: 372 /* Uninstall swapper before surgery begins */ 373 __idmap_cpu_set_reserved_ttbr1 x16, x17 374 375 /* Increment the flag to let the boot CPU we're ready */ 3761: ldxr w16, [flag_ptr] 377 add w16, w16, #1 378 stxr w17, w16, [flag_ptr] 379 cbnz w17, 1b 380 381 /* Wait for the boot CPU to finish messing around with swapper */ 382 sevl 3831: wfe 384 ldxr w16, [flag_ptr] 385 cbnz w16, 1b 386 387 /* All done, act like nothing happened */ 388 offset_ttbr1 swapper_ttb, x16 389 msr ttbr1_el1, swapper_ttb 390 isb 391 ret 392 393 .unreq swapper_ttb 394 .unreq flag_ptr 395SYM_FUNC_END(idmap_kpti_install_ng_mappings) 396 .popsection 397#endif 398 399/* 400 * __cpu_setup 401 * 402 * Initialise the processor for turning the MMU on. 403 * 404 * Output: 405 * Return in x0 the value of the SCTLR_EL1 register. 406 */ 407 .pushsection ".idmap.text", "awx" 408SYM_FUNC_START(__cpu_setup) 409 tlbi vmalle1 // Invalidate local TLB 410 dsb nsh 411 412 mov x1, #3 << 20 413 msr cpacr_el1, x1 // Enable FP/ASIMD 414 mov x1, #1 << 12 // Reset mdscr_el1 and disable 415 msr mdscr_el1, x1 // access to the DCC from EL0 416 isb // Unmask debug exceptions now, 417 enable_dbg // since this is per-cpu 418 reset_pmuserenr_el0 x1 // Disable PMU access from EL0 419 reset_amuserenr_el0 x1 // Disable AMU access from EL0 420 421 /* 422 * Default values for VMSA control registers. These will be adjusted 423 * below depending on detected CPU features. 424 */ 425 mair .req x17 426 tcr .req x16 427 mov_q mair, MAIR_EL1_SET 428 mov_q tcr, TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \ 429 TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \ 430 TCR_TBI0 | TCR_A1 | TCR_KASAN_SW_FLAGS 431 432#ifdef CONFIG_ARM64_MTE 433 /* 434 * Update MAIR_EL1, GCR_EL1 and TFSR*_EL1 if MTE is supported 435 * (ID_AA64PFR1_EL1[11:8] > 1). 436 */ 437 mrs x10, ID_AA64PFR1_EL1 438 ubfx x10, x10, #ID_AA64PFR1_MTE_SHIFT, #4 439 cmp x10, #ID_AA64PFR1_MTE 440 b.lt 1f 441 442 /* Normal Tagged memory type at the corresponding MAIR index */ 443 mov x10, #MAIR_ATTR_NORMAL_TAGGED 444 bfi mair, x10, #(8 * MT_NORMAL_TAGGED), #8 445 446 /* initialize GCR_EL1: all non-zero tags excluded by default */ 447 mov x10, #(SYS_GCR_EL1_RRND | SYS_GCR_EL1_EXCL_MASK) 448 msr_s SYS_GCR_EL1, x10 449 450 /* 451 * If GCR_EL1.RRND=1 is implemented the same way as RRND=0, then 452 * RGSR_EL1.SEED must be non-zero for IRG to produce 453 * pseudorandom numbers. As RGSR_EL1 is UNKNOWN out of reset, we 454 * must initialize it. 455 */ 456 mrs x10, CNTVCT_EL0 457 ands x10, x10, #SYS_RGSR_EL1_SEED_MASK 458 csinc x10, x10, xzr, ne 459 lsl x10, x10, #SYS_RGSR_EL1_SEED_SHIFT 460 msr_s SYS_RGSR_EL1, x10 461 462 /* clear any pending tag check faults in TFSR*_EL1 */ 463 msr_s SYS_TFSR_EL1, xzr 464 msr_s SYS_TFSRE0_EL1, xzr 465 466 /* set the TCR_EL1 bits */ 467 mov_q x10, TCR_KASAN_HW_FLAGS 468 orr tcr, tcr, x10 4691: 470#endif 471 tcr_clear_errata_bits tcr, x9, x5 472 473#ifdef CONFIG_ARM64_VA_BITS_52 474 ldr_l x9, vabits_actual 475 sub x9, xzr, x9 476 add x9, x9, #64 477 tcr_set_t1sz tcr, x9 478#else 479 ldr_l x9, idmap_t0sz 480#endif 481 tcr_set_t0sz tcr, x9 482 483 /* 484 * Set the IPS bits in TCR_EL1. 485 */ 486 tcr_compute_pa_size tcr, #TCR_IPS_SHIFT, x5, x6 487#ifdef CONFIG_ARM64_HW_AFDBM 488 /* 489 * Enable hardware update of the Access Flags bit. 490 * Hardware dirty bit management is enabled later, 491 * via capabilities. 492 */ 493 mrs x9, ID_AA64MMFR1_EL1 494 and x9, x9, #0xf 495 cbz x9, 1f 496 orr tcr, tcr, #TCR_HA // hardware Access flag update 4971: 498#endif /* CONFIG_ARM64_HW_AFDBM */ 499 msr mair_el1, mair 500 msr tcr_el1, tcr 501 /* 502 * Prepare SCTLR 503 */ 504 mov_q x0, INIT_SCTLR_EL1_MMU_ON 505 ret // return to head.S 506 507 .unreq mair 508 .unreq tcr 509SYM_FUNC_END(__cpu_setup) 510