xref: /openbmc/linux/arch/arm64/mm/proc.S (revision 80483c3a) 
1/*
2 * Based on arch/arm/mm/proc.S
3 *
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
5 * Copyright (C) 2012 ARM Ltd.
6 * Author: Catalin Marinas <catalin.marinas@arm.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#include <linux/init.h>
22#include <linux/linkage.h>
23#include <asm/assembler.h>
24#include <asm/asm-offsets.h>
25#include <asm/hwcap.h>
26#include <asm/pgtable.h>
27#include <asm/pgtable-hwdef.h>
28#include <asm/cpufeature.h>
29#include <asm/alternative.h>
30
31#ifdef CONFIG_ARM64_64K_PAGES
32#define TCR_TG_FLAGS	TCR_TG0_64K | TCR_TG1_64K
33#elif defined(CONFIG_ARM64_16K_PAGES)
34#define TCR_TG_FLAGS	TCR_TG0_16K | TCR_TG1_16K
35#else /* CONFIG_ARM64_4K_PAGES */
36#define TCR_TG_FLAGS	TCR_TG0_4K | TCR_TG1_4K
37#endif
38
39#define TCR_SMP_FLAGS	TCR_SHARED
40
41/* PTWs cacheable, inner/outer WBWA */
42#define TCR_CACHE_FLAGS	TCR_IRGN_WBWA | TCR_ORGN_WBWA
43
44#define MAIR(attr, mt)	((attr) << ((mt) * 8))
45
46/*
47 *	cpu_do_idle()
48 *
49 *	Idle the processor (wait for interrupt).
50 */
51ENTRY(cpu_do_idle)
52	dsb	sy				// WFI may enter a low-power mode
53	wfi
54	ret
55ENDPROC(cpu_do_idle)
56
57#ifdef CONFIG_CPU_PM
58/**
59 * cpu_do_suspend - save CPU registers context
60 *
61 * x0: virtual address of context pointer
62 */
63ENTRY(cpu_do_suspend)
64	mrs	x2, tpidr_el0
65	mrs	x3, tpidrro_el0
66	mrs	x4, contextidr_el1
67	mrs	x5, cpacr_el1
68	mrs	x6, tcr_el1
69	mrs	x7, vbar_el1
70	mrs	x8, mdscr_el1
71	mrs	x9, oslsr_el1
72	mrs	x10, sctlr_el1
73	stp	x2, x3, [x0]
74	stp	x4, xzr, [x0, #16]
75	stp	x5, x6, [x0, #32]
76	stp	x7, x8, [x0, #48]
77	stp	x9, x10, [x0, #64]
78	ret
79ENDPROC(cpu_do_suspend)
80
81/**
82 * cpu_do_resume - restore CPU register context
83 *
84 * x0: Address of context pointer
85 */
86ENTRY(cpu_do_resume)
87	ldp	x2, x3, [x0]
88	ldp	x4, x5, [x0, #16]
89	ldp	x6, x8, [x0, #32]
90	ldp	x9, x10, [x0, #48]
91	ldp	x11, x12, [x0, #64]
92	msr	tpidr_el0, x2
93	msr	tpidrro_el0, x3
94	msr	contextidr_el1, x4
95	msr	cpacr_el1, x6
96
97	/* Don't change t0sz here, mask those bits when restoring */
98	mrs	x5, tcr_el1
99	bfi	x8, x5, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH
100
101	msr	tcr_el1, x8
102	msr	vbar_el1, x9
103	msr	mdscr_el1, x10
104	msr	sctlr_el1, x12
105	/*
106	 * Restore oslsr_el1 by writing oslar_el1
107	 */
108	ubfx	x11, x11, #1, #1
109	msr	oslar_el1, x11
110	reset_pmuserenr_el0 x0			// Disable PMU access from EL0
111	isb
112	ret
113ENDPROC(cpu_do_resume)
114#endif
115
116/*
117 *	cpu_do_switch_mm(pgd_phys, tsk)
118 *
119 *	Set the translation table base pointer to be pgd_phys.
120 *
121 *	- pgd_phys - physical address of new TTB
122 */
123ENTRY(cpu_do_switch_mm)
124	mmid	x1, x1				// get mm->context.id
125	bfi	x0, x1, #48, #16		// set the ASID
126	msr	ttbr0_el1, x0			// set TTBR0
127	isb
128alternative_if_not ARM64_WORKAROUND_CAVIUM_27456
129	ret
130	nop
131	nop
132	nop
133alternative_else
134	ic	iallu
135	dsb	nsh
136	isb
137	ret
138alternative_endif
139ENDPROC(cpu_do_switch_mm)
140
141	.pushsection ".idmap.text", "ax"
142/*
143 * void idmap_cpu_replace_ttbr1(phys_addr_t new_pgd)
144 *
145 * This is the low-level counterpart to cpu_replace_ttbr1, and should not be
146 * called by anything else. It can only be executed from a TTBR0 mapping.
147 */
148ENTRY(idmap_cpu_replace_ttbr1)
149	mrs	x2, daif
150	msr	daifset, #0xf
151
152	adrp	x1, empty_zero_page
153	msr	ttbr1_el1, x1
154	isb
155
156	tlbi	vmalle1
157	dsb	nsh
158	isb
159
160	msr	ttbr1_el1, x0
161	isb
162
163	msr	daif, x2
164
165	ret
166ENDPROC(idmap_cpu_replace_ttbr1)
167	.popsection
168
169/*
170 *	__cpu_setup
171 *
172 *	Initialise the processor for turning the MMU on.  Return in x0 the
173 *	value of the SCTLR_EL1 register.
174 */
175ENTRY(__cpu_setup)
176	tlbi	vmalle1				// Invalidate local TLB
177	dsb	nsh
178
179	mov	x0, #3 << 20
180	msr	cpacr_el1, x0			// Enable FP/ASIMD
181	mov	x0, #1 << 12			// Reset mdscr_el1 and disable
182	msr	mdscr_el1, x0			// access to the DCC from EL0
183	isb					// Unmask debug exceptions now,
184	enable_dbg				// since this is per-cpu
185	reset_pmuserenr_el0 x0			// Disable PMU access from EL0
186	/*
187	 * Memory region attributes for LPAE:
188	 *
189	 *   n = AttrIndx[2:0]
190	 *			n	MAIR
191	 *   DEVICE_nGnRnE	000	00000000
192	 *   DEVICE_nGnRE	001	00000100
193	 *   DEVICE_GRE		010	00001100
194	 *   NORMAL_NC		011	01000100
195	 *   NORMAL		100	11111111
196	 *   NORMAL_WT		101	10111011
197	 */
198	ldr	x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \
199		     MAIR(0x04, MT_DEVICE_nGnRE) | \
200		     MAIR(0x0c, MT_DEVICE_GRE) | \
201		     MAIR(0x44, MT_NORMAL_NC) | \
202		     MAIR(0xff, MT_NORMAL) | \
203		     MAIR(0xbb, MT_NORMAL_WT)
204	msr	mair_el1, x5
205	/*
206	 * Prepare SCTLR
207	 */
208	adr	x5, crval
209	ldp	w5, w6, [x5]
210	mrs	x0, sctlr_el1
211	bic	x0, x0, x5			// clear bits
212	orr	x0, x0, x6			// set bits
213	/*
214	 * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for
215	 * both user and kernel.
216	 */
217	ldr	x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \
218			TCR_TG_FLAGS | TCR_ASID16 | TCR_TBI0
219	tcr_set_idmap_t0sz	x10, x9
220
221	/*
222	 * Read the PARange bits from ID_AA64MMFR0_EL1 and set the IPS bits in
223	 * TCR_EL1.
224	 */
225	mrs	x9, ID_AA64MMFR0_EL1
226	bfi	x10, x9, #32, #3
227#ifdef CONFIG_ARM64_HW_AFDBM
228	/*
229	 * Hardware update of the Access and Dirty bits.
230	 */
231	mrs	x9, ID_AA64MMFR1_EL1
232	and	x9, x9, #0xf
233	cbz	x9, 2f
234	cmp	x9, #2
235	b.lt	1f
236	orr	x10, x10, #TCR_HD		// hardware Dirty flag update
2371:	orr	x10, x10, #TCR_HA		// hardware Access flag update
2382:
239#endif	/* CONFIG_ARM64_HW_AFDBM */
240	msr	tcr_el1, x10
241	ret					// return to head.S
242ENDPROC(__cpu_setup)
243
244	/*
245	 * We set the desired value explicitly, including those of the
246	 * reserved bits. The values of bits EE & E0E were set early in
247	 * el2_setup, which are left untouched below.
248	 *
249	 *                 n n            T
250	 *       U E      WT T UD     US IHBS
251	 *       CE0      XWHW CZ     ME TEEA S
252	 * .... .IEE .... NEAI TE.I ..AD DEN0 ACAM
253	 * 0011 0... 1101 ..0. ..0. 10.. .0.. .... < hardware reserved
254	 * .... .1.. .... 01.1 11.1 ..01 0.01 1101 < software settings
255	 */
256	.type	crval, #object
257crval:
258	.word	0xfcffffff			// clear
259	.word	0x34d5d91d			// set
260