1/* 2 * Based on arch/arm/mm/proc.S 3 * 4 * Copyright (C) 2001 Deep Blue Solutions Ltd. 5 * Copyright (C) 2012 ARM Ltd. 6 * Author: Catalin Marinas <catalin.marinas@arm.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21#include <linux/init.h> 22#include <linux/linkage.h> 23#include <asm/assembler.h> 24#include <asm/asm-offsets.h> 25#include <asm/hwcap.h> 26#include <asm/pgtable.h> 27#include <asm/pgtable-hwdef.h> 28#include <asm/cpufeature.h> 29#include <asm/alternative.h> 30 31#ifdef CONFIG_ARM64_64K_PAGES 32#define TCR_TG_FLAGS TCR_TG0_64K | TCR_TG1_64K 33#elif defined(CONFIG_ARM64_16K_PAGES) 34#define TCR_TG_FLAGS TCR_TG0_16K | TCR_TG1_16K 35#else /* CONFIG_ARM64_4K_PAGES */ 36#define TCR_TG_FLAGS TCR_TG0_4K | TCR_TG1_4K 37#endif 38 39#define TCR_SMP_FLAGS TCR_SHARED 40 41/* PTWs cacheable, inner/outer WBWA */ 42#define TCR_CACHE_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA 43 44#define MAIR(attr, mt) ((attr) << ((mt) * 8)) 45 46/* 47 * cpu_do_idle() 48 * 49 * Idle the processor (wait for interrupt). 50 */ 51ENTRY(cpu_do_idle) 52 dsb sy // WFI may enter a low-power mode 53 wfi 54 ret 55ENDPROC(cpu_do_idle) 56 57#ifdef CONFIG_CPU_PM 58/** 59 * cpu_do_suspend - save CPU registers context 60 * 61 * x0: virtual address of context pointer 62 */ 63ENTRY(cpu_do_suspend) 64 mrs x2, tpidr_el0 65 mrs x3, tpidrro_el0 66 mrs x4, contextidr_el1 67 mrs x5, cpacr_el1 68 mrs x6, tcr_el1 69 mrs x7, vbar_el1 70 mrs x8, mdscr_el1 71 mrs x9, oslsr_el1 72 mrs x10, sctlr_el1 73 mrs x11, tpidr_el1 74 mrs x12, sp_el0 75 stp x2, x3, [x0] 76 stp x4, xzr, [x0, #16] 77 stp x5, x6, [x0, #32] 78 stp x7, x8, [x0, #48] 79 stp x9, x10, [x0, #64] 80 stp x11, x12, [x0, #80] 81 ret 82ENDPROC(cpu_do_suspend) 83 84/** 85 * cpu_do_resume - restore CPU register context 86 * 87 * x0: Address of context pointer 88 */ 89 .pushsection ".idmap.text", "ax" 90ENTRY(cpu_do_resume) 91 ldp x2, x3, [x0] 92 ldp x4, x5, [x0, #16] 93 ldp x6, x8, [x0, #32] 94 ldp x9, x10, [x0, #48] 95 ldp x11, x12, [x0, #64] 96 ldp x13, x14, [x0, #80] 97 msr tpidr_el0, x2 98 msr tpidrro_el0, x3 99 msr contextidr_el1, x4 100 msr cpacr_el1, x6 101 102 /* Don't change t0sz here, mask those bits when restoring */ 103 mrs x5, tcr_el1 104 bfi x8, x5, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH 105 106 msr tcr_el1, x8 107 msr vbar_el1, x9 108 109 /* 110 * __cpu_setup() cleared MDSCR_EL1.MDE and friends, before unmasking 111 * debug exceptions. By restoring MDSCR_EL1 here, we may take a debug 112 * exception. Mask them until local_daif_restore() in cpu_suspend() 113 * resets them. 114 */ 115 disable_daif 116 msr mdscr_el1, x10 117 118 msr sctlr_el1, x12 119 msr tpidr_el1, x13 120 msr sp_el0, x14 121 /* 122 * Restore oslsr_el1 by writing oslar_el1 123 */ 124 ubfx x11, x11, #1, #1 125 msr oslar_el1, x11 126 reset_pmuserenr_el0 x0 // Disable PMU access from EL0 127 isb 128 ret 129ENDPROC(cpu_do_resume) 130 .popsection 131#endif 132 133/* 134 * cpu_do_switch_mm(pgd_phys, tsk) 135 * 136 * Set the translation table base pointer to be pgd_phys. 137 * 138 * - pgd_phys - physical address of new TTB 139 */ 140ENTRY(cpu_do_switch_mm) 141 pre_ttbr0_update_workaround x0, x2, x3 142 mrs x2, ttbr1_el1 143 mmid x1, x1 // get mm->context.id 144 bfi x2, x1, #48, #16 // set the ASID 145 msr ttbr1_el1, x2 // in TTBR1 (since TCR.A1 is set) 146 isb 147 msr ttbr0_el1, x0 // now update TTBR0 148 isb 149 post_ttbr0_update_workaround 150 ret 151ENDPROC(cpu_do_switch_mm) 152 153 .pushsection ".idmap.text", "ax" 154/* 155 * void idmap_cpu_replace_ttbr1(phys_addr_t new_pgd) 156 * 157 * This is the low-level counterpart to cpu_replace_ttbr1, and should not be 158 * called by anything else. It can only be executed from a TTBR0 mapping. 159 */ 160ENTRY(idmap_cpu_replace_ttbr1) 161 save_and_disable_daif flags=x2 162 163 adrp x1, empty_zero_page 164 msr ttbr1_el1, x1 165 isb 166 167 tlbi vmalle1 168 dsb nsh 169 isb 170 171 msr ttbr1_el1, x0 172 isb 173 174 restore_daif x2 175 176 ret 177ENDPROC(idmap_cpu_replace_ttbr1) 178 .popsection 179 180/* 181 * __cpu_setup 182 * 183 * Initialise the processor for turning the MMU on. Return in x0 the 184 * value of the SCTLR_EL1 register. 185 */ 186 .pushsection ".idmap.text", "ax" 187ENTRY(__cpu_setup) 188 tlbi vmalle1 // Invalidate local TLB 189 dsb nsh 190 191 mov x0, #3 << 20 192 msr cpacr_el1, x0 // Enable FP/ASIMD 193 mov x0, #1 << 12 // Reset mdscr_el1 and disable 194 msr mdscr_el1, x0 // access to the DCC from EL0 195 isb // Unmask debug exceptions now, 196 enable_dbg // since this is per-cpu 197 reset_pmuserenr_el0 x0 // Disable PMU access from EL0 198 /* 199 * Memory region attributes for LPAE: 200 * 201 * n = AttrIndx[2:0] 202 * n MAIR 203 * DEVICE_nGnRnE 000 00000000 204 * DEVICE_nGnRE 001 00000100 205 * DEVICE_GRE 010 00001100 206 * NORMAL_NC 011 01000100 207 * NORMAL 100 11111111 208 * NORMAL_WT 101 10111011 209 */ 210 ldr x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \ 211 MAIR(0x04, MT_DEVICE_nGnRE) | \ 212 MAIR(0x0c, MT_DEVICE_GRE) | \ 213 MAIR(0x44, MT_NORMAL_NC) | \ 214 MAIR(0xff, MT_NORMAL) | \ 215 MAIR(0xbb, MT_NORMAL_WT) 216 msr mair_el1, x5 217 /* 218 * Prepare SCTLR 219 */ 220 adr x5, crval 221 ldp w5, w6, [x5] 222 mrs x0, sctlr_el1 223 bic x0, x0, x5 // clear bits 224 orr x0, x0, x6 // set bits 225 /* 226 * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for 227 * both user and kernel. 228 */ 229 ldr x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \ 230 TCR_TG_FLAGS | TCR_ASID16 | TCR_TBI0 | TCR_A1 231 tcr_set_idmap_t0sz x10, x9 232 233 /* 234 * Read the PARange bits from ID_AA64MMFR0_EL1 and set the IPS bits in 235 * TCR_EL1. 236 */ 237 mrs x9, ID_AA64MMFR0_EL1 238 bfi x10, x9, #32, #3 239#ifdef CONFIG_ARM64_HW_AFDBM 240 /* 241 * Hardware update of the Access and Dirty bits. 242 */ 243 mrs x9, ID_AA64MMFR1_EL1 244 and x9, x9, #0xf 245 cbz x9, 2f 246 cmp x9, #2 247 b.lt 1f 248 orr x10, x10, #TCR_HD // hardware Dirty flag update 2491: orr x10, x10, #TCR_HA // hardware Access flag update 2502: 251#endif /* CONFIG_ARM64_HW_AFDBM */ 252 msr tcr_el1, x10 253 ret // return to head.S 254ENDPROC(__cpu_setup) 255 256 /* 257 * We set the desired value explicitly, including those of the 258 * reserved bits. The values of bits EE & E0E were set early in 259 * el2_setup, which are left untouched below. 260 * 261 * n n T 262 * U E WT T UD US IHBS 263 * CE0 XWHW CZ ME TEEA S 264 * .... .IEE .... NEAI TE.I ..AD DEN0 ACAM 265 * 0011 0... 1101 ..0. ..0. 10.. .0.. .... < hardware reserved 266 * .... .1.. .... 01.1 11.1 ..01 0.01 1101 < software settings 267 */ 268 .type crval, #object 269crval: 270 .word 0xfcffffff // clear 271 .word 0x34d5d91d // set 272 .popsection 273