xref: /openbmc/linux/arch/arm64/mm/proc.S (revision 752beb5e) 
1/*
2 * Based on arch/arm/mm/proc.S
3 *
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
5 * Copyright (C) 2012 ARM Ltd.
6 * Author: Catalin Marinas <catalin.marinas@arm.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#include <linux/init.h>
22#include <linux/linkage.h>
23#include <asm/assembler.h>
24#include <asm/asm-offsets.h>
25#include <asm/hwcap.h>
26#include <asm/pgtable.h>
27#include <asm/pgtable-hwdef.h>
28#include <asm/cpufeature.h>
29#include <asm/alternative.h>
30
31#ifdef CONFIG_ARM64_64K_PAGES
32#define TCR_TG_FLAGS	TCR_TG0_64K | TCR_TG1_64K
33#elif defined(CONFIG_ARM64_16K_PAGES)
34#define TCR_TG_FLAGS	TCR_TG0_16K | TCR_TG1_16K
35#else /* CONFIG_ARM64_4K_PAGES */
36#define TCR_TG_FLAGS	TCR_TG0_4K | TCR_TG1_4K
37#endif
38
39#ifdef CONFIG_RANDOMIZE_BASE
40#define TCR_KASLR_FLAGS	TCR_NFD1
41#else
42#define TCR_KASLR_FLAGS	0
43#endif
44
45#define TCR_SMP_FLAGS	TCR_SHARED
46
47/* PTWs cacheable, inner/outer WBWA */
48#define TCR_CACHE_FLAGS	TCR_IRGN_WBWA | TCR_ORGN_WBWA
49
50#ifdef CONFIG_KASAN_SW_TAGS
51#define TCR_KASAN_FLAGS TCR_TBI1
52#else
53#define TCR_KASAN_FLAGS 0
54#endif
55
56#define MAIR(attr, mt)	((attr) << ((mt) * 8))
57
58#ifdef CONFIG_CPU_PM
59/**
60 * cpu_do_suspend - save CPU registers context
61 *
62 * x0: virtual address of context pointer
63 */
64ENTRY(cpu_do_suspend)
65	mrs	x2, tpidr_el0
66	mrs	x3, tpidrro_el0
67	mrs	x4, contextidr_el1
68	mrs	x5, osdlr_el1
69	mrs	x6, cpacr_el1
70	mrs	x7, tcr_el1
71	mrs	x8, vbar_el1
72	mrs	x9, mdscr_el1
73	mrs	x10, oslsr_el1
74	mrs	x11, sctlr_el1
75alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
76	mrs	x12, tpidr_el1
77alternative_else
78	mrs	x12, tpidr_el2
79alternative_endif
80	mrs	x13, sp_el0
81	stp	x2, x3, [x0]
82	stp	x4, x5, [x0, #16]
83	stp	x6, x7, [x0, #32]
84	stp	x8, x9, [x0, #48]
85	stp	x10, x11, [x0, #64]
86	stp	x12, x13, [x0, #80]
87	ret
88ENDPROC(cpu_do_suspend)
89
90/**
91 * cpu_do_resume - restore CPU register context
92 *
93 * x0: Address of context pointer
94 */
95	.pushsection ".idmap.text", "awx"
96ENTRY(cpu_do_resume)
97	ldp	x2, x3, [x0]
98	ldp	x4, x5, [x0, #16]
99	ldp	x6, x8, [x0, #32]
100	ldp	x9, x10, [x0, #48]
101	ldp	x11, x12, [x0, #64]
102	ldp	x13, x14, [x0, #80]
103	msr	tpidr_el0, x2
104	msr	tpidrro_el0, x3
105	msr	contextidr_el1, x4
106	msr	cpacr_el1, x6
107
108	/* Don't change t0sz here, mask those bits when restoring */
109	mrs	x7, tcr_el1
110	bfi	x8, x7, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH
111
112	msr	tcr_el1, x8
113	msr	vbar_el1, x9
114
115	/*
116	 * __cpu_setup() cleared MDSCR_EL1.MDE and friends, before unmasking
117	 * debug exceptions. By restoring MDSCR_EL1 here, we may take a debug
118	 * exception. Mask them until local_daif_restore() in cpu_suspend()
119	 * resets them.
120	 */
121	disable_daif
122	msr	mdscr_el1, x10
123
124	msr	sctlr_el1, x12
125alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
126	msr	tpidr_el1, x13
127alternative_else
128	msr	tpidr_el2, x13
129alternative_endif
130	msr	sp_el0, x14
131	/*
132	 * Restore oslsr_el1 by writing oslar_el1
133	 */
134	msr	osdlr_el1, x5
135	ubfx	x11, x11, #1, #1
136	msr	oslar_el1, x11
137	reset_pmuserenr_el0 x0			// Disable PMU access from EL0
138
139alternative_if ARM64_HAS_RAS_EXTN
140	msr_s	SYS_DISR_EL1, xzr
141alternative_else_nop_endif
142
143	isb
144	ret
145ENDPROC(cpu_do_resume)
146	.popsection
147#endif
148
149/*
150 *	cpu_do_switch_mm(pgd_phys, tsk)
151 *
152 *	Set the translation table base pointer to be pgd_phys.
153 *
154 *	- pgd_phys - physical address of new TTB
155 */
156ENTRY(cpu_do_switch_mm)
157	mrs	x2, ttbr1_el1
158	mmid	x1, x1				// get mm->context.id
159	phys_to_ttbr x3, x0
160
161alternative_if ARM64_HAS_CNP
162	cbz     x1, 1f                          // skip CNP for reserved ASID
163	orr     x3, x3, #TTBR_CNP_BIT
1641:
165alternative_else_nop_endif
166#ifdef CONFIG_ARM64_SW_TTBR0_PAN
167	bfi	x3, x1, #48, #16		// set the ASID field in TTBR0
168#endif
169	bfi	x2, x1, #48, #16		// set the ASID
170	msr	ttbr1_el1, x2			// in TTBR1 (since TCR.A1 is set)
171	isb
172	msr	ttbr0_el1, x3			// now update TTBR0
173	isb
174	b	post_ttbr_update_workaround	// Back to C code...
175ENDPROC(cpu_do_switch_mm)
176
177	.pushsection ".idmap.text", "awx"
178
179.macro	__idmap_cpu_set_reserved_ttbr1, tmp1, tmp2
180	adrp	\tmp1, empty_zero_page
181	phys_to_ttbr \tmp2, \tmp1
182	offset_ttbr1 \tmp2
183	msr	ttbr1_el1, \tmp2
184	isb
185	tlbi	vmalle1
186	dsb	nsh
187	isb
188.endm
189
190/*
191 * void idmap_cpu_replace_ttbr1(phys_addr_t ttbr1)
192 *
193 * This is the low-level counterpart to cpu_replace_ttbr1, and should not be
194 * called by anything else. It can only be executed from a TTBR0 mapping.
195 */
196ENTRY(idmap_cpu_replace_ttbr1)
197	save_and_disable_daif flags=x2
198
199	__idmap_cpu_set_reserved_ttbr1 x1, x3
200
201	offset_ttbr1 x0
202	msr	ttbr1_el1, x0
203	isb
204
205	restore_daif x2
206
207	ret
208ENDPROC(idmap_cpu_replace_ttbr1)
209	.popsection
210
211#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
212	.pushsection ".idmap.text", "awx"
213
214	.macro	__idmap_kpti_get_pgtable_ent, type
215	dc	cvac, cur_\()\type\()p		// Ensure any existing dirty
216	dmb	sy				// lines are written back before
217	ldr	\type, [cur_\()\type\()p]	// loading the entry
218	tbz	\type, #0, skip_\()\type	// Skip invalid and
219	tbnz	\type, #11, skip_\()\type	// non-global entries
220	.endm
221
222	.macro __idmap_kpti_put_pgtable_ent_ng, type
223	orr	\type, \type, #PTE_NG		// Same bit for blocks and pages
224	str	\type, [cur_\()\type\()p]	// Update the entry and ensure
225	dmb	sy				// that it is visible to all
226	dc	civac, cur_\()\type\()p		// CPUs.
227	.endm
228
229/*
230 * void __kpti_install_ng_mappings(int cpu, int num_cpus, phys_addr_t swapper)
231 *
232 * Called exactly once from stop_machine context by each CPU found during boot.
233 */
234__idmap_kpti_flag:
235	.long	1
236ENTRY(idmap_kpti_install_ng_mappings)
237	cpu		.req	w0
238	num_cpus	.req	w1
239	swapper_pa	.req	x2
240	swapper_ttb	.req	x3
241	flag_ptr	.req	x4
242	cur_pgdp	.req	x5
243	end_pgdp	.req	x6
244	pgd		.req	x7
245	cur_pudp	.req	x8
246	end_pudp	.req	x9
247	pud		.req	x10
248	cur_pmdp	.req	x11
249	end_pmdp	.req	x12
250	pmd		.req	x13
251	cur_ptep	.req	x14
252	end_ptep	.req	x15
253	pte		.req	x16
254
255	mrs	swapper_ttb, ttbr1_el1
256	restore_ttbr1	swapper_ttb
257	adr	flag_ptr, __idmap_kpti_flag
258
259	cbnz	cpu, __idmap_kpti_secondary
260
261	/* We're the boot CPU. Wait for the others to catch up */
262	sevl
2631:	wfe
264	ldaxr	w18, [flag_ptr]
265	eor	w18, w18, num_cpus
266	cbnz	w18, 1b
267
268	/* We need to walk swapper, so turn off the MMU. */
269	pre_disable_mmu_workaround
270	mrs	x18, sctlr_el1
271	bic	x18, x18, #SCTLR_ELx_M
272	msr	sctlr_el1, x18
273	isb
274
275	/* Everybody is enjoying the idmap, so we can rewrite swapper. */
276	/* PGD */
277	mov	cur_pgdp, swapper_pa
278	add	end_pgdp, cur_pgdp, #(PTRS_PER_PGD * 8)
279do_pgd:	__idmap_kpti_get_pgtable_ent	pgd
280	tbnz	pgd, #1, walk_puds
281next_pgd:
282	__idmap_kpti_put_pgtable_ent_ng	pgd
283skip_pgd:
284	add	cur_pgdp, cur_pgdp, #8
285	cmp	cur_pgdp, end_pgdp
286	b.ne	do_pgd
287
288	/* Publish the updated tables and nuke all the TLBs */
289	dsb	sy
290	tlbi	vmalle1is
291	dsb	ish
292	isb
293
294	/* We're done: fire up the MMU again */
295	mrs	x18, sctlr_el1
296	orr	x18, x18, #SCTLR_ELx_M
297	msr	sctlr_el1, x18
298	isb
299
300	/* Set the flag to zero to indicate that we're all done */
301	str	wzr, [flag_ptr]
302	ret
303
304	/* PUD */
305walk_puds:
306	.if CONFIG_PGTABLE_LEVELS > 3
307	pte_to_phys	cur_pudp, pgd
308	add	end_pudp, cur_pudp, #(PTRS_PER_PUD * 8)
309do_pud:	__idmap_kpti_get_pgtable_ent	pud
310	tbnz	pud, #1, walk_pmds
311next_pud:
312	__idmap_kpti_put_pgtable_ent_ng	pud
313skip_pud:
314	add	cur_pudp, cur_pudp, 8
315	cmp	cur_pudp, end_pudp
316	b.ne	do_pud
317	b	next_pgd
318	.else /* CONFIG_PGTABLE_LEVELS <= 3 */
319	mov	pud, pgd
320	b	walk_pmds
321next_pud:
322	b	next_pgd
323	.endif
324
325	/* PMD */
326walk_pmds:
327	.if CONFIG_PGTABLE_LEVELS > 2
328	pte_to_phys	cur_pmdp, pud
329	add	end_pmdp, cur_pmdp, #(PTRS_PER_PMD * 8)
330do_pmd:	__idmap_kpti_get_pgtable_ent	pmd
331	tbnz	pmd, #1, walk_ptes
332next_pmd:
333	__idmap_kpti_put_pgtable_ent_ng	pmd
334skip_pmd:
335	add	cur_pmdp, cur_pmdp, #8
336	cmp	cur_pmdp, end_pmdp
337	b.ne	do_pmd
338	b	next_pud
339	.else /* CONFIG_PGTABLE_LEVELS <= 2 */
340	mov	pmd, pud
341	b	walk_ptes
342next_pmd:
343	b	next_pud
344	.endif
345
346	/* PTE */
347walk_ptes:
348	pte_to_phys	cur_ptep, pmd
349	add	end_ptep, cur_ptep, #(PTRS_PER_PTE * 8)
350do_pte:	__idmap_kpti_get_pgtable_ent	pte
351	__idmap_kpti_put_pgtable_ent_ng	pte
352skip_pte:
353	add	cur_ptep, cur_ptep, #8
354	cmp	cur_ptep, end_ptep
355	b.ne	do_pte
356	b	next_pmd
357
358	/* Secondary CPUs end up here */
359__idmap_kpti_secondary:
360	/* Uninstall swapper before surgery begins */
361	__idmap_cpu_set_reserved_ttbr1 x18, x17
362
363	/* Increment the flag to let the boot CPU we're ready */
3641:	ldxr	w18, [flag_ptr]
365	add	w18, w18, #1
366	stxr	w17, w18, [flag_ptr]
367	cbnz	w17, 1b
368
369	/* Wait for the boot CPU to finish messing around with swapper */
370	sevl
3711:	wfe
372	ldxr	w18, [flag_ptr]
373	cbnz	w18, 1b
374
375	/* All done, act like nothing happened */
376	offset_ttbr1 swapper_ttb
377	msr	ttbr1_el1, swapper_ttb
378	isb
379	ret
380
381	.unreq	cpu
382	.unreq	num_cpus
383	.unreq	swapper_pa
384	.unreq	swapper_ttb
385	.unreq	flag_ptr
386	.unreq	cur_pgdp
387	.unreq	end_pgdp
388	.unreq	pgd
389	.unreq	cur_pudp
390	.unreq	end_pudp
391	.unreq	pud
392	.unreq	cur_pmdp
393	.unreq	end_pmdp
394	.unreq	pmd
395	.unreq	cur_ptep
396	.unreq	end_ptep
397	.unreq	pte
398ENDPROC(idmap_kpti_install_ng_mappings)
399	.popsection
400#endif
401
402/*
403 *	__cpu_setup
404 *
405 *	Initialise the processor for turning the MMU on.  Return in x0 the
406 *	value of the SCTLR_EL1 register.
407 */
408	.pushsection ".idmap.text", "awx"
409ENTRY(__cpu_setup)
410	tlbi	vmalle1				// Invalidate local TLB
411	dsb	nsh
412
413	mov	x0, #3 << 20
414	msr	cpacr_el1, x0			// Enable FP/ASIMD
415	mov	x0, #1 << 12			// Reset mdscr_el1 and disable
416	msr	mdscr_el1, x0			// access to the DCC from EL0
417	isb					// Unmask debug exceptions now,
418	enable_dbg				// since this is per-cpu
419	reset_pmuserenr_el0 x0			// Disable PMU access from EL0
420	/*
421	 * Memory region attributes for LPAE:
422	 *
423	 *   n = AttrIndx[2:0]
424	 *			n	MAIR
425	 *   DEVICE_nGnRnE	000	00000000
426	 *   DEVICE_nGnRE	001	00000100
427	 *   DEVICE_GRE		010	00001100
428	 *   NORMAL_NC		011	01000100
429	 *   NORMAL		100	11111111
430	 *   NORMAL_WT		101	10111011
431	 */
432	ldr	x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \
433		     MAIR(0x04, MT_DEVICE_nGnRE) | \
434		     MAIR(0x0c, MT_DEVICE_GRE) | \
435		     MAIR(0x44, MT_NORMAL_NC) | \
436		     MAIR(0xff, MT_NORMAL) | \
437		     MAIR(0xbb, MT_NORMAL_WT)
438	msr	mair_el1, x5
439	/*
440	 * Prepare SCTLR
441	 */
442	mov_q	x0, SCTLR_EL1_SET
443	/*
444	 * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for
445	 * both user and kernel.
446	 */
447	ldr	x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \
448			TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \
449			TCR_TBI0 | TCR_A1 | TCR_KASAN_FLAGS
450	tcr_clear_errata_bits x10, x9, x5
451
452#ifdef CONFIG_ARM64_USER_VA_BITS_52
453	ldr_l		x9, vabits_user
454	sub		x9, xzr, x9
455	add		x9, x9, #64
456#else
457	ldr_l		x9, idmap_t0sz
458#endif
459	tcr_set_t0sz	x10, x9
460
461	/*
462	 * Set the IPS bits in TCR_EL1.
463	 */
464	tcr_compute_pa_size x10, #TCR_IPS_SHIFT, x5, x6
465#ifdef CONFIG_ARM64_HW_AFDBM
466	/*
467	 * Enable hardware update of the Access Flags bit.
468	 * Hardware dirty bit management is enabled later,
469	 * via capabilities.
470	 */
471	mrs	x9, ID_AA64MMFR1_EL1
472	and	x9, x9, #0xf
473	cbz	x9, 1f
474	orr	x10, x10, #TCR_HA		// hardware Access flag update
4751:
476#endif	/* CONFIG_ARM64_HW_AFDBM */
477	msr	tcr_el1, x10
478	ret					// return to head.S
479ENDPROC(__cpu_setup)
480