1/* 2 * Based on arch/arm/mm/proc.S 3 * 4 * Copyright (C) 2001 Deep Blue Solutions Ltd. 5 * Copyright (C) 2012 ARM Ltd. 6 * Author: Catalin Marinas <catalin.marinas@arm.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21#include <linux/init.h> 22#include <linux/linkage.h> 23#include <asm/assembler.h> 24#include <asm/asm-offsets.h> 25#include <asm/hwcap.h> 26#include <asm/pgtable.h> 27#include <asm/pgtable-hwdef.h> 28#include <asm/cpufeature.h> 29#include <asm/alternative.h> 30 31#ifdef CONFIG_ARM64_64K_PAGES 32#define TCR_TG_FLAGS TCR_TG0_64K | TCR_TG1_64K 33#elif defined(CONFIG_ARM64_16K_PAGES) 34#define TCR_TG_FLAGS TCR_TG0_16K | TCR_TG1_16K 35#else /* CONFIG_ARM64_4K_PAGES */ 36#define TCR_TG_FLAGS TCR_TG0_4K | TCR_TG1_4K 37#endif 38 39#define TCR_SMP_FLAGS TCR_SHARED 40 41/* PTWs cacheable, inner/outer WBWA */ 42#define TCR_CACHE_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA 43 44#define MAIR(attr, mt) ((attr) << ((mt) * 8)) 45 46/* 47 * cpu_do_idle() 48 * 49 * Idle the processor (wait for interrupt). 50 */ 51ENTRY(cpu_do_idle) 52 dsb sy // WFI may enter a low-power mode 53 wfi 54 ret 55ENDPROC(cpu_do_idle) 56 57#ifdef CONFIG_CPU_PM 58/** 59 * cpu_do_suspend - save CPU registers context 60 * 61 * x0: virtual address of context pointer 62 */ 63ENTRY(cpu_do_suspend) 64 mrs x2, tpidr_el0 65 mrs x3, tpidrro_el0 66 mrs x4, contextidr_el1 67 mrs x5, cpacr_el1 68 mrs x6, tcr_el1 69 mrs x7, vbar_el1 70 mrs x8, mdscr_el1 71 mrs x9, oslsr_el1 72 mrs x10, sctlr_el1 73alternative_if_not ARM64_HAS_VIRT_HOST_EXTN 74 mrs x11, tpidr_el1 75alternative_else 76 mrs x11, tpidr_el2 77alternative_endif 78 mrs x12, sp_el0 79 stp x2, x3, [x0] 80 stp x4, xzr, [x0, #16] 81 stp x5, x6, [x0, #32] 82 stp x7, x8, [x0, #48] 83 stp x9, x10, [x0, #64] 84 stp x11, x12, [x0, #80] 85 ret 86ENDPROC(cpu_do_suspend) 87 88/** 89 * cpu_do_resume - restore CPU register context 90 * 91 * x0: Address of context pointer 92 */ 93 .pushsection ".idmap.text", "ax" 94ENTRY(cpu_do_resume) 95 ldp x2, x3, [x0] 96 ldp x4, x5, [x0, #16] 97 ldp x6, x8, [x0, #32] 98 ldp x9, x10, [x0, #48] 99 ldp x11, x12, [x0, #64] 100 ldp x13, x14, [x0, #80] 101 msr tpidr_el0, x2 102 msr tpidrro_el0, x3 103 msr contextidr_el1, x4 104 msr cpacr_el1, x6 105 106 /* Don't change t0sz here, mask those bits when restoring */ 107 mrs x5, tcr_el1 108 bfi x8, x5, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH 109 110 msr tcr_el1, x8 111 msr vbar_el1, x9 112 113 /* 114 * __cpu_setup() cleared MDSCR_EL1.MDE and friends, before unmasking 115 * debug exceptions. By restoring MDSCR_EL1 here, we may take a debug 116 * exception. Mask them until local_daif_restore() in cpu_suspend() 117 * resets them. 118 */ 119 disable_daif 120 msr mdscr_el1, x10 121 122 msr sctlr_el1, x12 123alternative_if_not ARM64_HAS_VIRT_HOST_EXTN 124 msr tpidr_el1, x13 125alternative_else 126 msr tpidr_el2, x13 127alternative_endif 128 msr sp_el0, x14 129 /* 130 * Restore oslsr_el1 by writing oslar_el1 131 */ 132 ubfx x11, x11, #1, #1 133 msr oslar_el1, x11 134 reset_pmuserenr_el0 x0 // Disable PMU access from EL0 135 isb 136 ret 137ENDPROC(cpu_do_resume) 138 .popsection 139#endif 140 141/* 142 * cpu_do_switch_mm(pgd_phys, tsk) 143 * 144 * Set the translation table base pointer to be pgd_phys. 145 * 146 * - pgd_phys - physical address of new TTB 147 */ 148ENTRY(cpu_do_switch_mm) 149 mrs x2, ttbr1_el1 150 mmid x1, x1 // get mm->context.id 151 bfi x2, x1, #48, #16 // set the ASID 152 msr ttbr1_el1, x2 // in TTBR1 (since TCR.A1 is set) 153 isb 154 phys_to_ttbr x0, x2 155 msr ttbr0_el1, x2 // now update TTBR0 156 isb 157 b post_ttbr_update_workaround // Back to C code... 158ENDPROC(cpu_do_switch_mm) 159 160 .pushsection ".idmap.text", "ax" 161/* 162 * void idmap_cpu_replace_ttbr1(phys_addr_t new_pgd) 163 * 164 * This is the low-level counterpart to cpu_replace_ttbr1, and should not be 165 * called by anything else. It can only be executed from a TTBR0 mapping. 166 */ 167ENTRY(idmap_cpu_replace_ttbr1) 168 save_and_disable_daif flags=x2 169 170 adrp x1, empty_zero_page 171 phys_to_ttbr x1, x3 172 msr ttbr1_el1, x3 173 isb 174 175 tlbi vmalle1 176 dsb nsh 177 isb 178 179 phys_to_ttbr x0, x3 180 msr ttbr1_el1, x3 181 isb 182 183 restore_daif x2 184 185 ret 186ENDPROC(idmap_cpu_replace_ttbr1) 187 .popsection 188 189/* 190 * __cpu_setup 191 * 192 * Initialise the processor for turning the MMU on. Return in x0 the 193 * value of the SCTLR_EL1 register. 194 */ 195 .pushsection ".idmap.text", "ax" 196ENTRY(__cpu_setup) 197 tlbi vmalle1 // Invalidate local TLB 198 dsb nsh 199 200 mov x0, #3 << 20 201 msr cpacr_el1, x0 // Enable FP/ASIMD 202 mov x0, #1 << 12 // Reset mdscr_el1 and disable 203 msr mdscr_el1, x0 // access to the DCC from EL0 204 isb // Unmask debug exceptions now, 205 enable_dbg // since this is per-cpu 206 reset_pmuserenr_el0 x0 // Disable PMU access from EL0 207 /* 208 * Memory region attributes for LPAE: 209 * 210 * n = AttrIndx[2:0] 211 * n MAIR 212 * DEVICE_nGnRnE 000 00000000 213 * DEVICE_nGnRE 001 00000100 214 * DEVICE_GRE 010 00001100 215 * NORMAL_NC 011 01000100 216 * NORMAL 100 11111111 217 * NORMAL_WT 101 10111011 218 */ 219 ldr x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \ 220 MAIR(0x04, MT_DEVICE_nGnRE) | \ 221 MAIR(0x0c, MT_DEVICE_GRE) | \ 222 MAIR(0x44, MT_NORMAL_NC) | \ 223 MAIR(0xff, MT_NORMAL) | \ 224 MAIR(0xbb, MT_NORMAL_WT) 225 msr mair_el1, x5 226 /* 227 * Prepare SCTLR 228 */ 229 adr x5, crval 230 ldp w5, w6, [x5] 231 mrs x0, sctlr_el1 232 bic x0, x0, x5 // clear bits 233 orr x0, x0, x6 // set bits 234 /* 235 * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for 236 * both user and kernel. 237 */ 238 ldr x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \ 239 TCR_TG_FLAGS | TCR_ASID16 | TCR_TBI0 | TCR_A1 240 tcr_set_idmap_t0sz x10, x9 241 242 /* 243 * Set the IPS bits in TCR_EL1. 244 */ 245 tcr_compute_pa_size x10, #TCR_IPS_SHIFT, x5, x6 246#ifdef CONFIG_ARM64_HW_AFDBM 247 /* 248 * Hardware update of the Access and Dirty bits. 249 */ 250 mrs x9, ID_AA64MMFR1_EL1 251 and x9, x9, #0xf 252 cbz x9, 2f 253 cmp x9, #2 254 b.lt 1f 255 orr x10, x10, #TCR_HD // hardware Dirty flag update 2561: orr x10, x10, #TCR_HA // hardware Access flag update 2572: 258#endif /* CONFIG_ARM64_HW_AFDBM */ 259 msr tcr_el1, x10 260 ret // return to head.S 261ENDPROC(__cpu_setup) 262 263 /* 264 * We set the desired value explicitly, including those of the 265 * reserved bits. The values of bits EE & E0E were set early in 266 * el2_setup, which are left untouched below. 267 * 268 * n n T 269 * U E WT T UD US IHBS 270 * CE0 XWHW CZ ME TEEA S 271 * .... .IEE .... NEAI TE.I ..AD DEN0 ACAM 272 * 0011 0... 1101 ..0. ..0. 10.. .0.. .... < hardware reserved 273 * .... .1.. .... 01.1 11.1 ..01 0.01 1101 < software settings 274 */ 275 .type crval, #object 276crval: 277 .word 0xfcffffff // clear 278 .word 0x34d5d91d // set 279 .popsection 280