xref: /openbmc/linux/arch/arm64/mm/proc.S (revision 6d99a79c) 
1/*
2 * Based on arch/arm/mm/proc.S
3 *
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
5 * Copyright (C) 2012 ARM Ltd.
6 * Author: Catalin Marinas <catalin.marinas@arm.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#include <linux/init.h>
22#include <linux/linkage.h>
23#include <asm/assembler.h>
24#include <asm/asm-offsets.h>
25#include <asm/hwcap.h>
26#include <asm/pgtable.h>
27#include <asm/pgtable-hwdef.h>
28#include <asm/cpufeature.h>
29#include <asm/alternative.h>
30
31#ifdef CONFIG_ARM64_64K_PAGES
32#define TCR_TG_FLAGS	TCR_TG0_64K | TCR_TG1_64K
33#elif defined(CONFIG_ARM64_16K_PAGES)
34#define TCR_TG_FLAGS	TCR_TG0_16K | TCR_TG1_16K
35#else /* CONFIG_ARM64_4K_PAGES */
36#define TCR_TG_FLAGS	TCR_TG0_4K | TCR_TG1_4K
37#endif
38
39#ifdef CONFIG_RANDOMIZE_BASE
40#define TCR_KASLR_FLAGS	TCR_NFD1
41#else
42#define TCR_KASLR_FLAGS	0
43#endif
44
45#define TCR_SMP_FLAGS	TCR_SHARED
46
47/* PTWs cacheable, inner/outer WBWA */
48#define TCR_CACHE_FLAGS	TCR_IRGN_WBWA | TCR_ORGN_WBWA
49
50#define MAIR(attr, mt)	((attr) << ((mt) * 8))
51
52/*
53 *	cpu_do_idle()
54 *
55 *	Idle the processor (wait for interrupt).
56 */
57ENTRY(cpu_do_idle)
58	dsb	sy				// WFI may enter a low-power mode
59	wfi
60	ret
61ENDPROC(cpu_do_idle)
62
63#ifdef CONFIG_CPU_PM
64/**
65 * cpu_do_suspend - save CPU registers context
66 *
67 * x0: virtual address of context pointer
68 */
69ENTRY(cpu_do_suspend)
70	mrs	x2, tpidr_el0
71	mrs	x3, tpidrro_el0
72	mrs	x4, contextidr_el1
73	mrs	x5, cpacr_el1
74	mrs	x6, tcr_el1
75	mrs	x7, vbar_el1
76	mrs	x8, mdscr_el1
77	mrs	x9, oslsr_el1
78	mrs	x10, sctlr_el1
79alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
80	mrs	x11, tpidr_el1
81alternative_else
82	mrs	x11, tpidr_el2
83alternative_endif
84	mrs	x12, sp_el0
85	stp	x2, x3, [x0]
86	stp	x4, xzr, [x0, #16]
87	stp	x5, x6, [x0, #32]
88	stp	x7, x8, [x0, #48]
89	stp	x9, x10, [x0, #64]
90	stp	x11, x12, [x0, #80]
91	ret
92ENDPROC(cpu_do_suspend)
93
94/**
95 * cpu_do_resume - restore CPU register context
96 *
97 * x0: Address of context pointer
98 */
99	.pushsection ".idmap.text", "awx"
100ENTRY(cpu_do_resume)
101	ldp	x2, x3, [x0]
102	ldp	x4, x5, [x0, #16]
103	ldp	x6, x8, [x0, #32]
104	ldp	x9, x10, [x0, #48]
105	ldp	x11, x12, [x0, #64]
106	ldp	x13, x14, [x0, #80]
107	msr	tpidr_el0, x2
108	msr	tpidrro_el0, x3
109	msr	contextidr_el1, x4
110	msr	cpacr_el1, x6
111
112	/* Don't change t0sz here, mask those bits when restoring */
113	mrs	x5, tcr_el1
114	bfi	x8, x5, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH
115
116	msr	tcr_el1, x8
117	msr	vbar_el1, x9
118
119	/*
120	 * __cpu_setup() cleared MDSCR_EL1.MDE and friends, before unmasking
121	 * debug exceptions. By restoring MDSCR_EL1 here, we may take a debug
122	 * exception. Mask them until local_daif_restore() in cpu_suspend()
123	 * resets them.
124	 */
125	disable_daif
126	msr	mdscr_el1, x10
127
128	msr	sctlr_el1, x12
129alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
130	msr	tpidr_el1, x13
131alternative_else
132	msr	tpidr_el2, x13
133alternative_endif
134	msr	sp_el0, x14
135	/*
136	 * Restore oslsr_el1 by writing oslar_el1
137	 */
138	ubfx	x11, x11, #1, #1
139	msr	oslar_el1, x11
140	reset_pmuserenr_el0 x0			// Disable PMU access from EL0
141
142alternative_if ARM64_HAS_RAS_EXTN
143	msr_s	SYS_DISR_EL1, xzr
144alternative_else_nop_endif
145
146	isb
147	ret
148ENDPROC(cpu_do_resume)
149	.popsection
150#endif
151
152/*
153 *	cpu_do_switch_mm(pgd_phys, tsk)
154 *
155 *	Set the translation table base pointer to be pgd_phys.
156 *
157 *	- pgd_phys - physical address of new TTB
158 */
159ENTRY(cpu_do_switch_mm)
160	mrs	x2, ttbr1_el1
161	mmid	x1, x1				// get mm->context.id
162	phys_to_ttbr x3, x0
163
164alternative_if ARM64_HAS_CNP
165	cbz     x1, 1f                          // skip CNP for reserved ASID
166	orr     x3, x3, #TTBR_CNP_BIT
1671:
168alternative_else_nop_endif
169#ifdef CONFIG_ARM64_SW_TTBR0_PAN
170	bfi	x3, x1, #48, #16		// set the ASID field in TTBR0
171#endif
172	bfi	x2, x1, #48, #16		// set the ASID
173	msr	ttbr1_el1, x2			// in TTBR1 (since TCR.A1 is set)
174	isb
175	msr	ttbr0_el1, x3			// now update TTBR0
176	isb
177	b	post_ttbr_update_workaround	// Back to C code...
178ENDPROC(cpu_do_switch_mm)
179
180	.pushsection ".idmap.text", "awx"
181
182.macro	__idmap_cpu_set_reserved_ttbr1, tmp1, tmp2
183	adrp	\tmp1, empty_zero_page
184	phys_to_ttbr \tmp2, \tmp1
185	msr	ttbr1_el1, \tmp2
186	isb
187	tlbi	vmalle1
188	dsb	nsh
189	isb
190.endm
191
192/*
193 * void idmap_cpu_replace_ttbr1(phys_addr_t ttbr1)
194 *
195 * This is the low-level counterpart to cpu_replace_ttbr1, and should not be
196 * called by anything else. It can only be executed from a TTBR0 mapping.
197 */
198ENTRY(idmap_cpu_replace_ttbr1)
199	save_and_disable_daif flags=x2
200
201	__idmap_cpu_set_reserved_ttbr1 x1, x3
202
203	msr	ttbr1_el1, x0
204	isb
205
206	restore_daif x2
207
208	ret
209ENDPROC(idmap_cpu_replace_ttbr1)
210	.popsection
211
212#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
213	.pushsection ".idmap.text", "awx"
214
215	.macro	__idmap_kpti_get_pgtable_ent, type
216	dc	cvac, cur_\()\type\()p		// Ensure any existing dirty
217	dmb	sy				// lines are written back before
218	ldr	\type, [cur_\()\type\()p]	// loading the entry
219	tbz	\type, #0, skip_\()\type	// Skip invalid and
220	tbnz	\type, #11, skip_\()\type	// non-global entries
221	.endm
222
223	.macro __idmap_kpti_put_pgtable_ent_ng, type
224	orr	\type, \type, #PTE_NG		// Same bit for blocks and pages
225	str	\type, [cur_\()\type\()p]	// Update the entry and ensure
226	dmb	sy				// that it is visible to all
227	dc	civac, cur_\()\type\()p		// CPUs.
228	.endm
229
230/*
231 * void __kpti_install_ng_mappings(int cpu, int num_cpus, phys_addr_t swapper)
232 *
233 * Called exactly once from stop_machine context by each CPU found during boot.
234 */
235__idmap_kpti_flag:
236	.long	1
237ENTRY(idmap_kpti_install_ng_mappings)
238	cpu		.req	w0
239	num_cpus	.req	w1
240	swapper_pa	.req	x2
241	swapper_ttb	.req	x3
242	flag_ptr	.req	x4
243	cur_pgdp	.req	x5
244	end_pgdp	.req	x6
245	pgd		.req	x7
246	cur_pudp	.req	x8
247	end_pudp	.req	x9
248	pud		.req	x10
249	cur_pmdp	.req	x11
250	end_pmdp	.req	x12
251	pmd		.req	x13
252	cur_ptep	.req	x14
253	end_ptep	.req	x15
254	pte		.req	x16
255
256	mrs	swapper_ttb, ttbr1_el1
257	adr	flag_ptr, __idmap_kpti_flag
258
259	cbnz	cpu, __idmap_kpti_secondary
260
261	/* We're the boot CPU. Wait for the others to catch up */
262	sevl
2631:	wfe
264	ldaxr	w18, [flag_ptr]
265	eor	w18, w18, num_cpus
266	cbnz	w18, 1b
267
268	/* We need to walk swapper, so turn off the MMU. */
269	pre_disable_mmu_workaround
270	mrs	x18, sctlr_el1
271	bic	x18, x18, #SCTLR_ELx_M
272	msr	sctlr_el1, x18
273	isb
274
275	/* Everybody is enjoying the idmap, so we can rewrite swapper. */
276	/* PGD */
277	mov	cur_pgdp, swapper_pa
278	add	end_pgdp, cur_pgdp, #(PTRS_PER_PGD * 8)
279do_pgd:	__idmap_kpti_get_pgtable_ent	pgd
280	tbnz	pgd, #1, walk_puds
281next_pgd:
282	__idmap_kpti_put_pgtable_ent_ng	pgd
283skip_pgd:
284	add	cur_pgdp, cur_pgdp, #8
285	cmp	cur_pgdp, end_pgdp
286	b.ne	do_pgd
287
288	/* Publish the updated tables and nuke all the TLBs */
289	dsb	sy
290	tlbi	vmalle1is
291	dsb	ish
292	isb
293
294	/* We're done: fire up the MMU again */
295	mrs	x18, sctlr_el1
296	orr	x18, x18, #SCTLR_ELx_M
297	msr	sctlr_el1, x18
298	isb
299
300	/* Set the flag to zero to indicate that we're all done */
301	str	wzr, [flag_ptr]
302	ret
303
304	/* PUD */
305walk_puds:
306	.if CONFIG_PGTABLE_LEVELS > 3
307	pte_to_phys	cur_pudp, pgd
308	add	end_pudp, cur_pudp, #(PTRS_PER_PUD * 8)
309do_pud:	__idmap_kpti_get_pgtable_ent	pud
310	tbnz	pud, #1, walk_pmds
311next_pud:
312	__idmap_kpti_put_pgtable_ent_ng	pud
313skip_pud:
314	add	cur_pudp, cur_pudp, 8
315	cmp	cur_pudp, end_pudp
316	b.ne	do_pud
317	b	next_pgd
318	.else /* CONFIG_PGTABLE_LEVELS <= 3 */
319	mov	pud, pgd
320	b	walk_pmds
321next_pud:
322	b	next_pgd
323	.endif
324
325	/* PMD */
326walk_pmds:
327	.if CONFIG_PGTABLE_LEVELS > 2
328	pte_to_phys	cur_pmdp, pud
329	add	end_pmdp, cur_pmdp, #(PTRS_PER_PMD * 8)
330do_pmd:	__idmap_kpti_get_pgtable_ent	pmd
331	tbnz	pmd, #1, walk_ptes
332next_pmd:
333	__idmap_kpti_put_pgtable_ent_ng	pmd
334skip_pmd:
335	add	cur_pmdp, cur_pmdp, #8
336	cmp	cur_pmdp, end_pmdp
337	b.ne	do_pmd
338	b	next_pud
339	.else /* CONFIG_PGTABLE_LEVELS <= 2 */
340	mov	pmd, pud
341	b	walk_ptes
342next_pmd:
343	b	next_pud
344	.endif
345
346	/* PTE */
347walk_ptes:
348	pte_to_phys	cur_ptep, pmd
349	add	end_ptep, cur_ptep, #(PTRS_PER_PTE * 8)
350do_pte:	__idmap_kpti_get_pgtable_ent	pte
351	__idmap_kpti_put_pgtable_ent_ng	pte
352skip_pte:
353	add	cur_ptep, cur_ptep, #8
354	cmp	cur_ptep, end_ptep
355	b.ne	do_pte
356	b	next_pmd
357
358	/* Secondary CPUs end up here */
359__idmap_kpti_secondary:
360	/* Uninstall swapper before surgery begins */
361	__idmap_cpu_set_reserved_ttbr1 x18, x17
362
363	/* Increment the flag to let the boot CPU we're ready */
3641:	ldxr	w18, [flag_ptr]
365	add	w18, w18, #1
366	stxr	w17, w18, [flag_ptr]
367	cbnz	w17, 1b
368
369	/* Wait for the boot CPU to finish messing around with swapper */
370	sevl
3711:	wfe
372	ldxr	w18, [flag_ptr]
373	cbnz	w18, 1b
374
375	/* All done, act like nothing happened */
376	msr	ttbr1_el1, swapper_ttb
377	isb
378	ret
379
380	.unreq	cpu
381	.unreq	num_cpus
382	.unreq	swapper_pa
383	.unreq	swapper_ttb
384	.unreq	flag_ptr
385	.unreq	cur_pgdp
386	.unreq	end_pgdp
387	.unreq	pgd
388	.unreq	cur_pudp
389	.unreq	end_pudp
390	.unreq	pud
391	.unreq	cur_pmdp
392	.unreq	end_pmdp
393	.unreq	pmd
394	.unreq	cur_ptep
395	.unreq	end_ptep
396	.unreq	pte
397ENDPROC(idmap_kpti_install_ng_mappings)
398	.popsection
399#endif
400
401/*
402 *	__cpu_setup
403 *
404 *	Initialise the processor for turning the MMU on.  Return in x0 the
405 *	value of the SCTLR_EL1 register.
406 */
407	.pushsection ".idmap.text", "awx"
408ENTRY(__cpu_setup)
409	tlbi	vmalle1				// Invalidate local TLB
410	dsb	nsh
411
412	mov	x0, #3 << 20
413	msr	cpacr_el1, x0			// Enable FP/ASIMD
414	mov	x0, #1 << 12			// Reset mdscr_el1 and disable
415	msr	mdscr_el1, x0			// access to the DCC from EL0
416	isb					// Unmask debug exceptions now,
417	enable_dbg				// since this is per-cpu
418	reset_pmuserenr_el0 x0			// Disable PMU access from EL0
419	/*
420	 * Memory region attributes for LPAE:
421	 *
422	 *   n = AttrIndx[2:0]
423	 *			n	MAIR
424	 *   DEVICE_nGnRnE	000	00000000
425	 *   DEVICE_nGnRE	001	00000100
426	 *   DEVICE_GRE		010	00001100
427	 *   NORMAL_NC		011	01000100
428	 *   NORMAL		100	11111111
429	 *   NORMAL_WT		101	10111011
430	 */
431	ldr	x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \
432		     MAIR(0x04, MT_DEVICE_nGnRE) | \
433		     MAIR(0x0c, MT_DEVICE_GRE) | \
434		     MAIR(0x44, MT_NORMAL_NC) | \
435		     MAIR(0xff, MT_NORMAL) | \
436		     MAIR(0xbb, MT_NORMAL_WT)
437	msr	mair_el1, x5
438	/*
439	 * Prepare SCTLR
440	 */
441	mov_q	x0, SCTLR_EL1_SET
442	/*
443	 * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for
444	 * both user and kernel.
445	 */
446	ldr	x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \
447			TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \
448			TCR_TBI0 | TCR_A1
449	tcr_set_idmap_t0sz	x10, x9
450
451	/*
452	 * Set the IPS bits in TCR_EL1.
453	 */
454	tcr_compute_pa_size x10, #TCR_IPS_SHIFT, x5, x6
455#ifdef CONFIG_ARM64_HW_AFDBM
456	/*
457	 * Enable hardware update of the Access Flags bit.
458	 * Hardware dirty bit management is enabled later,
459	 * via capabilities.
460	 */
461	mrs	x9, ID_AA64MMFR1_EL1
462	and	x9, x9, #0xf
463	cbz	x9, 1f
464	orr	x10, x10, #TCR_HA		// hardware Access flag update
4651:
466#endif	/* CONFIG_ARM64_HW_AFDBM */
467	msr	tcr_el1, x10
468	ret					// return to head.S
469ENDPROC(__cpu_setup)
470