xref: /openbmc/linux/arch/arm64/mm/proc.S (revision 6abeae2a) 
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Based on arch/arm/mm/proc.S
4 *
5 * Copyright (C) 2001 Deep Blue Solutions Ltd.
6 * Copyright (C) 2012 ARM Ltd.
7 * Author: Catalin Marinas <catalin.marinas@arm.com>
8 */
9
10#include <linux/init.h>
11#include <linux/linkage.h>
12#include <linux/pgtable.h>
13#include <asm/assembler.h>
14#include <asm/asm-offsets.h>
15#include <asm/asm_pointer_auth.h>
16#include <asm/hwcap.h>
17#include <asm/pgtable-hwdef.h>
18#include <asm/cpufeature.h>
19#include <asm/alternative.h>
20#include <asm/smp.h>
21#include <asm/sysreg.h>
22
23#ifdef CONFIG_ARM64_64K_PAGES
24#define TCR_TG_FLAGS	TCR_TG0_64K | TCR_TG1_64K
25#elif defined(CONFIG_ARM64_16K_PAGES)
26#define TCR_TG_FLAGS	TCR_TG0_16K | TCR_TG1_16K
27#else /* CONFIG_ARM64_4K_PAGES */
28#define TCR_TG_FLAGS	TCR_TG0_4K | TCR_TG1_4K
29#endif
30
31#ifdef CONFIG_RANDOMIZE_BASE
32#define TCR_KASLR_FLAGS	TCR_NFD1
33#else
34#define TCR_KASLR_FLAGS	0
35#endif
36
37#define TCR_SMP_FLAGS	TCR_SHARED
38
39/* PTWs cacheable, inner/outer WBWA */
40#define TCR_CACHE_FLAGS	TCR_IRGN_WBWA | TCR_ORGN_WBWA
41
42#ifdef CONFIG_KASAN_SW_TAGS
43#define TCR_KASAN_SW_FLAGS TCR_TBI1 | TCR_TBID1
44#else
45#define TCR_KASAN_SW_FLAGS 0
46#endif
47
48#ifdef CONFIG_KASAN_HW_TAGS
49#define TCR_KASAN_HW_FLAGS SYS_TCR_EL1_TCMA1 | TCR_TBI1
50#else
51#define TCR_KASAN_HW_FLAGS 0
52#endif
53
54/*
55 * Default MAIR_EL1. MT_NORMAL_TAGGED is initially mapped as Normal memory and
56 * changed during __cpu_setup to Normal Tagged if the system supports MTE.
57 */
58#define MAIR_EL1_SET							\
59	(MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRnE, MT_DEVICE_nGnRnE) |	\
60	 MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRE, MT_DEVICE_nGnRE) |	\
61	 MAIR_ATTRIDX(MAIR_ATTR_DEVICE_GRE, MT_DEVICE_GRE) |		\
62	 MAIR_ATTRIDX(MAIR_ATTR_NORMAL_NC, MT_NORMAL_NC) |		\
63	 MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL) |			\
64	 MAIR_ATTRIDX(MAIR_ATTR_NORMAL_WT, MT_NORMAL_WT) |		\
65	 MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL_TAGGED))
66
67#ifdef CONFIG_CPU_PM
68/**
69 * cpu_do_suspend - save CPU registers context
70 *
71 * x0: virtual address of context pointer
72 *
73 * This must be kept in sync with struct cpu_suspend_ctx in <asm/suspend.h>.
74 */
75SYM_FUNC_START(cpu_do_suspend)
76	mrs	x2, tpidr_el0
77	mrs	x3, tpidrro_el0
78	mrs	x4, contextidr_el1
79	mrs	x5, osdlr_el1
80	mrs	x6, cpacr_el1
81	mrs	x7, tcr_el1
82	mrs	x8, vbar_el1
83	mrs	x9, mdscr_el1
84	mrs	x10, oslsr_el1
85	mrs	x11, sctlr_el1
86alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
87	mrs	x12, tpidr_el1
88alternative_else
89	mrs	x12, tpidr_el2
90alternative_endif
91	mrs	x13, sp_el0
92	stp	x2, x3, [x0]
93	stp	x4, x5, [x0, #16]
94	stp	x6, x7, [x0, #32]
95	stp	x8, x9, [x0, #48]
96	stp	x10, x11, [x0, #64]
97	stp	x12, x13, [x0, #80]
98	/*
99	 * Save x18 as it may be used as a platform register, e.g. by shadow
100	 * call stack.
101	 */
102	str	x18, [x0, #96]
103	ret
104SYM_FUNC_END(cpu_do_suspend)
105
106/**
107 * cpu_do_resume - restore CPU register context
108 *
109 * x0: Address of context pointer
110 */
111	.pushsection ".idmap.text", "awx"
112SYM_FUNC_START(cpu_do_resume)
113	ldp	x2, x3, [x0]
114	ldp	x4, x5, [x0, #16]
115	ldp	x6, x8, [x0, #32]
116	ldp	x9, x10, [x0, #48]
117	ldp	x11, x12, [x0, #64]
118	ldp	x13, x14, [x0, #80]
119	/*
120	 * Restore x18, as it may be used as a platform register, and clear
121	 * the buffer to minimize the risk of exposure when used for shadow
122	 * call stack.
123	 */
124	ldr	x18, [x0, #96]
125	str	xzr, [x0, #96]
126	msr	tpidr_el0, x2
127	msr	tpidrro_el0, x3
128	msr	contextidr_el1, x4
129	msr	cpacr_el1, x6
130
131	/* Don't change t0sz here, mask those bits when restoring */
132	mrs	x7, tcr_el1
133	bfi	x8, x7, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH
134
135	msr	tcr_el1, x8
136	msr	vbar_el1, x9
137
138	/*
139	 * __cpu_setup() cleared MDSCR_EL1.MDE and friends, before unmasking
140	 * debug exceptions. By restoring MDSCR_EL1 here, we may take a debug
141	 * exception. Mask them until local_daif_restore() in cpu_suspend()
142	 * resets them.
143	 */
144	disable_daif
145	msr	mdscr_el1, x10
146
147	msr	sctlr_el1, x12
148alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
149	msr	tpidr_el1, x13
150alternative_else
151	msr	tpidr_el2, x13
152alternative_endif
153	msr	sp_el0, x14
154	/*
155	 * Restore oslsr_el1 by writing oslar_el1
156	 */
157	msr	osdlr_el1, x5
158	ubfx	x11, x11, #1, #1
159	msr	oslar_el1, x11
160	reset_pmuserenr_el0 x0			// Disable PMU access from EL0
161	reset_amuserenr_el0 x0			// Disable AMU access from EL0
162
163alternative_if ARM64_HAS_RAS_EXTN
164	msr_s	SYS_DISR_EL1, xzr
165alternative_else_nop_endif
166
167	ptrauth_keys_install_kernel_nosync x14, x1, x2, x3
168	isb
169	ret
170SYM_FUNC_END(cpu_do_resume)
171	.popsection
172#endif
173
174	.pushsection ".idmap.text", "awx"
175
176.macro	__idmap_cpu_set_reserved_ttbr1, tmp1, tmp2
177	adrp	\tmp1, reserved_pg_dir
178	phys_to_ttbr \tmp2, \tmp1
179	offset_ttbr1 \tmp2, \tmp1
180	msr	ttbr1_el1, \tmp2
181	isb
182	tlbi	vmalle1
183	dsb	nsh
184	isb
185.endm
186
187/*
188 * void idmap_cpu_replace_ttbr1(phys_addr_t ttbr1)
189 *
190 * This is the low-level counterpart to cpu_replace_ttbr1, and should not be
191 * called by anything else. It can only be executed from a TTBR0 mapping.
192 */
193SYM_FUNC_START(idmap_cpu_replace_ttbr1)
194	save_and_disable_daif flags=x2
195
196	__idmap_cpu_set_reserved_ttbr1 x1, x3
197
198	offset_ttbr1 x0, x3
199	msr	ttbr1_el1, x0
200	isb
201
202	restore_daif x2
203
204	ret
205SYM_FUNC_END(idmap_cpu_replace_ttbr1)
206	.popsection
207
208#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
209	.pushsection ".idmap.text", "awx"
210
211	.macro	__idmap_kpti_get_pgtable_ent, type
212	dc	cvac, cur_\()\type\()p		// Ensure any existing dirty
213	dmb	sy				// lines are written back before
214	ldr	\type, [cur_\()\type\()p]	// loading the entry
215	tbz	\type, #0, skip_\()\type	// Skip invalid and
216	tbnz	\type, #11, skip_\()\type	// non-global entries
217	.endm
218
219	.macro __idmap_kpti_put_pgtable_ent_ng, type
220	orr	\type, \type, #PTE_NG		// Same bit for blocks and pages
221	str	\type, [cur_\()\type\()p]	// Update the entry and ensure
222	dmb	sy				// that it is visible to all
223	dc	civac, cur_\()\type\()p		// CPUs.
224	.endm
225
226/*
227 * void __kpti_install_ng_mappings(int cpu, int num_cpus, phys_addr_t swapper)
228 *
229 * Called exactly once from stop_machine context by each CPU found during boot.
230 */
231__idmap_kpti_flag:
232	.long	1
233SYM_FUNC_START(idmap_kpti_install_ng_mappings)
234	cpu		.req	w0
235	num_cpus	.req	w1
236	swapper_pa	.req	x2
237	swapper_ttb	.req	x3
238	flag_ptr	.req	x4
239	cur_pgdp	.req	x5
240	end_pgdp	.req	x6
241	pgd		.req	x7
242	cur_pudp	.req	x8
243	end_pudp	.req	x9
244	pud		.req	x10
245	cur_pmdp	.req	x11
246	end_pmdp	.req	x12
247	pmd		.req	x13
248	cur_ptep	.req	x14
249	end_ptep	.req	x15
250	pte		.req	x16
251
252	mrs	swapper_ttb, ttbr1_el1
253	restore_ttbr1	swapper_ttb
254	adr	flag_ptr, __idmap_kpti_flag
255
256	cbnz	cpu, __idmap_kpti_secondary
257
258	/* We're the boot CPU. Wait for the others to catch up */
259	sevl
2601:	wfe
261	ldaxr	w17, [flag_ptr]
262	eor	w17, w17, num_cpus
263	cbnz	w17, 1b
264
265	/* We need to walk swapper, so turn off the MMU. */
266	pre_disable_mmu_workaround
267	mrs	x17, sctlr_el1
268	bic	x17, x17, #SCTLR_ELx_M
269	msr	sctlr_el1, x17
270	isb
271
272	/* Everybody is enjoying the idmap, so we can rewrite swapper. */
273	/* PGD */
274	mov	cur_pgdp, swapper_pa
275	add	end_pgdp, cur_pgdp, #(PTRS_PER_PGD * 8)
276do_pgd:	__idmap_kpti_get_pgtable_ent	pgd
277	tbnz	pgd, #1, walk_puds
278next_pgd:
279	__idmap_kpti_put_pgtable_ent_ng	pgd
280skip_pgd:
281	add	cur_pgdp, cur_pgdp, #8
282	cmp	cur_pgdp, end_pgdp
283	b.ne	do_pgd
284
285	/* Publish the updated tables and nuke all the TLBs */
286	dsb	sy
287	tlbi	vmalle1is
288	dsb	ish
289	isb
290
291	/* We're done: fire up the MMU again */
292	mrs	x17, sctlr_el1
293	orr	x17, x17, #SCTLR_ELx_M
294	msr	sctlr_el1, x17
295	isb
296
297	/*
298	 * Invalidate the local I-cache so that any instructions fetched
299	 * speculatively from the PoC are discarded, since they may have
300	 * been dynamically patched at the PoU.
301	 */
302	ic	iallu
303	dsb	nsh
304	isb
305
306	/* Set the flag to zero to indicate that we're all done */
307	str	wzr, [flag_ptr]
308	ret
309
310	/* PUD */
311walk_puds:
312	.if CONFIG_PGTABLE_LEVELS > 3
313	pte_to_phys	cur_pudp, pgd
314	add	end_pudp, cur_pudp, #(PTRS_PER_PUD * 8)
315do_pud:	__idmap_kpti_get_pgtable_ent	pud
316	tbnz	pud, #1, walk_pmds
317next_pud:
318	__idmap_kpti_put_pgtable_ent_ng	pud
319skip_pud:
320	add	cur_pudp, cur_pudp, 8
321	cmp	cur_pudp, end_pudp
322	b.ne	do_pud
323	b	next_pgd
324	.else /* CONFIG_PGTABLE_LEVELS <= 3 */
325	mov	pud, pgd
326	b	walk_pmds
327next_pud:
328	b	next_pgd
329	.endif
330
331	/* PMD */
332walk_pmds:
333	.if CONFIG_PGTABLE_LEVELS > 2
334	pte_to_phys	cur_pmdp, pud
335	add	end_pmdp, cur_pmdp, #(PTRS_PER_PMD * 8)
336do_pmd:	__idmap_kpti_get_pgtable_ent	pmd
337	tbnz	pmd, #1, walk_ptes
338next_pmd:
339	__idmap_kpti_put_pgtable_ent_ng	pmd
340skip_pmd:
341	add	cur_pmdp, cur_pmdp, #8
342	cmp	cur_pmdp, end_pmdp
343	b.ne	do_pmd
344	b	next_pud
345	.else /* CONFIG_PGTABLE_LEVELS <= 2 */
346	mov	pmd, pud
347	b	walk_ptes
348next_pmd:
349	b	next_pud
350	.endif
351
352	/* PTE */
353walk_ptes:
354	pte_to_phys	cur_ptep, pmd
355	add	end_ptep, cur_ptep, #(PTRS_PER_PTE * 8)
356do_pte:	__idmap_kpti_get_pgtable_ent	pte
357	__idmap_kpti_put_pgtable_ent_ng	pte
358skip_pte:
359	add	cur_ptep, cur_ptep, #8
360	cmp	cur_ptep, end_ptep
361	b.ne	do_pte
362	b	next_pmd
363
364	.unreq	cpu
365	.unreq	num_cpus
366	.unreq	swapper_pa
367	.unreq	cur_pgdp
368	.unreq	end_pgdp
369	.unreq	pgd
370	.unreq	cur_pudp
371	.unreq	end_pudp
372	.unreq	pud
373	.unreq	cur_pmdp
374	.unreq	end_pmdp
375	.unreq	pmd
376	.unreq	cur_ptep
377	.unreq	end_ptep
378	.unreq	pte
379
380	/* Secondary CPUs end up here */
381__idmap_kpti_secondary:
382	/* Uninstall swapper before surgery begins */
383	__idmap_cpu_set_reserved_ttbr1 x16, x17
384
385	/* Increment the flag to let the boot CPU we're ready */
3861:	ldxr	w16, [flag_ptr]
387	add	w16, w16, #1
388	stxr	w17, w16, [flag_ptr]
389	cbnz	w17, 1b
390
391	/* Wait for the boot CPU to finish messing around with swapper */
392	sevl
3931:	wfe
394	ldxr	w16, [flag_ptr]
395	cbnz	w16, 1b
396
397	/* All done, act like nothing happened */
398	offset_ttbr1 swapper_ttb, x16
399	msr	ttbr1_el1, swapper_ttb
400	isb
401	ret
402
403	.unreq	swapper_ttb
404	.unreq	flag_ptr
405SYM_FUNC_END(idmap_kpti_install_ng_mappings)
406	.popsection
407#endif
408
409/*
410 *	__cpu_setup
411 *
412 *	Initialise the processor for turning the MMU on.
413 *
414 * Output:
415 *	Return in x0 the value of the SCTLR_EL1 register.
416 */
417	.pushsection ".idmap.text", "awx"
418SYM_FUNC_START(__cpu_setup)
419	tlbi	vmalle1				// Invalidate local TLB
420	dsb	nsh
421
422	mov	x1, #3 << 20
423	msr	cpacr_el1, x1			// Enable FP/ASIMD
424	mov	x1, #1 << 12			// Reset mdscr_el1 and disable
425	msr	mdscr_el1, x1			// access to the DCC from EL0
426	isb					// Unmask debug exceptions now,
427	enable_dbg				// since this is per-cpu
428	reset_pmuserenr_el0 x1			// Disable PMU access from EL0
429	reset_amuserenr_el0 x1			// Disable AMU access from EL0
430
431	/*
432	 * Memory region attributes
433	 */
434	mov_q	x5, MAIR_EL1_SET
435#ifdef CONFIG_ARM64_MTE
436	mte_tcr	.req	x20
437
438	mov	mte_tcr, #0
439
440	/*
441	 * Update MAIR_EL1, GCR_EL1 and TFSR*_EL1 if MTE is supported
442	 * (ID_AA64PFR1_EL1[11:8] > 1).
443	 */
444	mrs	x10, ID_AA64PFR1_EL1
445	ubfx	x10, x10, #ID_AA64PFR1_MTE_SHIFT, #4
446	cmp	x10, #ID_AA64PFR1_MTE
447	b.lt	1f
448
449	/* Normal Tagged memory type at the corresponding MAIR index */
450	mov	x10, #MAIR_ATTR_NORMAL_TAGGED
451	bfi	x5, x10, #(8 *  MT_NORMAL_TAGGED), #8
452
453	/* initialize GCR_EL1: all non-zero tags excluded by default */
454	mov	x10, #(SYS_GCR_EL1_RRND | SYS_GCR_EL1_EXCL_MASK)
455	msr_s	SYS_GCR_EL1, x10
456
457	/* clear any pending tag check faults in TFSR*_EL1 */
458	msr_s	SYS_TFSR_EL1, xzr
459	msr_s	SYS_TFSRE0_EL1, xzr
460
461	/* set the TCR_EL1 bits */
462	mov_q	mte_tcr, TCR_KASAN_HW_FLAGS
4631:
464#endif
465	msr	mair_el1, x5
466	/*
467	 * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for
468	 * both user and kernel.
469	 */
470	mov_q	x10, TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \
471			TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \
472			TCR_TBI0 | TCR_A1 | TCR_KASAN_SW_FLAGS
473#ifdef CONFIG_ARM64_MTE
474	orr	x10, x10, mte_tcr
475	.unreq	mte_tcr
476#endif
477	tcr_clear_errata_bits x10, x9, x5
478
479#ifdef CONFIG_ARM64_VA_BITS_52
480	ldr_l		x9, vabits_actual
481	sub		x9, xzr, x9
482	add		x9, x9, #64
483	tcr_set_t1sz	x10, x9
484#else
485	ldr_l		x9, idmap_t0sz
486#endif
487	tcr_set_t0sz	x10, x9
488
489	/*
490	 * Set the IPS bits in TCR_EL1.
491	 */
492	tcr_compute_pa_size x10, #TCR_IPS_SHIFT, x5, x6
493#ifdef CONFIG_ARM64_HW_AFDBM
494	/*
495	 * Enable hardware update of the Access Flags bit.
496	 * Hardware dirty bit management is enabled later,
497	 * via capabilities.
498	 */
499	mrs	x9, ID_AA64MMFR1_EL1
500	and	x9, x9, #0xf
501	cbz	x9, 1f
502	orr	x10, x10, #TCR_HA		// hardware Access flag update
5031:
504#endif	/* CONFIG_ARM64_HW_AFDBM */
505	msr	tcr_el1, x10
506	/*
507	 * Prepare SCTLR
508	 */
509	mov_q	x0, INIT_SCTLR_EL1_MMU_ON
510	ret					// return to head.S
511SYM_FUNC_END(__cpu_setup)
512