1/* 2 * Based on arch/arm/mm/proc.S 3 * 4 * Copyright (C) 2001 Deep Blue Solutions Ltd. 5 * Copyright (C) 2012 ARM Ltd. 6 * Author: Catalin Marinas <catalin.marinas@arm.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21#include <linux/init.h> 22#include <linux/linkage.h> 23#include <asm/assembler.h> 24#include <asm/asm-offsets.h> 25#include <asm/hwcap.h> 26#include <asm/pgtable-hwdef.h> 27#include <asm/pgtable.h> 28 29#include "proc-macros.S" 30 31#ifdef CONFIG_ARM64_64K_PAGES 32#define TCR_TG_FLAGS TCR_TG0_64K | TCR_TG1_64K 33#elif defined(CONFIG_ARM64_16K_PAGES) 34#define TCR_TG_FLAGS TCR_TG0_16K | TCR_TG1_16K 35#else /* CONFIG_ARM64_4K_PAGES */ 36#define TCR_TG_FLAGS TCR_TG0_4K | TCR_TG1_4K 37#endif 38 39#define TCR_SMP_FLAGS TCR_SHARED 40 41/* PTWs cacheable, inner/outer WBWA */ 42#define TCR_CACHE_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA 43 44#define MAIR(attr, mt) ((attr) << ((mt) * 8)) 45 46/* 47 * cpu_do_idle() 48 * 49 * Idle the processor (wait for interrupt). 50 */ 51ENTRY(cpu_do_idle) 52 dsb sy // WFI may enter a low-power mode 53 wfi 54 ret 55ENDPROC(cpu_do_idle) 56 57#ifdef CONFIG_CPU_PM 58/** 59 * cpu_do_suspend - save CPU registers context 60 * 61 * x0: virtual address of context pointer 62 */ 63ENTRY(cpu_do_suspend) 64 mrs x2, tpidr_el0 65 mrs x3, tpidrro_el0 66 mrs x4, contextidr_el1 67 mrs x5, mair_el1 68 mrs x6, cpacr_el1 69 mrs x7, ttbr1_el1 70 mrs x8, tcr_el1 71 mrs x9, vbar_el1 72 mrs x10, mdscr_el1 73 mrs x11, oslsr_el1 74 mrs x12, sctlr_el1 75 stp x2, x3, [x0] 76 stp x4, x5, [x0, #16] 77 stp x6, x7, [x0, #32] 78 stp x8, x9, [x0, #48] 79 stp x10, x11, [x0, #64] 80 str x12, [x0, #80] 81 ret 82ENDPROC(cpu_do_suspend) 83 84/** 85 * cpu_do_resume - restore CPU register context 86 * 87 * x0: Physical address of context pointer 88 * x1: ttbr0_el1 to be restored 89 * 90 * Returns: 91 * sctlr_el1 value in x0 92 */ 93ENTRY(cpu_do_resume) 94 /* 95 * Invalidate local tlb entries before turning on MMU 96 */ 97 tlbi vmalle1 98 ldp x2, x3, [x0] 99 ldp x4, x5, [x0, #16] 100 ldp x6, x7, [x0, #32] 101 ldp x8, x9, [x0, #48] 102 ldp x10, x11, [x0, #64] 103 ldr x12, [x0, #80] 104 msr tpidr_el0, x2 105 msr tpidrro_el0, x3 106 msr contextidr_el1, x4 107 msr mair_el1, x5 108 msr cpacr_el1, x6 109 msr ttbr0_el1, x1 110 msr ttbr1_el1, x7 111 tcr_set_idmap_t0sz x8, x7 112 msr tcr_el1, x8 113 msr vbar_el1, x9 114 msr mdscr_el1, x10 115 /* 116 * Restore oslsr_el1 by writing oslar_el1 117 */ 118 ubfx x11, x11, #1, #1 119 msr oslar_el1, x11 120 msr pmuserenr_el0, xzr // Disable PMU access from EL0 121 mov x0, x12 122 dsb nsh // Make sure local tlb invalidation completed 123 isb 124 ret 125ENDPROC(cpu_do_resume) 126#endif 127 128/* 129 * cpu_do_switch_mm(pgd_phys, tsk) 130 * 131 * Set the translation table base pointer to be pgd_phys. 132 * 133 * - pgd_phys - physical address of new TTB 134 */ 135ENTRY(cpu_do_switch_mm) 136 mmid x1, x1 // get mm->context.id 137 bfi x0, x1, #48, #16 // set the ASID 138 msr ttbr0_el1, x0 // set TTBR0 139 isb 140 ret 141ENDPROC(cpu_do_switch_mm) 142 143 .section ".text.init", #alloc, #execinstr 144 145/* 146 * __cpu_setup 147 * 148 * Initialise the processor for turning the MMU on. Return in x0 the 149 * value of the SCTLR_EL1 register. 150 */ 151ENTRY(__cpu_setup) 152 tlbi vmalle1 // Invalidate local TLB 153 dsb nsh 154 155 mov x0, #3 << 20 156 msr cpacr_el1, x0 // Enable FP/ASIMD 157 mov x0, #1 << 12 // Reset mdscr_el1 and disable 158 msr mdscr_el1, x0 // access to the DCC from EL0 159 msr pmuserenr_el0, xzr // Disable PMU access from EL0 160 /* 161 * Memory region attributes for LPAE: 162 * 163 * n = AttrIndx[2:0] 164 * n MAIR 165 * DEVICE_nGnRnE 000 00000000 166 * DEVICE_nGnRE 001 00000100 167 * DEVICE_GRE 010 00001100 168 * NORMAL_NC 011 01000100 169 * NORMAL 100 11111111 170 * NORMAL_WT 101 10111011 171 */ 172 ldr x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \ 173 MAIR(0x04, MT_DEVICE_nGnRE) | \ 174 MAIR(0x0c, MT_DEVICE_GRE) | \ 175 MAIR(0x44, MT_NORMAL_NC) | \ 176 MAIR(0xff, MT_NORMAL) | \ 177 MAIR(0xbb, MT_NORMAL_WT) 178 msr mair_el1, x5 179 /* 180 * Prepare SCTLR 181 */ 182 adr x5, crval 183 ldp w5, w6, [x5] 184 mrs x0, sctlr_el1 185 bic x0, x0, x5 // clear bits 186 orr x0, x0, x6 // set bits 187 /* 188 * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for 189 * both user and kernel. 190 */ 191 ldr x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \ 192 TCR_TG_FLAGS | TCR_ASID16 | TCR_TBI0 193 tcr_set_idmap_t0sz x10, x9 194 195 /* 196 * Read the PARange bits from ID_AA64MMFR0_EL1 and set the IPS bits in 197 * TCR_EL1. 198 */ 199 mrs x9, ID_AA64MMFR0_EL1 200 bfi x10, x9, #32, #3 201#ifdef CONFIG_ARM64_HW_AFDBM 202 /* 203 * Hardware update of the Access and Dirty bits. 204 */ 205 mrs x9, ID_AA64MMFR1_EL1 206 and x9, x9, #0xf 207 cbz x9, 2f 208 cmp x9, #2 209 b.lt 1f 210 orr x10, x10, #TCR_HD // hardware Dirty flag update 2111: orr x10, x10, #TCR_HA // hardware Access flag update 2122: 213#endif /* CONFIG_ARM64_HW_AFDBM */ 214 msr tcr_el1, x10 215 ret // return to head.S 216ENDPROC(__cpu_setup) 217 218 /* 219 * We set the desired value explicitly, including those of the 220 * reserved bits. The values of bits EE & E0E were set early in 221 * el2_setup, which are left untouched below. 222 * 223 * n n T 224 * U E WT T UD US IHBS 225 * CE0 XWHW CZ ME TEEA S 226 * .... .IEE .... NEAI TE.I ..AD DEN0 ACAM 227 * 0011 0... 1101 ..0. ..0. 10.. .0.. .... < hardware reserved 228 * .... .1.. .... 01.1 11.1 ..01 0.01 1101 < software settings 229 */ 230 .type crval, #object 231crval: 232 .word 0xfcffffff // clear 233 .word 0x34d5d91d // set 234