1/* 2 * Based on arch/arm/mm/proc.S 3 * 4 * Copyright (C) 2001 Deep Blue Solutions Ltd. 5 * Copyright (C) 2012 ARM Ltd. 6 * Author: Catalin Marinas <catalin.marinas@arm.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21#include <linux/init.h> 22#include <linux/linkage.h> 23#include <asm/assembler.h> 24#include <asm/asm-offsets.h> 25#include <asm/hwcap.h> 26#include <asm/pgtable-hwdef.h> 27#include <asm/pgtable.h> 28 29#include "proc-macros.S" 30 31#ifdef CONFIG_ARM64_64K_PAGES 32#define TCR_TG_FLAGS TCR_TG0_64K | TCR_TG1_64K 33#elif defined(CONFIG_ARM64_16K_PAGES) 34#define TCR_TG_FLAGS TCR_TG0_16K | TCR_TG1_16K 35#else /* CONFIG_ARM64_4K_PAGES */ 36#define TCR_TG_FLAGS TCR_TG0_4K | TCR_TG1_4K 37#endif 38 39#define TCR_SMP_FLAGS TCR_SHARED 40 41/* PTWs cacheable, inner/outer WBWA */ 42#define TCR_CACHE_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA 43 44#define MAIR(attr, mt) ((attr) << ((mt) * 8)) 45 46/* 47 * cpu_do_idle() 48 * 49 * Idle the processor (wait for interrupt). 50 */ 51ENTRY(cpu_do_idle) 52 dsb sy // WFI may enter a low-power mode 53 wfi 54 ret 55ENDPROC(cpu_do_idle) 56 57#ifdef CONFIG_CPU_PM 58/** 59 * cpu_do_suspend - save CPU registers context 60 * 61 * x0: virtual address of context pointer 62 */ 63ENTRY(cpu_do_suspend) 64 mrs x2, tpidr_el0 65 mrs x3, tpidrro_el0 66 mrs x4, contextidr_el1 67 mrs x5, mair_el1 68 mrs x6, cpacr_el1 69 mrs x7, ttbr1_el1 70 mrs x8, tcr_el1 71 mrs x9, vbar_el1 72 mrs x10, mdscr_el1 73 mrs x11, oslsr_el1 74 mrs x12, sctlr_el1 75 stp x2, x3, [x0] 76 stp x4, x5, [x0, #16] 77 stp x6, x7, [x0, #32] 78 stp x8, x9, [x0, #48] 79 stp x10, x11, [x0, #64] 80 str x12, [x0, #80] 81 ret 82ENDPROC(cpu_do_suspend) 83 84/** 85 * cpu_do_resume - restore CPU register context 86 * 87 * x0: Physical address of context pointer 88 * x1: ttbr0_el1 to be restored 89 * 90 * Returns: 91 * sctlr_el1 value in x0 92 */ 93ENTRY(cpu_do_resume) 94 /* 95 * Invalidate local tlb entries before turning on MMU 96 */ 97 tlbi vmalle1 98 ldp x2, x3, [x0] 99 ldp x4, x5, [x0, #16] 100 ldp x6, x7, [x0, #32] 101 ldp x8, x9, [x0, #48] 102 ldp x10, x11, [x0, #64] 103 ldr x12, [x0, #80] 104 msr tpidr_el0, x2 105 msr tpidrro_el0, x3 106 msr contextidr_el1, x4 107 msr mair_el1, x5 108 msr cpacr_el1, x6 109 msr ttbr0_el1, x1 110 msr ttbr1_el1, x7 111 tcr_set_idmap_t0sz x8, x7 112 msr tcr_el1, x8 113 msr vbar_el1, x9 114 msr mdscr_el1, x10 115 /* 116 * Restore oslsr_el1 by writing oslar_el1 117 */ 118 ubfx x11, x11, #1, #1 119 msr oslar_el1, x11 120 reset_pmuserenr_el0 x0 // Disable PMU access from EL0 121 mov x0, x12 122 dsb nsh // Make sure local tlb invalidation completed 123 isb 124 ret 125ENDPROC(cpu_do_resume) 126#endif 127 128/* 129 * cpu_do_switch_mm(pgd_phys, tsk) 130 * 131 * Set the translation table base pointer to be pgd_phys. 132 * 133 * - pgd_phys - physical address of new TTB 134 */ 135ENTRY(cpu_do_switch_mm) 136 mmid x1, x1 // get mm->context.id 137 bfi x0, x1, #48, #16 // set the ASID 138 msr ttbr0_el1, x0 // set TTBR0 139 isb 140 ret 141ENDPROC(cpu_do_switch_mm) 142 143 .pushsection ".idmap.text", "ax" 144/* 145 * void idmap_cpu_replace_ttbr1(phys_addr_t new_pgd) 146 * 147 * This is the low-level counterpart to cpu_replace_ttbr1, and should not be 148 * called by anything else. It can only be executed from a TTBR0 mapping. 149 */ 150ENTRY(idmap_cpu_replace_ttbr1) 151 mrs x2, daif 152 msr daifset, #0xf 153 154 adrp x1, empty_zero_page 155 msr ttbr1_el1, x1 156 isb 157 158 tlbi vmalle1 159 dsb nsh 160 isb 161 162 msr ttbr1_el1, x0 163 isb 164 165 msr daif, x2 166 167 ret 168ENDPROC(idmap_cpu_replace_ttbr1) 169 .popsection 170 171/* 172 * __cpu_setup 173 * 174 * Initialise the processor for turning the MMU on. Return in x0 the 175 * value of the SCTLR_EL1 register. 176 */ 177ENTRY(__cpu_setup) 178 tlbi vmalle1 // Invalidate local TLB 179 dsb nsh 180 181 mov x0, #3 << 20 182 msr cpacr_el1, x0 // Enable FP/ASIMD 183 mov x0, #1 << 12 // Reset mdscr_el1 and disable 184 msr mdscr_el1, x0 // access to the DCC from EL0 185 reset_pmuserenr_el0 x0 // Disable PMU access from EL0 186 /* 187 * Memory region attributes for LPAE: 188 * 189 * n = AttrIndx[2:0] 190 * n MAIR 191 * DEVICE_nGnRnE 000 00000000 192 * DEVICE_nGnRE 001 00000100 193 * DEVICE_GRE 010 00001100 194 * NORMAL_NC 011 01000100 195 * NORMAL 100 11111111 196 * NORMAL_WT 101 10111011 197 */ 198 ldr x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \ 199 MAIR(0x04, MT_DEVICE_nGnRE) | \ 200 MAIR(0x0c, MT_DEVICE_GRE) | \ 201 MAIR(0x44, MT_NORMAL_NC) | \ 202 MAIR(0xff, MT_NORMAL) | \ 203 MAIR(0xbb, MT_NORMAL_WT) 204 msr mair_el1, x5 205 /* 206 * Prepare SCTLR 207 */ 208 adr x5, crval 209 ldp w5, w6, [x5] 210 mrs x0, sctlr_el1 211 bic x0, x0, x5 // clear bits 212 orr x0, x0, x6 // set bits 213 /* 214 * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for 215 * both user and kernel. 216 */ 217 ldr x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \ 218 TCR_TG_FLAGS | TCR_ASID16 | TCR_TBI0 219 tcr_set_idmap_t0sz x10, x9 220 221 /* 222 * Read the PARange bits from ID_AA64MMFR0_EL1 and set the IPS bits in 223 * TCR_EL1. 224 */ 225 mrs x9, ID_AA64MMFR0_EL1 226 bfi x10, x9, #32, #3 227#ifdef CONFIG_ARM64_HW_AFDBM 228 /* 229 * Hardware update of the Access and Dirty bits. 230 */ 231 mrs x9, ID_AA64MMFR1_EL1 232 and x9, x9, #0xf 233 cbz x9, 2f 234 cmp x9, #2 235 b.lt 1f 236 orr x10, x10, #TCR_HD // hardware Dirty flag update 2371: orr x10, x10, #TCR_HA // hardware Access flag update 2382: 239#endif /* CONFIG_ARM64_HW_AFDBM */ 240 msr tcr_el1, x10 241 ret // return to head.S 242ENDPROC(__cpu_setup) 243 244 /* 245 * We set the desired value explicitly, including those of the 246 * reserved bits. The values of bits EE & E0E were set early in 247 * el2_setup, which are left untouched below. 248 * 249 * n n T 250 * U E WT T UD US IHBS 251 * CE0 XWHW CZ ME TEEA S 252 * .... .IEE .... NEAI TE.I ..AD DEN0 ACAM 253 * 0011 0... 1101 ..0. ..0. 10.. .0.. .... < hardware reserved 254 * .... .1.. .... 01.1 11.1 ..01 0.01 1101 < software settings 255 */ 256 .type crval, #object 257crval: 258 .word 0xfcffffff // clear 259 .word 0x34d5d91d // set 260