xref: /openbmc/linux/arch/arm64/mm/proc.S (revision 133f9794) 
1/*
2 * Based on arch/arm/mm/proc.S
3 *
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
5 * Copyright (C) 2012 ARM Ltd.
6 * Author: Catalin Marinas <catalin.marinas@arm.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#include <linux/init.h>
22#include <linux/linkage.h>
23#include <asm/assembler.h>
24#include <asm/asm-offsets.h>
25#include <asm/hwcap.h>
26#include <asm/pgtable.h>
27#include <asm/pgtable-hwdef.h>
28#include <asm/cpufeature.h>
29#include <asm/alternative.h>
30
31#ifdef CONFIG_ARM64_64K_PAGES
32#define TCR_TG_FLAGS	TCR_TG0_64K | TCR_TG1_64K
33#elif defined(CONFIG_ARM64_16K_PAGES)
34#define TCR_TG_FLAGS	TCR_TG0_16K | TCR_TG1_16K
35#else /* CONFIG_ARM64_4K_PAGES */
36#define TCR_TG_FLAGS	TCR_TG0_4K | TCR_TG1_4K
37#endif
38
39#define TCR_SMP_FLAGS	TCR_SHARED
40
41/* PTWs cacheable, inner/outer WBWA */
42#define TCR_CACHE_FLAGS	TCR_IRGN_WBWA | TCR_ORGN_WBWA
43
44#define MAIR(attr, mt)	((attr) << ((mt) * 8))
45
46/*
47 *	cpu_do_idle()
48 *
49 *	Idle the processor (wait for interrupt).
50 */
51ENTRY(cpu_do_idle)
52	dsb	sy				// WFI may enter a low-power mode
53	wfi
54	ret
55ENDPROC(cpu_do_idle)
56
57#ifdef CONFIG_CPU_PM
58/**
59 * cpu_do_suspend - save CPU registers context
60 *
61 * x0: virtual address of context pointer
62 */
63ENTRY(cpu_do_suspend)
64	mrs	x2, tpidr_el0
65	mrs	x3, tpidrro_el0
66	mrs	x4, contextidr_el1
67	mrs	x5, cpacr_el1
68	mrs	x6, tcr_el1
69	mrs	x7, vbar_el1
70	mrs	x8, mdscr_el1
71	mrs	x9, oslsr_el1
72	mrs	x10, sctlr_el1
73alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
74	mrs	x11, tpidr_el1
75alternative_else
76	mrs	x11, tpidr_el2
77alternative_endif
78	mrs	x12, sp_el0
79	stp	x2, x3, [x0]
80	stp	x4, xzr, [x0, #16]
81	stp	x5, x6, [x0, #32]
82	stp	x7, x8, [x0, #48]
83	stp	x9, x10, [x0, #64]
84	stp	x11, x12, [x0, #80]
85	ret
86ENDPROC(cpu_do_suspend)
87
88/**
89 * cpu_do_resume - restore CPU register context
90 *
91 * x0: Address of context pointer
92 */
93	.pushsection ".idmap.text", "awx"
94ENTRY(cpu_do_resume)
95	ldp	x2, x3, [x0]
96	ldp	x4, x5, [x0, #16]
97	ldp	x6, x8, [x0, #32]
98	ldp	x9, x10, [x0, #48]
99	ldp	x11, x12, [x0, #64]
100	ldp	x13, x14, [x0, #80]
101	msr	tpidr_el0, x2
102	msr	tpidrro_el0, x3
103	msr	contextidr_el1, x4
104	msr	cpacr_el1, x6
105
106	/* Don't change t0sz here, mask those bits when restoring */
107	mrs	x5, tcr_el1
108	bfi	x8, x5, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH
109
110	msr	tcr_el1, x8
111	msr	vbar_el1, x9
112
113	/*
114	 * __cpu_setup() cleared MDSCR_EL1.MDE and friends, before unmasking
115	 * debug exceptions. By restoring MDSCR_EL1 here, we may take a debug
116	 * exception. Mask them until local_daif_restore() in cpu_suspend()
117	 * resets them.
118	 */
119	disable_daif
120	msr	mdscr_el1, x10
121
122	msr	sctlr_el1, x12
123alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
124	msr	tpidr_el1, x13
125alternative_else
126	msr	tpidr_el2, x13
127alternative_endif
128	msr	sp_el0, x14
129	/*
130	 * Restore oslsr_el1 by writing oslar_el1
131	 */
132	ubfx	x11, x11, #1, #1
133	msr	oslar_el1, x11
134	reset_pmuserenr_el0 x0			// Disable PMU access from EL0
135
136alternative_if ARM64_HAS_RAS_EXTN
137	msr_s	SYS_DISR_EL1, xzr
138alternative_else_nop_endif
139
140	isb
141	ret
142ENDPROC(cpu_do_resume)
143	.popsection
144#endif
145
146/*
147 *	cpu_do_switch_mm(pgd_phys, tsk)
148 *
149 *	Set the translation table base pointer to be pgd_phys.
150 *
151 *	- pgd_phys - physical address of new TTB
152 */
153ENTRY(cpu_do_switch_mm)
154	mrs	x2, ttbr1_el1
155	mmid	x1, x1				// get mm->context.id
156	phys_to_ttbr x3, x0
157#ifdef CONFIG_ARM64_SW_TTBR0_PAN
158	bfi	x3, x1, #48, #16		// set the ASID field in TTBR0
159#endif
160	bfi	x2, x1, #48, #16		// set the ASID
161	msr	ttbr1_el1, x2			// in TTBR1 (since TCR.A1 is set)
162	isb
163	msr	ttbr0_el1, x3			// now update TTBR0
164	isb
165	b	post_ttbr_update_workaround	// Back to C code...
166ENDPROC(cpu_do_switch_mm)
167
168	.pushsection ".idmap.text", "awx"
169
170.macro	__idmap_cpu_set_reserved_ttbr1, tmp1, tmp2
171	adrp	\tmp1, empty_zero_page
172	phys_to_ttbr \tmp2, \tmp1
173	msr	ttbr1_el1, \tmp2
174	isb
175	tlbi	vmalle1
176	dsb	nsh
177	isb
178.endm
179
180/*
181 * void idmap_cpu_replace_ttbr1(phys_addr_t new_pgd)
182 *
183 * This is the low-level counterpart to cpu_replace_ttbr1, and should not be
184 * called by anything else. It can only be executed from a TTBR0 mapping.
185 */
186ENTRY(idmap_cpu_replace_ttbr1)
187	save_and_disable_daif flags=x2
188
189	__idmap_cpu_set_reserved_ttbr1 x1, x3
190
191	phys_to_ttbr x3, x0
192	msr	ttbr1_el1, x3
193	isb
194
195	restore_daif x2
196
197	ret
198ENDPROC(idmap_cpu_replace_ttbr1)
199	.popsection
200
201#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
202	.pushsection ".idmap.text", "awx"
203
204	.macro	__idmap_kpti_get_pgtable_ent, type
205	dc	cvac, cur_\()\type\()p		// Ensure any existing dirty
206	dmb	sy				// lines are written back before
207	ldr	\type, [cur_\()\type\()p]	// loading the entry
208	tbz	\type, #0, next_\()\type	// Skip invalid entries
209	.endm
210
211	.macro __idmap_kpti_put_pgtable_ent_ng, type
212	orr	\type, \type, #PTE_NG		// Same bit for blocks and pages
213	str	\type, [cur_\()\type\()p]	// Update the entry and ensure it
214	dc	civac, cur_\()\type\()p		// is visible to all CPUs.
215	.endm
216
217/*
218 * void __kpti_install_ng_mappings(int cpu, int num_cpus, phys_addr_t swapper)
219 *
220 * Called exactly once from stop_machine context by each CPU found during boot.
221 */
222__idmap_kpti_flag:
223	.long	1
224ENTRY(idmap_kpti_install_ng_mappings)
225	cpu		.req	w0
226	num_cpus	.req	w1
227	swapper_pa	.req	x2
228	swapper_ttb	.req	x3
229	flag_ptr	.req	x4
230	cur_pgdp	.req	x5
231	end_pgdp	.req	x6
232	pgd		.req	x7
233	cur_pudp	.req	x8
234	end_pudp	.req	x9
235	pud		.req	x10
236	cur_pmdp	.req	x11
237	end_pmdp	.req	x12
238	pmd		.req	x13
239	cur_ptep	.req	x14
240	end_ptep	.req	x15
241	pte		.req	x16
242
243	mrs	swapper_ttb, ttbr1_el1
244	adr	flag_ptr, __idmap_kpti_flag
245
246	cbnz	cpu, __idmap_kpti_secondary
247
248	/* We're the boot CPU. Wait for the others to catch up */
249	sevl
2501:	wfe
251	ldaxr	w18, [flag_ptr]
252	eor	w18, w18, num_cpus
253	cbnz	w18, 1b
254
255	/* We need to walk swapper, so turn off the MMU. */
256	pre_disable_mmu_workaround
257	mrs	x18, sctlr_el1
258	bic	x18, x18, #SCTLR_ELx_M
259	msr	sctlr_el1, x18
260	isb
261
262	/* Everybody is enjoying the idmap, so we can rewrite swapper. */
263	/* PGD */
264	mov	cur_pgdp, swapper_pa
265	add	end_pgdp, cur_pgdp, #(PTRS_PER_PGD * 8)
266do_pgd:	__idmap_kpti_get_pgtable_ent	pgd
267	tbnz	pgd, #1, walk_puds
268	__idmap_kpti_put_pgtable_ent_ng	pgd
269next_pgd:
270	add	cur_pgdp, cur_pgdp, #8
271	cmp	cur_pgdp, end_pgdp
272	b.ne	do_pgd
273
274	/* Publish the updated tables and nuke all the TLBs */
275	dsb	sy
276	tlbi	vmalle1is
277	dsb	ish
278	isb
279
280	/* We're done: fire up the MMU again */
281	mrs	x18, sctlr_el1
282	orr	x18, x18, #SCTLR_ELx_M
283	msr	sctlr_el1, x18
284	isb
285
286	/* Set the flag to zero to indicate that we're all done */
287	str	wzr, [flag_ptr]
288	ret
289
290	/* PUD */
291walk_puds:
292	.if CONFIG_PGTABLE_LEVELS > 3
293	pte_to_phys	cur_pudp, pgd
294	add	end_pudp, cur_pudp, #(PTRS_PER_PUD * 8)
295do_pud:	__idmap_kpti_get_pgtable_ent	pud
296	tbnz	pud, #1, walk_pmds
297	__idmap_kpti_put_pgtable_ent_ng	pud
298next_pud:
299	add	cur_pudp, cur_pudp, 8
300	cmp	cur_pudp, end_pudp
301	b.ne	do_pud
302	b	next_pgd
303	.else /* CONFIG_PGTABLE_LEVELS <= 3 */
304	mov	pud, pgd
305	b	walk_pmds
306next_pud:
307	b	next_pgd
308	.endif
309
310	/* PMD */
311walk_pmds:
312	.if CONFIG_PGTABLE_LEVELS > 2
313	pte_to_phys	cur_pmdp, pud
314	add	end_pmdp, cur_pmdp, #(PTRS_PER_PMD * 8)
315do_pmd:	__idmap_kpti_get_pgtable_ent	pmd
316	tbnz	pmd, #1, walk_ptes
317	__idmap_kpti_put_pgtable_ent_ng	pmd
318next_pmd:
319	add	cur_pmdp, cur_pmdp, #8
320	cmp	cur_pmdp, end_pmdp
321	b.ne	do_pmd
322	b	next_pud
323	.else /* CONFIG_PGTABLE_LEVELS <= 2 */
324	mov	pmd, pud
325	b	walk_ptes
326next_pmd:
327	b	next_pud
328	.endif
329
330	/* PTE */
331walk_ptes:
332	pte_to_phys	cur_ptep, pmd
333	add	end_ptep, cur_ptep, #(PTRS_PER_PTE * 8)
334do_pte:	__idmap_kpti_get_pgtable_ent	pte
335	__idmap_kpti_put_pgtable_ent_ng	pte
336next_pte:
337	add	cur_ptep, cur_ptep, #8
338	cmp	cur_ptep, end_ptep
339	b.ne	do_pte
340	b	next_pmd
341
342	/* Secondary CPUs end up here */
343__idmap_kpti_secondary:
344	/* Uninstall swapper before surgery begins */
345	__idmap_cpu_set_reserved_ttbr1 x18, x17
346
347	/* Increment the flag to let the boot CPU we're ready */
3481:	ldxr	w18, [flag_ptr]
349	add	w18, w18, #1
350	stxr	w17, w18, [flag_ptr]
351	cbnz	w17, 1b
352
353	/* Wait for the boot CPU to finish messing around with swapper */
354	sevl
3551:	wfe
356	ldxr	w18, [flag_ptr]
357	cbnz	w18, 1b
358
359	/* All done, act like nothing happened */
360	msr	ttbr1_el1, swapper_ttb
361	isb
362	ret
363
364	.unreq	cpu
365	.unreq	num_cpus
366	.unreq	swapper_pa
367	.unreq	swapper_ttb
368	.unreq	flag_ptr
369	.unreq	cur_pgdp
370	.unreq	end_pgdp
371	.unreq	pgd
372	.unreq	cur_pudp
373	.unreq	end_pudp
374	.unreq	pud
375	.unreq	cur_pmdp
376	.unreq	end_pmdp
377	.unreq	pmd
378	.unreq	cur_ptep
379	.unreq	end_ptep
380	.unreq	pte
381ENDPROC(idmap_kpti_install_ng_mappings)
382	.popsection
383#endif
384
385/*
386 *	__cpu_setup
387 *
388 *	Initialise the processor for turning the MMU on.  Return in x0 the
389 *	value of the SCTLR_EL1 register.
390 */
391	.pushsection ".idmap.text", "awx"
392ENTRY(__cpu_setup)
393	tlbi	vmalle1				// Invalidate local TLB
394	dsb	nsh
395
396	mov	x0, #3 << 20
397	msr	cpacr_el1, x0			// Enable FP/ASIMD
398	mov	x0, #1 << 12			// Reset mdscr_el1 and disable
399	msr	mdscr_el1, x0			// access to the DCC from EL0
400	isb					// Unmask debug exceptions now,
401	enable_dbg				// since this is per-cpu
402	reset_pmuserenr_el0 x0			// Disable PMU access from EL0
403	/*
404	 * Memory region attributes for LPAE:
405	 *
406	 *   n = AttrIndx[2:0]
407	 *			n	MAIR
408	 *   DEVICE_nGnRnE	000	00000000
409	 *   DEVICE_nGnRE	001	00000100
410	 *   DEVICE_GRE		010	00001100
411	 *   NORMAL_NC		011	01000100
412	 *   NORMAL		100	11111111
413	 *   NORMAL_WT		101	10111011
414	 */
415	ldr	x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \
416		     MAIR(0x04, MT_DEVICE_nGnRE) | \
417		     MAIR(0x0c, MT_DEVICE_GRE) | \
418		     MAIR(0x44, MT_NORMAL_NC) | \
419		     MAIR(0xff, MT_NORMAL) | \
420		     MAIR(0xbb, MT_NORMAL_WT)
421	msr	mair_el1, x5
422	/*
423	 * Prepare SCTLR
424	 */
425	mov_q	x0, SCTLR_EL1_SET
426	/*
427	 * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for
428	 * both user and kernel.
429	 */
430	ldr	x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \
431			TCR_TG_FLAGS | TCR_ASID16 | TCR_TBI0 | TCR_A1
432	tcr_set_idmap_t0sz	x10, x9
433
434	/*
435	 * Set the IPS bits in TCR_EL1.
436	 */
437	tcr_compute_pa_size x10, #TCR_IPS_SHIFT, x5, x6
438#ifdef CONFIG_ARM64_HW_AFDBM
439	/*
440	 * Hardware update of the Access and Dirty bits.
441	 */
442	mrs	x9, ID_AA64MMFR1_EL1
443	and	x9, x9, #0xf
444	cbz	x9, 2f
445	cmp	x9, #2
446	b.lt	1f
447	orr	x10, x10, #TCR_HD		// hardware Dirty flag update
4481:	orr	x10, x10, #TCR_HA		// hardware Access flag update
4492:
450#endif	/* CONFIG_ARM64_HW_AFDBM */
451	msr	tcr_el1, x10
452	ret					// return to head.S
453ENDPROC(__cpu_setup)
454