1/* 2 * Based on arch/arm/mm/proc.S 3 * 4 * Copyright (C) 2001 Deep Blue Solutions Ltd. 5 * Copyright (C) 2012 ARM Ltd. 6 * Author: Catalin Marinas <catalin.marinas@arm.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21#include <linux/init.h> 22#include <linux/linkage.h> 23#include <asm/assembler.h> 24#include <asm/asm-offsets.h> 25#include <asm/hwcap.h> 26#include <asm/pgtable-hwdef.h> 27#include <asm/pgtable.h> 28 29#include "proc-macros.S" 30 31#ifndef CONFIG_SMP 32/* PTWs cacheable, inner/outer WBWA not shareable */ 33#define TCR_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA 34#else 35/* PTWs cacheable, inner/outer WBWA shareable */ 36#define TCR_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA | TCR_SHARED 37#endif 38 39#define MAIR(attr, mt) ((attr) << ((mt) * 8)) 40 41/* 42 * cpu_cache_off() 43 * 44 * Turn the CPU D-cache off. 45 */ 46ENTRY(cpu_cache_off) 47 mrs x0, sctlr_el1 48 bic x0, x0, #1 << 2 // clear SCTLR.C 49 msr sctlr_el1, x0 50 isb 51 ret 52ENDPROC(cpu_cache_off) 53 54/* 55 * cpu_reset(loc) 56 * 57 * Perform a soft reset of the system. Put the CPU into the same state 58 * as it would be if it had been reset, and branch to what would be the 59 * reset vector. It must be executed with the flat identity mapping. 60 * 61 * - loc - location to jump to for soft reset 62 */ 63 .align 5 64ENTRY(cpu_reset) 65 mrs x1, sctlr_el1 66 bic x1, x1, #1 67 msr sctlr_el1, x1 // disable the MMU 68 isb 69 ret x0 70ENDPROC(cpu_reset) 71 72/* 73 * cpu_do_idle() 74 * 75 * Idle the processor (wait for interrupt). 76 */ 77ENTRY(cpu_do_idle) 78 dsb sy // WFI may enter a low-power mode 79 wfi 80 ret 81ENDPROC(cpu_do_idle) 82 83/* 84 * cpu_switch_mm(pgd_phys, tsk) 85 * 86 * Set the translation table base pointer to be pgd_phys. 87 * 88 * - pgd_phys - physical address of new TTB 89 */ 90ENTRY(cpu_do_switch_mm) 91 mmid w1, x1 // get mm->context.id 92 bfi x0, x1, #48, #16 // set the ASID 93 msr ttbr0_el1, x0 // set TTBR0 94 isb 95 ret 96ENDPROC(cpu_do_switch_mm) 97 98cpu_name: 99 .ascii "AArch64 Processor" 100 .align 101 102 .section ".text.init", #alloc, #execinstr 103 104/* 105 * __cpu_setup 106 * 107 * Initialise the processor for turning the MMU on. Return in x0 the 108 * value of the SCTLR_EL1 register. 109 */ 110ENTRY(__cpu_setup) 111 /* 112 * Preserve the link register across the function call. 113 */ 114 mov x28, lr 115 bl __flush_dcache_all 116 mov lr, x28 117 ic iallu // I+BTB cache invalidate 118 dsb sy 119 120 mov x0, #3 << 20 121 msr cpacr_el1, x0 // Enable FP/ASIMD 122 mov x0, #1 123 msr oslar_el1, x0 // Set the debug OS lock 124 tlbi vmalle1is // invalidate I + D TLBs 125 /* 126 * Memory region attributes for LPAE: 127 * 128 * n = AttrIndx[2:0] 129 * n MAIR 130 * DEVICE_nGnRnE 000 00000000 131 * DEVICE_nGnRE 001 00000100 132 * DEVICE_GRE 010 00001100 133 * NORMAL_NC 011 01000100 134 * NORMAL 100 11111111 135 */ 136 ldr x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \ 137 MAIR(0x04, MT_DEVICE_nGnRE) | \ 138 MAIR(0x0c, MT_DEVICE_GRE) | \ 139 MAIR(0x44, MT_NORMAL_NC) | \ 140 MAIR(0xff, MT_NORMAL) 141 msr mair_el1, x5 142 /* 143 * Prepare SCTLR 144 */ 145 adr x5, crval 146 ldp w5, w6, [x5] 147 mrs x0, sctlr_el1 148 bic x0, x0, x5 // clear bits 149 orr x0, x0, x6 // set bits 150 /* 151 * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for 152 * both user and kernel. 153 */ 154 ldr x10, =TCR_TxSZ(VA_BITS) | TCR_FLAGS | TCR_IPS_40BIT | \ 155 TCR_ASID16 | (1 << 31) 156#ifdef CONFIG_ARM64_64K_PAGES 157 orr x10, x10, TCR_TG0_64K 158 orr x10, x10, TCR_TG1_64K 159#endif 160 msr tcr_el1, x10 161 ret // return to head.S 162ENDPROC(__cpu_setup) 163 164 /* 165 * n n T 166 * U E WT T UD US IHBS 167 * CE0 XWHW CZ ME TEEA S 168 * .... .IEE .... NEAI TE.I ..AD DEN0 ACAM 169 * 0011 0... 1101 ..0. ..0. 10.. .... .... < hardware reserved 170 * .... .100 .... 01.1 11.1 ..01 0001 1101 < software settings 171 */ 172 .type crval, #object 173crval: 174 .word 0x030802e2 // clear 175 .word 0x0405d11d // set 176