xref: /openbmc/linux/arch/arm64/mm/proc.S (revision 04b3c795) 
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Based on arch/arm/mm/proc.S
4 *
5 * Copyright (C) 2001 Deep Blue Solutions Ltd.
6 * Copyright (C) 2012 ARM Ltd.
7 * Author: Catalin Marinas <catalin.marinas@arm.com>
8 */
9
10#include <linux/init.h>
11#include <linux/linkage.h>
12#include <linux/pgtable.h>
13#include <asm/assembler.h>
14#include <asm/asm-offsets.h>
15#include <asm/asm_pointer_auth.h>
16#include <asm/hwcap.h>
17#include <asm/pgtable-hwdef.h>
18#include <asm/cpufeature.h>
19#include <asm/alternative.h>
20#include <asm/smp.h>
21
22#ifdef CONFIG_ARM64_64K_PAGES
23#define TCR_TG_FLAGS	TCR_TG0_64K | TCR_TG1_64K
24#elif defined(CONFIG_ARM64_16K_PAGES)
25#define TCR_TG_FLAGS	TCR_TG0_16K | TCR_TG1_16K
26#else /* CONFIG_ARM64_4K_PAGES */
27#define TCR_TG_FLAGS	TCR_TG0_4K | TCR_TG1_4K
28#endif
29
30#ifdef CONFIG_RANDOMIZE_BASE
31#define TCR_KASLR_FLAGS	TCR_NFD1
32#else
33#define TCR_KASLR_FLAGS	0
34#endif
35
36#define TCR_SMP_FLAGS	TCR_SHARED
37
38/* PTWs cacheable, inner/outer WBWA */
39#define TCR_CACHE_FLAGS	TCR_IRGN_WBWA | TCR_ORGN_WBWA
40
41#ifdef CONFIG_KASAN_SW_TAGS
42#define TCR_KASAN_FLAGS TCR_TBI1
43#else
44#define TCR_KASAN_FLAGS 0
45#endif
46
47/* Default MAIR_EL1 */
48#define MAIR_EL1_SET							\
49	(MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRnE, MT_DEVICE_nGnRnE) |	\
50	 MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRE, MT_DEVICE_nGnRE) |	\
51	 MAIR_ATTRIDX(MAIR_ATTR_DEVICE_GRE, MT_DEVICE_GRE) |		\
52	 MAIR_ATTRIDX(MAIR_ATTR_NORMAL_NC, MT_NORMAL_NC) |		\
53	 MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL) |			\
54	 MAIR_ATTRIDX(MAIR_ATTR_NORMAL_WT, MT_NORMAL_WT))
55
56#ifdef CONFIG_CPU_PM
57/**
58 * cpu_do_suspend - save CPU registers context
59 *
60 * x0: virtual address of context pointer
61 *
62 * This must be kept in sync with struct cpu_suspend_ctx in <asm/suspend.h>.
63 */
64SYM_FUNC_START(cpu_do_suspend)
65	mrs	x2, tpidr_el0
66	mrs	x3, tpidrro_el0
67	mrs	x4, contextidr_el1
68	mrs	x5, osdlr_el1
69	mrs	x6, cpacr_el1
70	mrs	x7, tcr_el1
71	mrs	x8, vbar_el1
72	mrs	x9, mdscr_el1
73	mrs	x10, oslsr_el1
74	mrs	x11, sctlr_el1
75alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
76	mrs	x12, tpidr_el1
77alternative_else
78	mrs	x12, tpidr_el2
79alternative_endif
80	mrs	x13, sp_el0
81	stp	x2, x3, [x0]
82	stp	x4, x5, [x0, #16]
83	stp	x6, x7, [x0, #32]
84	stp	x8, x9, [x0, #48]
85	stp	x10, x11, [x0, #64]
86	stp	x12, x13, [x0, #80]
87	/*
88	 * Save x18 as it may be used as a platform register, e.g. by shadow
89	 * call stack.
90	 */
91	str	x18, [x0, #96]
92	ret
93SYM_FUNC_END(cpu_do_suspend)
94
95/**
96 * cpu_do_resume - restore CPU register context
97 *
98 * x0: Address of context pointer
99 */
100	.pushsection ".idmap.text", "awx"
101SYM_FUNC_START(cpu_do_resume)
102	ldp	x2, x3, [x0]
103	ldp	x4, x5, [x0, #16]
104	ldp	x6, x8, [x0, #32]
105	ldp	x9, x10, [x0, #48]
106	ldp	x11, x12, [x0, #64]
107	ldp	x13, x14, [x0, #80]
108	/*
109	 * Restore x18, as it may be used as a platform register, and clear
110	 * the buffer to minimize the risk of exposure when used for shadow
111	 * call stack.
112	 */
113	ldr	x18, [x0, #96]
114	str	xzr, [x0, #96]
115	msr	tpidr_el0, x2
116	msr	tpidrro_el0, x3
117	msr	contextidr_el1, x4
118	msr	cpacr_el1, x6
119
120	/* Don't change t0sz here, mask those bits when restoring */
121	mrs	x7, tcr_el1
122	bfi	x8, x7, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH
123
124	msr	tcr_el1, x8
125	msr	vbar_el1, x9
126
127	/*
128	 * __cpu_setup() cleared MDSCR_EL1.MDE and friends, before unmasking
129	 * debug exceptions. By restoring MDSCR_EL1 here, we may take a debug
130	 * exception. Mask them until local_daif_restore() in cpu_suspend()
131	 * resets them.
132	 */
133	disable_daif
134	msr	mdscr_el1, x10
135
136	msr	sctlr_el1, x12
137alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
138	msr	tpidr_el1, x13
139alternative_else
140	msr	tpidr_el2, x13
141alternative_endif
142	msr	sp_el0, x14
143	/*
144	 * Restore oslsr_el1 by writing oslar_el1
145	 */
146	msr	osdlr_el1, x5
147	ubfx	x11, x11, #1, #1
148	msr	oslar_el1, x11
149	reset_pmuserenr_el0 x0			// Disable PMU access from EL0
150	reset_amuserenr_el0 x0			// Disable AMU access from EL0
151
152alternative_if ARM64_HAS_RAS_EXTN
153	msr_s	SYS_DISR_EL1, xzr
154alternative_else_nop_endif
155
156	ptrauth_keys_install_kernel_nosync x14, x1, x2, x3
157	isb
158	ret
159SYM_FUNC_END(cpu_do_resume)
160	.popsection
161#endif
162
163	.pushsection ".idmap.text", "awx"
164
165.macro	__idmap_cpu_set_reserved_ttbr1, tmp1, tmp2
166	adrp	\tmp1, empty_zero_page
167	phys_to_ttbr \tmp2, \tmp1
168	offset_ttbr1 \tmp2, \tmp1
169	msr	ttbr1_el1, \tmp2
170	isb
171	tlbi	vmalle1
172	dsb	nsh
173	isb
174.endm
175
176/*
177 * void idmap_cpu_replace_ttbr1(phys_addr_t ttbr1)
178 *
179 * This is the low-level counterpart to cpu_replace_ttbr1, and should not be
180 * called by anything else. It can only be executed from a TTBR0 mapping.
181 */
182SYM_FUNC_START(idmap_cpu_replace_ttbr1)
183	save_and_disable_daif flags=x2
184
185	__idmap_cpu_set_reserved_ttbr1 x1, x3
186
187	offset_ttbr1 x0, x3
188	msr	ttbr1_el1, x0
189	isb
190
191	restore_daif x2
192
193	ret
194SYM_FUNC_END(idmap_cpu_replace_ttbr1)
195	.popsection
196
197#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
198	.pushsection ".idmap.text", "awx"
199
200	.macro	__idmap_kpti_get_pgtable_ent, type
201	dc	cvac, cur_\()\type\()p		// Ensure any existing dirty
202	dmb	sy				// lines are written back before
203	ldr	\type, [cur_\()\type\()p]	// loading the entry
204	tbz	\type, #0, skip_\()\type	// Skip invalid and
205	tbnz	\type, #11, skip_\()\type	// non-global entries
206	.endm
207
208	.macro __idmap_kpti_put_pgtable_ent_ng, type
209	orr	\type, \type, #PTE_NG		// Same bit for blocks and pages
210	str	\type, [cur_\()\type\()p]	// Update the entry and ensure
211	dmb	sy				// that it is visible to all
212	dc	civac, cur_\()\type\()p		// CPUs.
213	.endm
214
215/*
216 * void __kpti_install_ng_mappings(int cpu, int num_cpus, phys_addr_t swapper)
217 *
218 * Called exactly once from stop_machine context by each CPU found during boot.
219 */
220__idmap_kpti_flag:
221	.long	1
222SYM_FUNC_START(idmap_kpti_install_ng_mappings)
223	cpu		.req	w0
224	num_cpus	.req	w1
225	swapper_pa	.req	x2
226	swapper_ttb	.req	x3
227	flag_ptr	.req	x4
228	cur_pgdp	.req	x5
229	end_pgdp	.req	x6
230	pgd		.req	x7
231	cur_pudp	.req	x8
232	end_pudp	.req	x9
233	pud		.req	x10
234	cur_pmdp	.req	x11
235	end_pmdp	.req	x12
236	pmd		.req	x13
237	cur_ptep	.req	x14
238	end_ptep	.req	x15
239	pte		.req	x16
240
241	mrs	swapper_ttb, ttbr1_el1
242	restore_ttbr1	swapper_ttb
243	adr	flag_ptr, __idmap_kpti_flag
244
245	cbnz	cpu, __idmap_kpti_secondary
246
247	/* We're the boot CPU. Wait for the others to catch up */
248	sevl
2491:	wfe
250	ldaxr	w17, [flag_ptr]
251	eor	w17, w17, num_cpus
252	cbnz	w17, 1b
253
254	/* We need to walk swapper, so turn off the MMU. */
255	pre_disable_mmu_workaround
256	mrs	x17, sctlr_el1
257	bic	x17, x17, #SCTLR_ELx_M
258	msr	sctlr_el1, x17
259	isb
260
261	/* Everybody is enjoying the idmap, so we can rewrite swapper. */
262	/* PGD */
263	mov	cur_pgdp, swapper_pa
264	add	end_pgdp, cur_pgdp, #(PTRS_PER_PGD * 8)
265do_pgd:	__idmap_kpti_get_pgtable_ent	pgd
266	tbnz	pgd, #1, walk_puds
267next_pgd:
268	__idmap_kpti_put_pgtable_ent_ng	pgd
269skip_pgd:
270	add	cur_pgdp, cur_pgdp, #8
271	cmp	cur_pgdp, end_pgdp
272	b.ne	do_pgd
273
274	/* Publish the updated tables and nuke all the TLBs */
275	dsb	sy
276	tlbi	vmalle1is
277	dsb	ish
278	isb
279
280	/* We're done: fire up the MMU again */
281	mrs	x17, sctlr_el1
282	orr	x17, x17, #SCTLR_ELx_M
283	msr	sctlr_el1, x17
284	isb
285
286	/*
287	 * Invalidate the local I-cache so that any instructions fetched
288	 * speculatively from the PoC are discarded, since they may have
289	 * been dynamically patched at the PoU.
290	 */
291	ic	iallu
292	dsb	nsh
293	isb
294
295	/* Set the flag to zero to indicate that we're all done */
296	str	wzr, [flag_ptr]
297	ret
298
299	/* PUD */
300walk_puds:
301	.if CONFIG_PGTABLE_LEVELS > 3
302	pte_to_phys	cur_pudp, pgd
303	add	end_pudp, cur_pudp, #(PTRS_PER_PUD * 8)
304do_pud:	__idmap_kpti_get_pgtable_ent	pud
305	tbnz	pud, #1, walk_pmds
306next_pud:
307	__idmap_kpti_put_pgtable_ent_ng	pud
308skip_pud:
309	add	cur_pudp, cur_pudp, 8
310	cmp	cur_pudp, end_pudp
311	b.ne	do_pud
312	b	next_pgd
313	.else /* CONFIG_PGTABLE_LEVELS <= 3 */
314	mov	pud, pgd
315	b	walk_pmds
316next_pud:
317	b	next_pgd
318	.endif
319
320	/* PMD */
321walk_pmds:
322	.if CONFIG_PGTABLE_LEVELS > 2
323	pte_to_phys	cur_pmdp, pud
324	add	end_pmdp, cur_pmdp, #(PTRS_PER_PMD * 8)
325do_pmd:	__idmap_kpti_get_pgtable_ent	pmd
326	tbnz	pmd, #1, walk_ptes
327next_pmd:
328	__idmap_kpti_put_pgtable_ent_ng	pmd
329skip_pmd:
330	add	cur_pmdp, cur_pmdp, #8
331	cmp	cur_pmdp, end_pmdp
332	b.ne	do_pmd
333	b	next_pud
334	.else /* CONFIG_PGTABLE_LEVELS <= 2 */
335	mov	pmd, pud
336	b	walk_ptes
337next_pmd:
338	b	next_pud
339	.endif
340
341	/* PTE */
342walk_ptes:
343	pte_to_phys	cur_ptep, pmd
344	add	end_ptep, cur_ptep, #(PTRS_PER_PTE * 8)
345do_pte:	__idmap_kpti_get_pgtable_ent	pte
346	__idmap_kpti_put_pgtable_ent_ng	pte
347skip_pte:
348	add	cur_ptep, cur_ptep, #8
349	cmp	cur_ptep, end_ptep
350	b.ne	do_pte
351	b	next_pmd
352
353	.unreq	cpu
354	.unreq	num_cpus
355	.unreq	swapper_pa
356	.unreq	cur_pgdp
357	.unreq	end_pgdp
358	.unreq	pgd
359	.unreq	cur_pudp
360	.unreq	end_pudp
361	.unreq	pud
362	.unreq	cur_pmdp
363	.unreq	end_pmdp
364	.unreq	pmd
365	.unreq	cur_ptep
366	.unreq	end_ptep
367	.unreq	pte
368
369	/* Secondary CPUs end up here */
370__idmap_kpti_secondary:
371	/* Uninstall swapper before surgery begins */
372	__idmap_cpu_set_reserved_ttbr1 x16, x17
373
374	/* Increment the flag to let the boot CPU we're ready */
3751:	ldxr	w16, [flag_ptr]
376	add	w16, w16, #1
377	stxr	w17, w16, [flag_ptr]
378	cbnz	w17, 1b
379
380	/* Wait for the boot CPU to finish messing around with swapper */
381	sevl
3821:	wfe
383	ldxr	w16, [flag_ptr]
384	cbnz	w16, 1b
385
386	/* All done, act like nothing happened */
387	offset_ttbr1 swapper_ttb, x16
388	msr	ttbr1_el1, swapper_ttb
389	isb
390	ret
391
392	.unreq	swapper_ttb
393	.unreq	flag_ptr
394SYM_FUNC_END(idmap_kpti_install_ng_mappings)
395	.popsection
396#endif
397
398/*
399 *	__cpu_setup
400 *
401 *	Initialise the processor for turning the MMU on.
402 *
403 * Output:
404 *	Return in x0 the value of the SCTLR_EL1 register.
405 */
406	.pushsection ".idmap.text", "awx"
407SYM_FUNC_START(__cpu_setup)
408	tlbi	vmalle1				// Invalidate local TLB
409	dsb	nsh
410
411	mov	x1, #3 << 20
412	msr	cpacr_el1, x1			// Enable FP/ASIMD
413	mov	x1, #1 << 12			// Reset mdscr_el1 and disable
414	msr	mdscr_el1, x1			// access to the DCC from EL0
415	isb					// Unmask debug exceptions now,
416	enable_dbg				// since this is per-cpu
417	reset_pmuserenr_el0 x1			// Disable PMU access from EL0
418	reset_amuserenr_el0 x1			// Disable AMU access from EL0
419
420	/*
421	 * Memory region attributes
422	 */
423	mov_q	x5, MAIR_EL1_SET
424	msr	mair_el1, x5
425	/*
426	 * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for
427	 * both user and kernel.
428	 */
429	mov_q	x10, TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \
430			TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \
431			TCR_TBI0 | TCR_A1 | TCR_KASAN_FLAGS
432	tcr_clear_errata_bits x10, x9, x5
433
434#ifdef CONFIG_ARM64_VA_BITS_52
435	ldr_l		x9, vabits_actual
436	sub		x9, xzr, x9
437	add		x9, x9, #64
438	tcr_set_t1sz	x10, x9
439#else
440	ldr_l		x9, idmap_t0sz
441#endif
442	tcr_set_t0sz	x10, x9
443
444	/*
445	 * Set the IPS bits in TCR_EL1.
446	 */
447	tcr_compute_pa_size x10, #TCR_IPS_SHIFT, x5, x6
448#ifdef CONFIG_ARM64_HW_AFDBM
449	/*
450	 * Enable hardware update of the Access Flags bit.
451	 * Hardware dirty bit management is enabled later,
452	 * via capabilities.
453	 */
454	mrs	x9, ID_AA64MMFR1_EL1
455	and	x9, x9, #0xf
456	cbz	x9, 1f
457	orr	x10, x10, #TCR_HA		// hardware Access flag update
4581:
459#endif	/* CONFIG_ARM64_HW_AFDBM */
460	msr	tcr_el1, x10
461	/*
462	 * Prepare SCTLR
463	 */
464	mov_q	x0, SCTLR_EL1_SET
465	ret					// return to head.S
466SYM_FUNC_END(__cpu_setup)
467